LXR linux/drivers/gpu/drm/radeon/cypress

   1/*
   2 * Copyright 2011 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __CYPRESS_DPM_H__
  24#define __CYPRESS_DPM_H__
  25
  26#include "rv770_dpm.h"
  27#include "evergreen_smc.h"
  28
  29struct evergreen_mc_reg_entry {
  30        u32 mclk_max;
  31        u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
  32};
  33
  34struct evergreen_mc_reg_table {
  35        u8 last;
  36        u8 num_entries;
  37        u16 valid_flag;
  38        struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
  39        SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
  40};
  41
  42struct evergreen_ulv_param {
  43        bool supported;
  44        struct rv7xx_pl *pl;
  45};
  46
  47struct evergreen_arb_registers {
  48        u32 mc_arb_dram_timing;
  49        u32 mc_arb_dram_timing2;
  50        u32 mc_arb_rfsh_rate;
  51        u32 mc_arb_burst_time;
  52};
  53
  54struct at {
  55        u32 rlp;
  56        u32 rmp;
  57        u32 lhp;
  58        u32 lmp;
  59};
  60
  61struct evergreen_power_info {
  62        /* must be first! */
  63        struct rv7xx_power_info rv7xx;
  64        /* flags */
  65        bool vddci_control;
  66        bool dynamic_ac_timing;
  67        bool abm;
  68        bool mcls;
  69        bool light_sleep;
  70        bool memory_transition;
  71        bool pcie_performance_request;
  72        bool pcie_performance_request_registered;
  73        bool sclk_deep_sleep;
  74        bool dll_default_on;
  75        bool ls_clock_gating;
  76        bool smu_uvd_hs;
  77        bool uvd_enabled;
  78        /* stored values */
  79        u16 acpi_vddci;
  80        u8 mvdd_high_index;
  81        u8 mvdd_low_index;
  82        u32 mclk_edc_wr_enable_threshold;
  83        struct evergreen_mc_reg_table mc_reg_table;
  84        struct atom_voltage_table vddc_voltage_table;
  85        struct atom_voltage_table vddci_voltage_table;
  86        struct evergreen_arb_registers bootup_arb_registers;
  87        struct evergreen_ulv_param ulv;
  88        struct at ats[2];
  89        /* smc offsets */
  90        u16 mc_reg_table_start;
  91        struct radeon_ps current_rps;
  92        struct rv7xx_ps current_ps;
  93        struct radeon_ps requested_rps;
  94        struct rv7xx_ps requested_ps;
  95};
  96
  97#define CYPRESS_HASI_DFLT                               400000
  98#define CYPRESS_MGCGTTLOCAL0_DFLT                       0x00000000
  99#define CYPRESS_MGCGTTLOCAL1_DFLT                       0x00000000
 100#define CYPRESS_MGCGTTLOCAL2_DFLT                       0x00000000
 101#define CYPRESS_MGCGTTLOCAL3_DFLT                       0x00000000
 102#define CYPRESS_MGCGCGTSSMCTRL_DFLT                     0x81944bc0
 103#define REDWOOD_MGCGCGTSSMCTRL_DFLT                     0x6e944040
 104#define CEDAR_MGCGCGTSSMCTRL_DFLT                       0x46944040
 105#define CYPRESS_VRC_DFLT                                0xC00033
 106
 107#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
 108#define PCIE_PERF_REQ_FORCE_LOWPOWER    1
 109#define PCIE_PERF_REQ_PECI_GEN1         2
 110#define PCIE_PERF_REQ_PECI_GEN2         3
 111#define PCIE_PERF_REQ_PECI_GEN3         4
 112
 113int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
 114                                       struct rv7xx_pl *pl,
 115                                       RV770_SMC_HW_PERFORMANCE_LEVEL *level,
 116                                       u8 watermark_level);
 117int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
 118                                    RV770_SMC_STATETABLE *table);
 119int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
 120                                        RV770_SMC_STATETABLE *table);
 121int cypress_populate_smc_initial_state(struct radeon_device *rdev,
 122                                       struct radeon_ps *radeon_initial_state,
 123                                       RV770_SMC_STATETABLE *table);
 124u32 cypress_calculate_burst_time(struct radeon_device *rdev,
 125                                 u32 engine_clock, u32 memory_clock);
 126void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
 127                                                          struct radeon_ps *radeon_new_state,
 128                                                          struct radeon_ps *radeon_current_state);
 129int cypress_upload_sw_state(struct radeon_device *rdev,
 130                            struct radeon_ps *radeon_new_state);
 131int cypress_upload_mc_reg_table(struct radeon_device *rdev,
 132                                struct radeon_ps *radeon_new_state);
 133void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
 134                                              struct radeon_ps *radeon_new_state);
 135void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
 136                                                         struct radeon_ps *radeon_new_state,
 137                                                         struct radeon_ps *radeon_current_state);
 138int cypress_construct_voltage_tables(struct radeon_device *rdev);
 139int cypress_get_mvdd_configuration(struct radeon_device *rdev);
 140void cypress_enable_spread_spectrum(struct radeon_device *rdev,
 141                                    bool enable);
 142void cypress_enable_display_gap(struct radeon_device *rdev);
 143int cypress_get_table_locations(struct radeon_device *rdev);
 144int cypress_populate_mc_reg_table(struct radeon_device *rdev,
 145                                  struct radeon_ps *radeon_boot_state);
 146void cypress_program_response_times(struct radeon_device *rdev);
 147int cypress_notify_smc_display_change(struct radeon_device *rdev,
 148                                      bool has_display);
 149void cypress_enable_sclk_control(struct radeon_device *rdev,
 150                                 bool enable);
 151void cypress_enable_mclk_control(struct radeon_device *rdev,
 152                                 bool enable);
 153void cypress_start_dpm(struct radeon_device *rdev);
 154void cypress_advertise_gen2_capability(struct radeon_device *rdev);
 155u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
 156u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
 157                                    u32 memory_clock, bool strobe_mode);
 158u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);
 159
 160#endif
 161