LXR linux/drivers/gpu/drm/radeon/radeon

   1/*
   2 * Copyright 2008 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
  28#ifndef __RADEON_ASIC_H__
  29#define __RADEON_ASIC_H__
  30
  31/*
  32 * common functions
  33 */
  34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
  47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
  49
  50/*
  51 * r100,rv100,rs100,rv200,rs200
  52 */
  53struct r100_mc_save {
  54        u32     GENMO_WT;
  55        u32     CRTC_EXT_CNTL;
  56        u32     CRTC_GEN_CNTL;
  57        u32     CRTC2_GEN_CNTL;
  58        u32     CUR_OFFSET;
  59        u32     CUR2_OFFSET;
  60};
  61int r100_init(struct radeon_device *rdev);
  62void r100_fini(struct radeon_device *rdev);
  63int r100_suspend(struct radeon_device *rdev);
  64int r100_resume(struct radeon_device *rdev);
  65void r100_vga_set_state(struct radeon_device *rdev, bool state);
  66bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  67int r100_asic_reset(struct radeon_device *rdev, bool hard);
  68u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  69void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  70uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);
  71void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
  72                            uint64_t entry);
  73void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  74int r100_irq_set(struct radeon_device *rdev);
  75int r100_irq_process(struct radeon_device *rdev);
  76void r100_fence_ring_emit(struct radeon_device *rdev,
  77                          struct radeon_fence *fence);
  78bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  79                              struct radeon_ring *cp,
  80                              struct radeon_semaphore *semaphore,
  81                              bool emit_wait);
  82int r100_cs_parse(struct radeon_cs_parser *p);
  83void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  84uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  85struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
  86                                    uint64_t src_offset,
  87                                    uint64_t dst_offset,
  88                                    unsigned num_gpu_pages,
  89                                    struct reservation_object *resv);
  90int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  91                         uint32_t tiling_flags, uint32_t pitch,
  92                         uint32_t offset, uint32_t obj_size);
  93void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  94void r100_bandwidth_update(struct radeon_device *rdev);
  95void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  96int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  97void r100_hpd_init(struct radeon_device *rdev);
  98void r100_hpd_fini(struct radeon_device *rdev);
  99bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 100void r100_hpd_set_polarity(struct radeon_device *rdev,
 101                           enum radeon_hpd_id hpd);
 102int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 103int r100_debugfs_cp_init(struct radeon_device *rdev);
 104void r100_cp_disable(struct radeon_device *rdev);
 105int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 106void r100_cp_fini(struct radeon_device *rdev);
 107int r100_pci_gart_init(struct radeon_device *rdev);
 108void r100_pci_gart_fini(struct radeon_device *rdev);
 109int r100_pci_gart_enable(struct radeon_device *rdev);
 110void r100_pci_gart_disable(struct radeon_device *rdev);
 111int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 112int r100_gui_wait_for_idle(struct radeon_device *rdev);
 113int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 114void r100_irq_disable(struct radeon_device *rdev);
 115void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 116void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 117void r100_vram_init_sizes(struct radeon_device *rdev);
 118int r100_cp_reset(struct radeon_device *rdev);
 119void r100_vga_render_disable(struct radeon_device *rdev);
 120void r100_restore_sanity(struct radeon_device *rdev);
 121int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 122                                         struct radeon_cs_packet *pkt,
 123                                         struct radeon_bo *robj);
 124int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 125                          struct radeon_cs_packet *pkt,
 126                          const unsigned *auth, unsigned n,
 127                          radeon_packet0_check_t check);
 128int r100_cs_packet_parse(struct radeon_cs_parser *p,
 129                         struct radeon_cs_packet *pkt,
 130                         unsigned idx);
 131void r100_enable_bm(struct radeon_device *rdev);
 132void r100_set_common_regs(struct radeon_device *rdev);
 133void r100_bm_disable(struct radeon_device *rdev);
 134extern bool r100_gui_idle(struct radeon_device *rdev);
 135extern void r100_pm_misc(struct radeon_device *rdev);
 136extern void r100_pm_prepare(struct radeon_device *rdev);
 137extern void r100_pm_finish(struct radeon_device *rdev);
 138extern void r100_pm_init_profile(struct radeon_device *rdev);
 139extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
 140extern void r100_page_flip(struct radeon_device *rdev, int crtc,
 141                           u64 crtc_base, bool async);
 142extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
 143extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
 144extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
 145
 146u32 r100_gfx_get_rptr(struct radeon_device *rdev,
 147                      struct radeon_ring *ring);
 148u32 r100_gfx_get_wptr(struct radeon_device *rdev,
 149                      struct radeon_ring *ring);
 150void r100_gfx_set_wptr(struct radeon_device *rdev,
 151                       struct radeon_ring *ring);
 152
 153/*
 154 * r200,rv250,rs300,rv280
 155 */
 156struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
 157                                   uint64_t src_offset,
 158                                   uint64_t dst_offset,
 159                                   unsigned num_gpu_pages,
 160                                   struct reservation_object *resv);
 161void r200_set_safe_registers(struct radeon_device *rdev);
 162
 163/*
 164 * r300,r350,rv350,rv380
 165 */
 166extern int r300_init(struct radeon_device *rdev);
 167extern void r300_fini(struct radeon_device *rdev);
 168extern int r300_suspend(struct radeon_device *rdev);
 169extern int r300_resume(struct radeon_device *rdev);
 170extern int r300_asic_reset(struct radeon_device *rdev, bool hard);
 171extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 172extern void r300_fence_ring_emit(struct radeon_device *rdev,
 173                                struct radeon_fence *fence);
 174extern int r300_cs_parse(struct radeon_cs_parser *p);
 175extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 176extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);
 177extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
 178                                     uint64_t entry);
 179extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 180extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 181extern void r300_set_reg_safe(struct radeon_device *rdev);
 182extern void r300_mc_program(struct radeon_device *rdev);
 183extern void r300_mc_init(struct radeon_device *rdev);
 184extern void r300_clock_startup(struct radeon_device *rdev);
 185extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 186extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 187extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 188extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 189extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 190extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 191
 192/*
 193 * r420,r423,rv410
 194 */
 195extern int r420_init(struct radeon_device *rdev);
 196extern void r420_fini(struct radeon_device *rdev);
 197extern int r420_suspend(struct radeon_device *rdev);
 198extern int r420_resume(struct radeon_device *rdev);
 199extern void r420_pm_init_profile(struct radeon_device *rdev);
 200extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 201extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 202extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 203extern void r420_pipes_init(struct radeon_device *rdev);
 204
 205/*
 206 * rs400,rs480
 207 */
 208extern int rs400_init(struct radeon_device *rdev);
 209extern void rs400_fini(struct radeon_device *rdev);
 210extern int rs400_suspend(struct radeon_device *rdev);
 211extern int rs400_resume(struct radeon_device *rdev);
 212void rs400_gart_tlb_flush(struct radeon_device *rdev);
 213uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);
 214void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
 215                         uint64_t entry);
 216uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 217void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 218int rs400_gart_init(struct radeon_device *rdev);
 219int rs400_gart_enable(struct radeon_device *rdev);
 220void rs400_gart_adjust_size(struct radeon_device *rdev);
 221void rs400_gart_disable(struct radeon_device *rdev);
 222void rs400_gart_fini(struct radeon_device *rdev);
 223extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
 224
 225/*
 226 * rs600.
 227 */
 228extern int rs600_asic_reset(struct radeon_device *rdev, bool hard);
 229extern int rs600_init(struct radeon_device *rdev);
 230extern void rs600_fini(struct radeon_device *rdev);
 231extern int rs600_suspend(struct radeon_device *rdev);
 232extern int rs600_resume(struct radeon_device *rdev);
 233int rs600_irq_set(struct radeon_device *rdev);
 234int rs600_irq_process(struct radeon_device *rdev);
 235void rs600_irq_disable(struct radeon_device *rdev);
 236u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 237void rs600_gart_tlb_flush(struct radeon_device *rdev);
 238uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags);
 239void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
 240                         uint64_t entry);
 241uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 242void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 243void rs600_bandwidth_update(struct radeon_device *rdev);
 244void rs600_hpd_init(struct radeon_device *rdev);
 245void rs600_hpd_fini(struct radeon_device *rdev);
 246bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 247void rs600_hpd_set_polarity(struct radeon_device *rdev,
 248                            enum radeon_hpd_id hpd);
 249extern void rs600_pm_misc(struct radeon_device *rdev);
 250extern void rs600_pm_prepare(struct radeon_device *rdev);
 251extern void rs600_pm_finish(struct radeon_device *rdev);
 252extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
 253                            u64 crtc_base, bool async);
 254extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
 255void rs600_set_safe_registers(struct radeon_device *rdev);
 256extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
 257extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 258
 259/*
 260 * rs690,rs740
 261 */
 262int rs690_init(struct radeon_device *rdev);
 263void rs690_fini(struct radeon_device *rdev);
 264int rs690_resume(struct radeon_device *rdev);
 265int rs690_suspend(struct radeon_device *rdev);
 266uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 267void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 268void rs690_bandwidth_update(struct radeon_device *rdev);
 269void rs690_line_buffer_adjust(struct radeon_device *rdev,
 270                                        struct drm_display_mode *mode1,
 271                                        struct drm_display_mode *mode2);
 272extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
 273
 274/*
 275 * rv515
 276 */
 277struct rv515_mc_save {
 278        u32 vga_render_control;
 279        u32 vga_hdp_control;
 280        bool crtc_enabled[2];
 281};
 282
 283int rv515_init(struct radeon_device *rdev);
 284void rv515_fini(struct radeon_device *rdev);
 285uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 286void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 287void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 288void rv515_bandwidth_update(struct radeon_device *rdev);
 289int rv515_resume(struct radeon_device *rdev);
 290int rv515_suspend(struct radeon_device *rdev);
 291void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 292void rv515_vga_render_disable(struct radeon_device *rdev);
 293void rv515_set_safe_registers(struct radeon_device *rdev);
 294void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
 295void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
 296void rv515_clock_startup(struct radeon_device *rdev);
 297void rv515_debugfs(struct radeon_device *rdev);
 298int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 299
 300/*
 301 * r520,rv530,rv560,rv570,r580
 302 */
 303int r520_init(struct radeon_device *rdev);
 304int r520_resume(struct radeon_device *rdev);
 305int r520_mc_wait_for_idle(struct radeon_device *rdev);
 306
 307/*
 308 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 309 */
 310int r600_init(struct radeon_device *rdev);
 311void r600_fini(struct radeon_device *rdev);
 312int r600_suspend(struct radeon_device *rdev);
 313int r600_resume(struct radeon_device *rdev);
 314void r600_vga_set_state(struct radeon_device *rdev, bool state);
 315int r600_wb_init(struct radeon_device *rdev);
 316void r600_wb_fini(struct radeon_device *rdev);
 317void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 318uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 319void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 320int r600_cs_parse(struct radeon_cs_parser *p);
 321int r600_dma_cs_parse(struct radeon_cs_parser *p);
 322void r600_fence_ring_emit(struct radeon_device *rdev,
 323                          struct radeon_fence *fence);
 324bool r600_semaphore_ring_emit(struct radeon_device *rdev,
 325                              struct radeon_ring *cp,
 326                              struct radeon_semaphore *semaphore,
 327                              bool emit_wait);
 328void r600_dma_fence_ring_emit(struct radeon_device *rdev,
 329                              struct radeon_fence *fence);
 330bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
 331                                  struct radeon_ring *ring,
 332                                  struct radeon_semaphore *semaphore,
 333                                  bool emit_wait);
 334void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 335bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 336bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 337int r600_asic_reset(struct radeon_device *rdev, bool hard);
 338int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 339                         uint32_t tiling_flags, uint32_t pitch,
 340                         uint32_t offset, uint32_t obj_size);
 341void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 342int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 343int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 344void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 345int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 346int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 347struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
 348                                     uint64_t src_offset, uint64_t dst_offset,
 349                                     unsigned num_gpu_pages,
 350                                     struct reservation_object *resv);
 351struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
 352                                   uint64_t src_offset, uint64_t dst_offset,
 353                                   unsigned num_gpu_pages,
 354                                   struct reservation_object *resv);
 355void r600_hpd_init(struct radeon_device *rdev);
 356void r600_hpd_fini(struct radeon_device *rdev);
 357bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 358void r600_hpd_set_polarity(struct radeon_device *rdev,
 359                           enum radeon_hpd_id hpd);
 360extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
 361extern bool r600_gui_idle(struct radeon_device *rdev);
 362extern void r600_pm_misc(struct radeon_device *rdev);
 363extern void r600_pm_init_profile(struct radeon_device *rdev);
 364extern void rs780_pm_init_profile(struct radeon_device *rdev);
 365extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 366extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 367extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 368extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 369extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 370bool r600_card_posted(struct radeon_device *rdev);
 371void r600_cp_stop(struct radeon_device *rdev);
 372int r600_cp_start(struct radeon_device *rdev);
 373void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
 374int r600_cp_resume(struct radeon_device *rdev);
 375void r600_cp_fini(struct radeon_device *rdev);
 376int r600_count_pipe_bits(uint32_t val);
 377int r600_mc_wait_for_idle(struct radeon_device *rdev);
 378int r600_pcie_gart_init(struct radeon_device *rdev);
 379void r600_scratch_init(struct radeon_device *rdev);
 380int r600_init_microcode(struct radeon_device *rdev);
 381u32 r600_gfx_get_rptr(struct radeon_device *rdev,
 382                      struct radeon_ring *ring);
 383u32 r600_gfx_get_wptr(struct radeon_device *rdev,
 384                      struct radeon_ring *ring);
 385void r600_gfx_set_wptr(struct radeon_device *rdev,
 386                       struct radeon_ring *ring);
 387int r600_get_allowed_info_register(struct radeon_device *rdev,
 388                                   u32 reg, u32 *val);
 389/* r600 irq */
 390int r600_irq_process(struct radeon_device *rdev);
 391int r600_irq_init(struct radeon_device *rdev);
 392void r600_irq_fini(struct radeon_device *rdev);
 393void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
 394int r600_irq_set(struct radeon_device *rdev);
 395void r600_irq_suspend(struct radeon_device *rdev);
 396void r600_disable_interrupts(struct radeon_device *rdev);
 397void r600_rlc_stop(struct radeon_device *rdev);
 398/* r600 audio */
 399void r600_audio_fini(struct radeon_device *rdev);
 400void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
 401void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
 402                                    size_t size);
 403void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
 404void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
 405int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
 406void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
 407int r600_mc_wait_for_idle(struct radeon_device *rdev);
 408u32 r600_get_xclk(struct radeon_device *rdev);
 409uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
 410int rv6xx_get_temp(struct radeon_device *rdev);
 411int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 412int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 413void r600_dpm_post_set_power_state(struct radeon_device *rdev);
 414int r600_dpm_late_enable(struct radeon_device *rdev);
 415/* r600 dma */
 416uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
 417                           struct radeon_ring *ring);
 418uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
 419                           struct radeon_ring *ring);
 420void r600_dma_set_wptr(struct radeon_device *rdev,
 421                       struct radeon_ring *ring);
 422/* rv6xx dpm */
 423int rv6xx_dpm_init(struct radeon_device *rdev);
 424int rv6xx_dpm_enable(struct radeon_device *rdev);
 425void rv6xx_dpm_disable(struct radeon_device *rdev);
 426int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
 427void rv6xx_setup_asic(struct radeon_device *rdev);
 428void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
 429void rv6xx_dpm_fini(struct radeon_device *rdev);
 430u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
 431u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
 432void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
 433                                 struct radeon_ps *ps);
 434void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 435                                                       struct seq_file *m);
 436int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
 437                                      enum radeon_dpm_forced_level level);
 438u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev);
 439u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev);
 440/* rs780 dpm */
 441int rs780_dpm_init(struct radeon_device *rdev);
 442int rs780_dpm_enable(struct radeon_device *rdev);
 443void rs780_dpm_disable(struct radeon_device *rdev);
 444int rs780_dpm_set_power_state(struct radeon_device *rdev);
 445void rs780_dpm_setup_asic(struct radeon_device *rdev);
 446void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
 447void rs780_dpm_fini(struct radeon_device *rdev);
 448u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
 449u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
 450void rs780_dpm_print_power_state(struct radeon_device *rdev,
 451                                 struct radeon_ps *ps);
 452void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 453                                                       struct seq_file *m);
 454int rs780_dpm_force_performance_level(struct radeon_device *rdev,
 455                                      enum radeon_dpm_forced_level level);
 456u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev);
 457u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev);
 458
 459/*
 460 * rv770,rv730,rv710,rv740
 461 */
 462int rv770_init(struct radeon_device *rdev);
 463void rv770_fini(struct radeon_device *rdev);
 464int rv770_suspend(struct radeon_device *rdev);
 465int rv770_resume(struct radeon_device *rdev);
 466void rv770_pm_misc(struct radeon_device *rdev);
 467void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,
 468                     bool async);
 469bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
 470void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 471void r700_cp_stop(struct radeon_device *rdev);
 472void r700_cp_fini(struct radeon_device *rdev);
 473struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
 474                                    uint64_t src_offset, uint64_t dst_offset,
 475                                    unsigned num_gpu_pages,
 476                                    struct reservation_object *resv);
 477u32 rv770_get_xclk(struct radeon_device *rdev);
 478int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 479int rv770_get_temp(struct radeon_device *rdev);
 480/* rv7xx pm */
 481int rv770_dpm_init(struct radeon_device *rdev);
 482int rv770_dpm_enable(struct radeon_device *rdev);
 483int rv770_dpm_late_enable(struct radeon_device *rdev);
 484void rv770_dpm_disable(struct radeon_device *rdev);
 485int rv770_dpm_set_power_state(struct radeon_device *rdev);
 486void rv770_dpm_setup_asic(struct radeon_device *rdev);
 487void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
 488void rv770_dpm_fini(struct radeon_device *rdev);
 489u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
 490u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
 491void rv770_dpm_print_power_state(struct radeon_device *rdev,
 492                                 struct radeon_ps *ps);
 493void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 494                                                       struct seq_file *m);
 495int rv770_dpm_force_performance_level(struct radeon_device *rdev,
 496                                      enum radeon_dpm_forced_level level);
 497bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
 498u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev);
 499u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev);
 500
 501/*
 502 * evergreen
 503 */
 504struct evergreen_mc_save {
 505        u32 vga_render_control;
 506        u32 vga_hdp_control;
 507        bool crtc_enabled[RADEON_MAX_CRTCS];
 508};
 509
 510void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
 511int evergreen_init(struct radeon_device *rdev);
 512void evergreen_fini(struct radeon_device *rdev);
 513int evergreen_suspend(struct radeon_device *rdev);
 514int evergreen_resume(struct radeon_device *rdev);
 515bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 516bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 517int evergreen_asic_reset(struct radeon_device *rdev, bool hard);
 518void evergreen_bandwidth_update(struct radeon_device *rdev);
 519void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 520void evergreen_hpd_init(struct radeon_device *rdev);
 521void evergreen_hpd_fini(struct radeon_device *rdev);
 522bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 523void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 524                                enum radeon_hpd_id hpd);
 525u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
 526int evergreen_irq_set(struct radeon_device *rdev);
 527int evergreen_irq_process(struct radeon_device *rdev);
 528extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 529extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
 530extern void evergreen_pm_misc(struct radeon_device *rdev);
 531extern void evergreen_pm_prepare(struct radeon_device *rdev);
 532extern void evergreen_pm_finish(struct radeon_device *rdev);
 533extern void sumo_pm_init_profile(struct radeon_device *rdev);
 534extern void btc_pm_init_profile(struct radeon_device *rdev);
 535int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 536int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 537extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
 538                                u64 crtc_base, bool async);
 539extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
 540extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
 541void evergreen_disable_interrupt_state(struct radeon_device *rdev);
 542int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
 543void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
 544                                   struct radeon_fence *fence);
 545void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
 546                                   struct radeon_ib *ib);
 547struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
 548                                        uint64_t src_offset, uint64_t dst_offset,
 549                                        unsigned num_gpu_pages,
 550                                        struct reservation_object *resv);
 551int evergreen_get_temp(struct radeon_device *rdev);
 552int evergreen_get_allowed_info_register(struct radeon_device *rdev,
 553                                        u32 reg, u32 *val);
 554int sumo_get_temp(struct radeon_device *rdev);
 555int tn_get_temp(struct radeon_device *rdev);
 556int cypress_dpm_init(struct radeon_device *rdev);
 557void cypress_dpm_setup_asic(struct radeon_device *rdev);
 558int cypress_dpm_enable(struct radeon_device *rdev);
 559void cypress_dpm_disable(struct radeon_device *rdev);
 560int cypress_dpm_set_power_state(struct radeon_device *rdev);
 561void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
 562void cypress_dpm_fini(struct radeon_device *rdev);
 563bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
 564int btc_dpm_init(struct radeon_device *rdev);
 565void btc_dpm_setup_asic(struct radeon_device *rdev);
 566int btc_dpm_enable(struct radeon_device *rdev);
 567void btc_dpm_disable(struct radeon_device *rdev);
 568int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
 569int btc_dpm_set_power_state(struct radeon_device *rdev);
 570void btc_dpm_post_set_power_state(struct radeon_device *rdev);
 571void btc_dpm_fini(struct radeon_device *rdev);
 572u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
 573u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
 574bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
 575void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 576                                                     struct seq_file *m);
 577u32 btc_dpm_get_current_sclk(struct radeon_device *rdev);
 578u32 btc_dpm_get_current_mclk(struct radeon_device *rdev);
 579int sumo_dpm_init(struct radeon_device *rdev);
 580int sumo_dpm_enable(struct radeon_device *rdev);
 581int sumo_dpm_late_enable(struct radeon_device *rdev);
 582void sumo_dpm_disable(struct radeon_device *rdev);
 583int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
 584int sumo_dpm_set_power_state(struct radeon_device *rdev);
 585void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
 586void sumo_dpm_setup_asic(struct radeon_device *rdev);
 587void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
 588void sumo_dpm_fini(struct radeon_device *rdev);
 589u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
 590u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
 591void sumo_dpm_print_power_state(struct radeon_device *rdev,
 592                                struct radeon_ps *ps);
 593void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 594                                                      struct seq_file *m);
 595int sumo_dpm_force_performance_level(struct radeon_device *rdev,
 596                                     enum radeon_dpm_forced_level level);
 597u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);
 598u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);
 599
 600/*
 601 * cayman
 602 */
 603void cayman_fence_ring_emit(struct radeon_device *rdev,
 604                            struct radeon_fence *fence);
 605void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
 606int cayman_init(struct radeon_device *rdev);
 607void cayman_fini(struct radeon_device *rdev);
 608int cayman_suspend(struct radeon_device *rdev);
 609int cayman_resume(struct radeon_device *rdev);
 610int cayman_asic_reset(struct radeon_device *rdev, bool hard);
 611void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 612int cayman_vm_init(struct radeon_device *rdev);
 613void cayman_vm_fini(struct radeon_device *rdev);
 614void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 615                     unsigned vm_id, uint64_t pd_addr);
 616uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
 617int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 618int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 619void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
 620                                struct radeon_ib *ib);
 621bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 622bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 623
 624void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
 625                              struct radeon_ib *ib,
 626                              uint64_t pe, uint64_t src,
 627                              unsigned count);
 628void cayman_dma_vm_write_pages(struct radeon_device *rdev,
 629                               struct radeon_ib *ib,
 630                               uint64_t pe,
 631                               uint64_t addr, unsigned count,
 632                               uint32_t incr, uint32_t flags);
 633void cayman_dma_vm_set_pages(struct radeon_device *rdev,
 634                             struct radeon_ib *ib,
 635                             uint64_t pe,
 636                             uint64_t addr, unsigned count,
 637                             uint32_t incr, uint32_t flags);
 638void cayman_dma_vm_pad_ib(struct radeon_ib *ib);
 639
 640void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 641                         unsigned vm_id, uint64_t pd_addr);
 642
 643u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
 644                        struct radeon_ring *ring);
 645u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
 646                        struct radeon_ring *ring);
 647void cayman_gfx_set_wptr(struct radeon_device *rdev,
 648                         struct radeon_ring *ring);
 649uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
 650                             struct radeon_ring *ring);
 651uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
 652                             struct radeon_ring *ring);
 653void cayman_dma_set_wptr(struct radeon_device *rdev,
 654                         struct radeon_ring *ring);
 655int cayman_get_allowed_info_register(struct radeon_device *rdev,
 656                                     u32 reg, u32 *val);
 657
 658int ni_dpm_init(struct radeon_device *rdev);
 659void ni_dpm_setup_asic(struct radeon_device *rdev);
 660int ni_dpm_enable(struct radeon_device *rdev);
 661void ni_dpm_disable(struct radeon_device *rdev);
 662int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
 663int ni_dpm_set_power_state(struct radeon_device *rdev);
 664void ni_dpm_post_set_power_state(struct radeon_device *rdev);
 665void ni_dpm_fini(struct radeon_device *rdev);
 666u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
 667u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
 668void ni_dpm_print_power_state(struct radeon_device *rdev,
 669                              struct radeon_ps *ps);
 670void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 671                                                    struct seq_file *m);
 672int ni_dpm_force_performance_level(struct radeon_device *rdev,
 673                                   enum radeon_dpm_forced_level level);
 674bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
 675u32 ni_dpm_get_current_sclk(struct radeon_device *rdev);
 676u32 ni_dpm_get_current_mclk(struct radeon_device *rdev);
 677int trinity_dpm_init(struct radeon_device *rdev);
 678int trinity_dpm_enable(struct radeon_device *rdev);
 679int trinity_dpm_late_enable(struct radeon_device *rdev);
 680void trinity_dpm_disable(struct radeon_device *rdev);
 681int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
 682int trinity_dpm_set_power_state(struct radeon_device *rdev);
 683void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
 684void trinity_dpm_setup_asic(struct radeon_device *rdev);
 685void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
 686void trinity_dpm_fini(struct radeon_device *rdev);
 687u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
 688u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
 689void trinity_dpm_print_power_state(struct radeon_device *rdev,
 690                                   struct radeon_ps *ps);
 691void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 692                                                         struct seq_file *m);
 693int trinity_dpm_force_performance_level(struct radeon_device *rdev,
 694                                        enum radeon_dpm_forced_level level);
 695void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 696u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);
 697u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);
 698int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 699
 700/* DCE6 - SI */
 701void dce6_bandwidth_update(struct radeon_device *rdev);
 702void dce6_audio_fini(struct radeon_device *rdev);
 703
 704/*
 705 * si
 706 */
 707void si_fence_ring_emit(struct radeon_device *rdev,
 708                        struct radeon_fence *fence);
 709void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
 710int si_init(struct radeon_device *rdev);
 711void si_fini(struct radeon_device *rdev);
 712int si_suspend(struct radeon_device *rdev);
 713int si_resume(struct radeon_device *rdev);
 714bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 715bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 716int si_asic_reset(struct radeon_device *rdev, bool hard);
 717void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 718int si_irq_set(struct radeon_device *rdev);
 719int si_irq_process(struct radeon_device *rdev);
 720int si_vm_init(struct radeon_device *rdev);
 721void si_vm_fini(struct radeon_device *rdev);
 722void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 723                 unsigned vm_id, uint64_t pd_addr);
 724int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 725struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
 726                                 uint64_t src_offset, uint64_t dst_offset,
 727                                 unsigned num_gpu_pages,
 728                                 struct reservation_object *resv);
 729
 730void si_dma_vm_copy_pages(struct radeon_device *rdev,
 731                          struct radeon_ib *ib,
 732                          uint64_t pe, uint64_t src,
 733                          unsigned count);
 734void si_dma_vm_write_pages(struct radeon_device *rdev,
 735                           struct radeon_ib *ib,
 736                           uint64_t pe,
 737                           uint64_t addr, unsigned count,
 738                           uint32_t incr, uint32_t flags);
 739void si_dma_vm_set_pages(struct radeon_device *rdev,
 740                         struct radeon_ib *ib,
 741                         uint64_t pe,
 742                         uint64_t addr, unsigned count,
 743                         uint32_t incr, uint32_t flags);
 744
 745void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 746                     unsigned vm_id, uint64_t pd_addr);
 747u32 si_get_xclk(struct radeon_device *rdev);
 748uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
 749int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 750int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 751int si_get_temp(struct radeon_device *rdev);
 752int si_get_allowed_info_register(struct radeon_device *rdev,
 753                                 u32 reg, u32 *val);
 754int si_dpm_init(struct radeon_device *rdev);
 755void si_dpm_setup_asic(struct radeon_device *rdev);
 756int si_dpm_enable(struct radeon_device *rdev);
 757int si_dpm_late_enable(struct radeon_device *rdev);
 758void si_dpm_disable(struct radeon_device *rdev);
 759int si_dpm_pre_set_power_state(struct radeon_device *rdev);
 760int si_dpm_set_power_state(struct radeon_device *rdev);
 761void si_dpm_post_set_power_state(struct radeon_device *rdev);
 762void si_dpm_fini(struct radeon_device *rdev);
 763void si_dpm_display_configuration_changed(struct radeon_device *rdev);
 764void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 765                                                    struct seq_file *m);
 766int si_dpm_force_performance_level(struct radeon_device *rdev,
 767                                   enum radeon_dpm_forced_level level);
 768int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
 769                                                 u32 *speed);
 770int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
 771                                                 u32 speed);
 772u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);
 773void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
 774u32 si_dpm_get_current_sclk(struct radeon_device *rdev);
 775u32 si_dpm_get_current_mclk(struct radeon_device *rdev);
 776
 777/* DCE8 - CIK */
 778void dce8_bandwidth_update(struct radeon_device *rdev);
 779
 780/*
 781 * cik
 782 */
 783uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
 784u32 cik_get_xclk(struct radeon_device *rdev);
 785uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 786void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 787int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 788int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 789void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
 790                              struct radeon_fence *fence);
 791bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
 792                                  struct radeon_ring *ring,
 793                                  struct radeon_semaphore *semaphore,
 794                                  bool emit_wait);
 795void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 796struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
 797                                  uint64_t src_offset, uint64_t dst_offset,
 798                                  unsigned num_gpu_pages,
 799                                  struct reservation_object *resv);
 800struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
 801                                    uint64_t src_offset, uint64_t dst_offset,
 802                                    unsigned num_gpu_pages,
 803                                    struct reservation_object *resv);
 804int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 805int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 806bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 807void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
 808                             struct radeon_fence *fence);
 809void cik_fence_compute_ring_emit(struct radeon_device *rdev,
 810                                 struct radeon_fence *fence);
 811bool cik_semaphore_ring_emit(struct radeon_device *rdev,
 812                             struct radeon_ring *cp,
 813                             struct radeon_semaphore *semaphore,
 814                             bool emit_wait);
 815void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
 816int cik_init(struct radeon_device *rdev);
 817void cik_fini(struct radeon_device *rdev);
 818int cik_suspend(struct radeon_device *rdev);
 819int cik_resume(struct radeon_device *rdev);
 820bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 821int cik_asic_reset(struct radeon_device *rdev, bool hard);
 822void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 823int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 824int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 825int cik_irq_set(struct radeon_device *rdev);
 826int cik_irq_process(struct radeon_device *rdev);
 827int cik_vm_init(struct radeon_device *rdev);
 828void cik_vm_fini(struct radeon_device *rdev);
 829void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 830                  unsigned vm_id, uint64_t pd_addr);
 831
 832void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
 833                            struct radeon_ib *ib,
 834                            uint64_t pe, uint64_t src,
 835                            unsigned count);
 836void cik_sdma_vm_write_pages(struct radeon_device *rdev,
 837                             struct radeon_ib *ib,
 838                             uint64_t pe,
 839                             uint64_t addr, unsigned count,
 840                             uint32_t incr, uint32_t flags);
 841void cik_sdma_vm_set_pages(struct radeon_device *rdev,
 842                           struct radeon_ib *ib,
 843                           uint64_t pe,
 844                           uint64_t addr, unsigned count,
 845                           uint32_t incr, uint32_t flags);
 846void cik_sdma_vm_pad_ib(struct radeon_ib *ib);
 847
 848void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 849                      unsigned vm_id, uint64_t pd_addr);
 850int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 851u32 cik_gfx_get_rptr(struct radeon_device *rdev,
 852                     struct radeon_ring *ring);
 853u32 cik_gfx_get_wptr(struct radeon_device *rdev,
 854                     struct radeon_ring *ring);
 855void cik_gfx_set_wptr(struct radeon_device *rdev,
 856                      struct radeon_ring *ring);
 857u32 cik_compute_get_rptr(struct radeon_device *rdev,
 858                         struct radeon_ring *ring);
 859u32 cik_compute_get_wptr(struct radeon_device *rdev,
 860                         struct radeon_ring *ring);
 861void cik_compute_set_wptr(struct radeon_device *rdev,
 862                          struct radeon_ring *ring);
 863u32 cik_sdma_get_rptr(struct radeon_device *rdev,
 864                      struct radeon_ring *ring);
 865u32 cik_sdma_get_wptr(struct radeon_device *rdev,
 866                      struct radeon_ring *ring);
 867void cik_sdma_set_wptr(struct radeon_device *rdev,
 868                       struct radeon_ring *ring);
 869int ci_get_temp(struct radeon_device *rdev);
 870int kv_get_temp(struct radeon_device *rdev);
 871int cik_get_allowed_info_register(struct radeon_device *rdev,
 872                                  u32 reg, u32 *val);
 873
 874int ci_dpm_init(struct radeon_device *rdev);
 875int ci_dpm_enable(struct radeon_device *rdev);
 876int ci_dpm_late_enable(struct radeon_device *rdev);
 877void ci_dpm_disable(struct radeon_device *rdev);
 878int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
 879int ci_dpm_set_power_state(struct radeon_device *rdev);
 880void ci_dpm_post_set_power_state(struct radeon_device *rdev);
 881void ci_dpm_setup_asic(struct radeon_device *rdev);
 882void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
 883void ci_dpm_fini(struct radeon_device *rdev);
 884u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
 885u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
 886void ci_dpm_print_power_state(struct radeon_device *rdev,
 887                              struct radeon_ps *ps);
 888void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 889                                                    struct seq_file *m);
 890int ci_dpm_force_performance_level(struct radeon_device *rdev,
 891                                   enum radeon_dpm_forced_level level);
 892bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
 893void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 894u32 ci_dpm_get_current_sclk(struct radeon_device *rdev);
 895u32 ci_dpm_get_current_mclk(struct radeon_device *rdev);
 896
 897int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
 898                                                 u32 *speed);
 899int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
 900                                                 u32 speed);
 901u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev);
 902void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
 903
 904int kv_dpm_init(struct radeon_device *rdev);
 905int kv_dpm_enable(struct radeon_device *rdev);
 906int kv_dpm_late_enable(struct radeon_device *rdev);
 907void kv_dpm_disable(struct radeon_device *rdev);
 908int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
 909int kv_dpm_set_power_state(struct radeon_device *rdev);
 910void kv_dpm_post_set_power_state(struct radeon_device *rdev);
 911void kv_dpm_setup_asic(struct radeon_device *rdev);
 912void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
 913void kv_dpm_fini(struct radeon_device *rdev);
 914u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
 915u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
 916void kv_dpm_print_power_state(struct radeon_device *rdev,
 917                              struct radeon_ps *ps);
 918void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 919                                                    struct seq_file *m);
 920int kv_dpm_force_performance_level(struct radeon_device *rdev,
 921                                   enum radeon_dpm_forced_level level);
 922void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 923void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 924u32 kv_dpm_get_current_sclk(struct radeon_device *rdev);
 925u32 kv_dpm_get_current_mclk(struct radeon_device *rdev);
 926
 927/* uvd v1.0 */
 928uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
 929                           struct radeon_ring *ring);
 930uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
 931                           struct radeon_ring *ring);
 932void uvd_v1_0_set_wptr(struct radeon_device *rdev,
 933                       struct radeon_ring *ring);
 934int uvd_v1_0_resume(struct radeon_device *rdev);
 935
 936int uvd_v1_0_init(struct radeon_device *rdev);
 937void uvd_v1_0_fini(struct radeon_device *rdev);
 938int uvd_v1_0_start(struct radeon_device *rdev);
 939void uvd_v1_0_stop(struct radeon_device *rdev);
 940
 941int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 942void uvd_v1_0_fence_emit(struct radeon_device *rdev,
 943                         struct radeon_fence *fence);
 944int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 945bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
 946                             struct radeon_ring *ring,
 947                             struct radeon_semaphore *semaphore,
 948                             bool emit_wait);
 949void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 950
 951/* uvd v2.2 */
 952int uvd_v2_2_resume(struct radeon_device *rdev);
 953void uvd_v2_2_fence_emit(struct radeon_device *rdev,
 954                         struct radeon_fence *fence);
 955bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
 956                             struct radeon_ring *ring,
 957                             struct radeon_semaphore *semaphore,
 958                             bool emit_wait);
 959
 960/* uvd v3.1 */
 961bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
 962                             struct radeon_ring *ring,
 963                             struct radeon_semaphore *semaphore,
 964                             bool emit_wait);
 965
 966/* uvd v4.2 */
 967int uvd_v4_2_resume(struct radeon_device *rdev);
 968
 969/* vce v1.0 */
 970uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
 971                           struct radeon_ring *ring);
 972uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
 973                           struct radeon_ring *ring);
 974void vce_v1_0_set_wptr(struct radeon_device *rdev,
 975                       struct radeon_ring *ring);
 976int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data);
 977unsigned vce_v1_0_bo_size(struct radeon_device *rdev);
 978int vce_v1_0_resume(struct radeon_device *rdev);
 979int vce_v1_0_init(struct radeon_device *rdev);
 980int vce_v1_0_start(struct radeon_device *rdev);
 981
 982/* vce v2.0 */
 983unsigned vce_v2_0_bo_size(struct radeon_device *rdev);
 984int vce_v2_0_resume(struct radeon_device *rdev);
 985
 986#endif
 987