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27#include <drm/drm_device.h>
28#include <drm/drm_pci.h>
29#include <drm/radeon_drm.h>
30
31#include "radeon.h"
32
33#include "atom.h"
34#include "atom-bits.h"
35#include "radeon_asic.h"
36
37extern void
38radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
39 uint32_t supported_device, u16 caps);
40
41
42extern void
43radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
44 uint32_t supported_device);
45
46union atom_supported_devices {
47 struct _ATOM_SUPPORTED_DEVICES_INFO info;
48 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
49 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
50};
51
52static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
53 ATOM_GPIO_I2C_ASSIGMENT *gpio,
54 u8 index)
55{
56
57 if ((rdev->family == CHIP_R420) ||
58 (rdev->family == CHIP_R423) ||
59 (rdev->family == CHIP_RV410)) {
60 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
61 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
62 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
63 gpio->ucClkMaskShift = 0x19;
64 gpio->ucDataMaskShift = 0x18;
65 }
66 }
67
68
69 if (ASIC_IS_DCE4(rdev)) {
70 if ((index == 7) &&
71 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
72 (gpio->sucI2cId.ucAccess == 0)) {
73 gpio->sucI2cId.ucAccess = 0x97;
74 gpio->ucDataMaskShift = 8;
75 gpio->ucDataEnShift = 8;
76 gpio->ucDataY_Shift = 8;
77 gpio->ucDataA_Shift = 8;
78 }
79 }
80
81
82 if (ASIC_IS_DCE3(rdev)) {
83 if ((index == 4) &&
84 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
85 (gpio->sucI2cId.ucAccess == 0x94))
86 gpio->sucI2cId.ucAccess = 0x14;
87 }
88}
89
90static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
91{
92 struct radeon_i2c_bus_rec i2c;
93
94 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
95
96 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
97 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
98 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
99 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
100 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
101 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
102 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
103 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
104 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
105 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
106 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
107 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
108 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
109 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
110 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
111 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
112
113 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
114 i2c.hw_capable = true;
115 else
116 i2c.hw_capable = false;
117
118 if (gpio->sucI2cId.ucAccess == 0xa0)
119 i2c.mm_i2c = true;
120 else
121 i2c.mm_i2c = false;
122
123 i2c.i2c_id = gpio->sucI2cId.ucAccess;
124
125 if (i2c.mask_clk_reg)
126 i2c.valid = true;
127 else
128 i2c.valid = false;
129
130 return i2c;
131}
132
133static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
134 uint8_t id)
135{
136 struct atom_context *ctx = rdev->mode_info.atom_context;
137 ATOM_GPIO_I2C_ASSIGMENT *gpio;
138 struct radeon_i2c_bus_rec i2c;
139 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
140 struct _ATOM_GPIO_I2C_INFO *i2c_info;
141 uint16_t data_offset, size;
142 int i, num_indices;
143
144 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
145 i2c.valid = false;
146
147 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
148 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
149
150 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
151 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
152
153 gpio = &i2c_info->asGPIO_Info[0];
154 for (i = 0; i < num_indices; i++) {
155
156 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
157
158 if (gpio->sucI2cId.ucAccess == id) {
159 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
160 break;
161 }
162 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
163 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
164 }
165 }
166
167 return i2c;
168}
169
170void radeon_atombios_i2c_init(struct radeon_device *rdev)
171{
172 struct atom_context *ctx = rdev->mode_info.atom_context;
173 ATOM_GPIO_I2C_ASSIGMENT *gpio;
174 struct radeon_i2c_bus_rec i2c;
175 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
176 struct _ATOM_GPIO_I2C_INFO *i2c_info;
177 uint16_t data_offset, size;
178 int i, num_indices;
179 char stmp[32];
180
181 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
182 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
183
184 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
185 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
186
187 gpio = &i2c_info->asGPIO_Info[0];
188 for (i = 0; i < num_indices; i++) {
189 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
190
191 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
192
193 if (i2c.valid) {
194 sprintf(stmp, "0x%x", i2c.i2c_id);
195 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
196 }
197 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
198 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
199 }
200 }
201}
202
203struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
204 u8 id)
205{
206 struct atom_context *ctx = rdev->mode_info.atom_context;
207 struct radeon_gpio_rec gpio;
208 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
209 struct _ATOM_GPIO_PIN_LUT *gpio_info;
210 ATOM_GPIO_PIN_ASSIGNMENT *pin;
211 u16 data_offset, size;
212 int i, num_indices;
213
214 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
215 gpio.valid = false;
216
217 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
218 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
219
220 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
221 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
222
223 pin = gpio_info->asGPIO_Pin;
224 for (i = 0; i < num_indices; i++) {
225 if (id == pin->ucGPIO_ID) {
226 gpio.id = pin->ucGPIO_ID;
227 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
228 gpio.shift = pin->ucGpioPinBitShift;
229 gpio.mask = (1 << pin->ucGpioPinBitShift);
230 gpio.valid = true;
231 break;
232 }
233 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
234 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
235 }
236 }
237
238 return gpio;
239}
240
241static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
242 struct radeon_gpio_rec *gpio)
243{
244 struct radeon_hpd hpd;
245 u32 reg;
246
247 memset(&hpd, 0, sizeof(struct radeon_hpd));
248
249 if (ASIC_IS_DCE6(rdev))
250 reg = SI_DC_GPIO_HPD_A;
251 else if (ASIC_IS_DCE4(rdev))
252 reg = EVERGREEN_DC_GPIO_HPD_A;
253 else
254 reg = AVIVO_DC_GPIO_HPD_A;
255
256 hpd.gpio = *gpio;
257 if (gpio->reg == reg) {
258 switch(gpio->mask) {
259 case (1 << 0):
260 hpd.hpd = RADEON_HPD_1;
261 break;
262 case (1 << 8):
263 hpd.hpd = RADEON_HPD_2;
264 break;
265 case (1 << 16):
266 hpd.hpd = RADEON_HPD_3;
267 break;
268 case (1 << 24):
269 hpd.hpd = RADEON_HPD_4;
270 break;
271 case (1 << 26):
272 hpd.hpd = RADEON_HPD_5;
273 break;
274 case (1 << 28):
275 hpd.hpd = RADEON_HPD_6;
276 break;
277 default:
278 hpd.hpd = RADEON_HPD_NONE;
279 break;
280 }
281 } else
282 hpd.hpd = RADEON_HPD_NONE;
283 return hpd;
284}
285
286static bool radeon_atom_apply_quirks(struct drm_device *dev,
287 uint32_t supported_device,
288 int *connector_type,
289 struct radeon_i2c_bus_rec *i2c_bus,
290 uint16_t *line_mux,
291 struct radeon_hpd *hpd)
292{
293
294
295 if ((dev->pdev->device == 0x791e) &&
296 (dev->pdev->subsystem_vendor == 0x1043) &&
297 (dev->pdev->subsystem_device == 0x826d)) {
298 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
299 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
300 *connector_type = DRM_MODE_CONNECTOR_DVID;
301 }
302
303
304 if ((dev->pdev->device == 0x7941) &&
305 (dev->pdev->subsystem_vendor == 0x1849) &&
306 (dev->pdev->subsystem_device == 0x7941)) {
307 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
308 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
309 *connector_type = DRM_MODE_CONNECTOR_DVID;
310 }
311
312
313 if ((dev->pdev->device == 0x796e) &&
314 (dev->pdev->subsystem_vendor == 0x1462) &&
315 (dev->pdev->subsystem_device == 0x7302)) {
316 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
317 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
318 return false;
319 }
320
321
322 if ((dev->pdev->device == 0x7941) &&
323 (dev->pdev->subsystem_vendor == 0x147b) &&
324 (dev->pdev->subsystem_device == 0x2412)) {
325 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
326 return false;
327 }
328
329
330 if ((dev->pdev->device == 0x5653) &&
331 (dev->pdev->subsystem_vendor == 0x1462) &&
332 (dev->pdev->subsystem_device == 0x0291)) {
333 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
334 i2c_bus->valid = false;
335 *line_mux = 53;
336 }
337 }
338
339
340 if ((dev->pdev->device == 0x7146) &&
341 (dev->pdev->subsystem_vendor == 0x17af) &&
342 (dev->pdev->subsystem_device == 0x2058)) {
343 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
344 return false;
345 }
346
347
348 if ((dev->pdev->device == 0x7142) &&
349 (dev->pdev->subsystem_vendor == 0x1458) &&
350 (dev->pdev->subsystem_device == 0x2134)) {
351 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 return false;
353 }
354
355
356
357 if ((dev->pdev->device == 0x71C5) &&
358 (dev->pdev->subsystem_vendor == 0x106b) &&
359 (dev->pdev->subsystem_device == 0x0080)) {
360 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
361 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
362 return false;
363 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
364 *line_mux = 0x90;
365 }
366
367
368 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
369 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
370 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
371 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
372 }
373
374
375 if ((dev->pdev->device == 0x9598) &&
376 (dev->pdev->subsystem_vendor == 0x1043) &&
377 (dev->pdev->subsystem_device == 0x01da)) {
378 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
379 *connector_type = DRM_MODE_CONNECTOR_DVII;
380 }
381 }
382
383
384 if ((dev->pdev->device == 0x9598) &&
385 (dev->pdev->subsystem_vendor == 0x1043) &&
386 (dev->pdev->subsystem_device == 0x01e4)) {
387 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
388 *connector_type = DRM_MODE_CONNECTOR_DVII;
389 }
390 }
391
392
393 if ((dev->pdev->device == 0x95C5) &&
394 (dev->pdev->subsystem_vendor == 0x1043) &&
395 (dev->pdev->subsystem_device == 0x01e2)) {
396 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
397 *connector_type = DRM_MODE_CONNECTOR_DVII;
398 }
399 }
400
401
402
403
404 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
405 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
406 *connector_type = DRM_MODE_CONNECTOR_VGA;
407 *line_mux = 0;
408 }
409 }
410
411
412
413
414
415
416
417
418
419
420 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
421 (dev->pdev->subsystem_vendor == 0x1025) &&
422 (dev->pdev->subsystem_device == 0x013c)) {
423 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
424 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
425
426 *connector_type = DRM_MODE_CONNECTOR_DVID;
427 return false;
428 }
429 }
430
431
432
433
434 if ((dev->pdev->device == 0x9498) &&
435 (dev->pdev->subsystem_vendor == 0x1682) &&
436 (dev->pdev->subsystem_device == 0x2452) &&
437 (i2c_bus->valid == false) &&
438 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
439 struct radeon_device *rdev = dev->dev_private;
440 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
441 }
442
443
444 if (((dev->pdev->device == 0x9802) ||
445 (dev->pdev->device == 0x9805) ||
446 (dev->pdev->device == 0x9806)) &&
447 (dev->pdev->subsystem_vendor == 0x1734) &&
448 (dev->pdev->subsystem_device == 0x11bd)) {
449 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
450 *connector_type = DRM_MODE_CONNECTOR_DVII;
451 *line_mux = 0x3103;
452 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
453 *connector_type = DRM_MODE_CONNECTOR_DVII;
454 }
455 }
456
457 return true;
458}
459
460static const int supported_devices_connector_convert[] = {
461 DRM_MODE_CONNECTOR_Unknown,
462 DRM_MODE_CONNECTOR_VGA,
463 DRM_MODE_CONNECTOR_DVII,
464 DRM_MODE_CONNECTOR_DVID,
465 DRM_MODE_CONNECTOR_DVIA,
466 DRM_MODE_CONNECTOR_SVIDEO,
467 DRM_MODE_CONNECTOR_Composite,
468 DRM_MODE_CONNECTOR_LVDS,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_HDMIA,
472 DRM_MODE_CONNECTOR_HDMIB,
473 DRM_MODE_CONNECTOR_Unknown,
474 DRM_MODE_CONNECTOR_Unknown,
475 DRM_MODE_CONNECTOR_9PinDIN,
476 DRM_MODE_CONNECTOR_DisplayPort
477};
478
479static const uint16_t supported_devices_connector_object_id_convert[] = {
480 CONNECTOR_OBJECT_ID_NONE,
481 CONNECTOR_OBJECT_ID_VGA,
482 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
483 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D,
484 CONNECTOR_OBJECT_ID_VGA,
485 CONNECTOR_OBJECT_ID_COMPOSITE,
486 CONNECTOR_OBJECT_ID_SVIDEO,
487 CONNECTOR_OBJECT_ID_LVDS,
488 CONNECTOR_OBJECT_ID_9PIN_DIN,
489 CONNECTOR_OBJECT_ID_9PIN_DIN,
490 CONNECTOR_OBJECT_ID_DISPLAYPORT,
491 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
492 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
493 CONNECTOR_OBJECT_ID_SVIDEO
494};
495
496static const int object_connector_convert[] = {
497 DRM_MODE_CONNECTOR_Unknown,
498 DRM_MODE_CONNECTOR_DVII,
499 DRM_MODE_CONNECTOR_DVII,
500 DRM_MODE_CONNECTOR_DVID,
501 DRM_MODE_CONNECTOR_DVID,
502 DRM_MODE_CONNECTOR_VGA,
503 DRM_MODE_CONNECTOR_Composite,
504 DRM_MODE_CONNECTOR_SVIDEO,
505 DRM_MODE_CONNECTOR_Unknown,
506 DRM_MODE_CONNECTOR_Unknown,
507 DRM_MODE_CONNECTOR_9PinDIN,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_HDMIA,
510 DRM_MODE_CONNECTOR_HDMIB,
511 DRM_MODE_CONNECTOR_LVDS,
512 DRM_MODE_CONNECTOR_9PinDIN,
513 DRM_MODE_CONNECTOR_Unknown,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_DisplayPort,
517 DRM_MODE_CONNECTOR_eDP,
518 DRM_MODE_CONNECTOR_Unknown
519};
520
521bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
522{
523 struct radeon_device *rdev = dev->dev_private;
524 struct radeon_mode_info *mode_info = &rdev->mode_info;
525 struct atom_context *ctx = mode_info->atom_context;
526 int index = GetIndexIntoMasterTable(DATA, Object_Header);
527 u16 size, data_offset;
528 u8 frev, crev;
529 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
530 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
531 ATOM_OBJECT_TABLE *router_obj;
532 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
533 ATOM_OBJECT_HEADER *obj_header;
534 int i, j, k, path_size, device_support;
535 int connector_type;
536 u16 igp_lane_info, conn_id, connector_object_id;
537 struct radeon_i2c_bus_rec ddc_bus;
538 struct radeon_router router;
539 struct radeon_gpio_rec gpio;
540 struct radeon_hpd hpd;
541
542 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
543 return false;
544
545 if (crev < 2)
546 return false;
547
548 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
549 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
550 (ctx->bios + data_offset +
551 le16_to_cpu(obj_header->usDisplayPathTableOffset));
552 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
553 (ctx->bios + data_offset +
554 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
555 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
558 router_obj = (ATOM_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usRouterObjectTableOffset));
561 device_support = le16_to_cpu(obj_header->usDeviceSupport);
562
563 path_size = 0;
564 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
565 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
566 ATOM_DISPLAY_OBJECT_PATH *path;
567 addr += path_size;
568 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
569 path_size += le16_to_cpu(path->usSize);
570
571 if (device_support & le16_to_cpu(path->usDeviceTag)) {
572 uint8_t con_obj_id, con_obj_num, con_obj_type;
573
574 con_obj_id =
575 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
576 >> OBJECT_ID_SHIFT;
577 con_obj_num =
578 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
579 >> ENUM_ID_SHIFT;
580 con_obj_type =
581 (le16_to_cpu(path->usConnObjectId) &
582 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
583
584
585 if (le16_to_cpu(path->usDeviceTag) ==
586 ATOM_DEVICE_CV_SUPPORT)
587 continue;
588
589
590 if ((rdev->flags & RADEON_IS_IGP) &&
591 (con_obj_id ==
592 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
593 uint16_t igp_offset = 0;
594 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
595
596 index =
597 GetIndexIntoMasterTable(DATA,
598 IntegratedSystemInfo);
599
600 if (atom_parse_data_header(ctx, index, &size, &frev,
601 &crev, &igp_offset)) {
602
603 if (crev >= 2) {
604 igp_obj =
605 (ATOM_INTEGRATED_SYSTEM_INFO_V2
606 *) (ctx->bios + igp_offset);
607
608 if (igp_obj) {
609 uint32_t slot_config, ct;
610
611 if (con_obj_num == 1)
612 slot_config =
613 igp_obj->
614 ulDDISlot1Config;
615 else
616 slot_config =
617 igp_obj->
618 ulDDISlot2Config;
619
620 ct = (slot_config >> 16) & 0xff;
621 connector_type =
622 object_connector_convert
623 [ct];
624 connector_object_id = ct;
625 igp_lane_info =
626 slot_config & 0xffff;
627 } else
628 continue;
629 } else
630 continue;
631 } else {
632 igp_lane_info = 0;
633 connector_type =
634 object_connector_convert[con_obj_id];
635 connector_object_id = con_obj_id;
636 }
637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
643
644 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
645 continue;
646
647 router.ddc_valid = false;
648 router.cd_valid = false;
649 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
650 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
651
652 grph_obj_id =
653 (le16_to_cpu(path->usGraphicObjIds[j]) &
654 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
655 grph_obj_num =
656 (le16_to_cpu(path->usGraphicObjIds[j]) &
657 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
658 grph_obj_type =
659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
661
662 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
663 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
664 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
665 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
666 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
667 (ctx->bios + data_offset +
668 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
669 ATOM_ENCODER_CAP_RECORD *cap_record;
670 u16 caps = 0;
671
672 while (record->ucRecordSize > 0 &&
673 record->ucRecordType > 0 &&
674 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
675 switch (record->ucRecordType) {
676 case ATOM_ENCODER_CAP_RECORD_TYPE:
677 cap_record =(ATOM_ENCODER_CAP_RECORD *)
678 record;
679 caps = le16_to_cpu(cap_record->usEncoderCap);
680 break;
681 }
682 record = (ATOM_COMMON_RECORD_HEADER *)
683 ((char *)record + record->ucRecordSize);
684 }
685 radeon_add_atom_encoder(dev,
686 encoder_obj,
687 le16_to_cpu
688 (path->
689 usDeviceTag),
690 caps);
691 }
692 }
693 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
694 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
695 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
696 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
697 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
698 (ctx->bios + data_offset +
699 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
700 ATOM_I2C_RECORD *i2c_record;
701 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
702 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
703 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
704 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
705 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
706 (ctx->bios + data_offset +
707 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
708 u8 *num_dst_objs = (u8 *)
709 ((u8 *)router_src_dst_table + 1 +
710 (router_src_dst_table->ucNumberOfSrc * 2));
711 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
712 int enum_id;
713
714 router.router_id = router_obj_id;
715 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
716 if (le16_to_cpu(path->usConnObjectId) ==
717 le16_to_cpu(dst_objs[enum_id]))
718 break;
719 }
720
721 while (record->ucRecordSize > 0 &&
722 record->ucRecordType > 0 &&
723 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
724 switch (record->ucRecordType) {
725 case ATOM_I2C_RECORD_TYPE:
726 i2c_record =
727 (ATOM_I2C_RECORD *)
728 record;
729 i2c_config =
730 (ATOM_I2C_ID_CONFIG_ACCESS *)
731 &i2c_record->sucI2cId;
732 router.i2c_info =
733 radeon_lookup_i2c_gpio(rdev,
734 i2c_config->
735 ucAccess);
736 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
737 break;
738 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
739 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
740 record;
741 router.ddc_valid = true;
742 router.ddc_mux_type = ddc_path->ucMuxType;
743 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
744 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
745 break;
746 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
747 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
748 record;
749 router.cd_valid = true;
750 router.cd_mux_type = cd_path->ucMuxType;
751 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
752 router.cd_mux_state = cd_path->ucMuxState[enum_id];
753 break;
754 }
755 record = (ATOM_COMMON_RECORD_HEADER *)
756 ((char *)record + record->ucRecordSize);
757 }
758 }
759 }
760 }
761 }
762
763
764 ddc_bus.valid = false;
765 hpd.hpd = RADEON_HPD_NONE;
766 if ((le16_to_cpu(path->usDeviceTag) &
767 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
768 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
769 if (le16_to_cpu(path->usConnObjectId) ==
770 le16_to_cpu(con_obj->asObjects[j].
771 usObjectID)) {
772 ATOM_COMMON_RECORD_HEADER
773 *record =
774 (ATOM_COMMON_RECORD_HEADER
775 *)
776 (ctx->bios + data_offset +
777 le16_to_cpu(con_obj->
778 asObjects[j].
779 usRecordOffset));
780 ATOM_I2C_RECORD *i2c_record;
781 ATOM_HPD_INT_RECORD *hpd_record;
782 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
783
784 while (record->ucRecordSize > 0 &&
785 record->ucRecordType > 0 &&
786 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
787 switch (record->ucRecordType) {
788 case ATOM_I2C_RECORD_TYPE:
789 i2c_record =
790 (ATOM_I2C_RECORD *)
791 record;
792 i2c_config =
793 (ATOM_I2C_ID_CONFIG_ACCESS *)
794 &i2c_record->sucI2cId;
795 ddc_bus = radeon_lookup_i2c_gpio(rdev,
796 i2c_config->
797 ucAccess);
798 break;
799 case ATOM_HPD_INT_RECORD_TYPE:
800 hpd_record =
801 (ATOM_HPD_INT_RECORD *)
802 record;
803 gpio = radeon_atombios_lookup_gpio(rdev,
804 hpd_record->ucHPDIntGPIOID);
805 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
806 hpd.plugged_state = hpd_record->ucPlugged_PinState;
807 break;
808 }
809 record =
810 (ATOM_COMMON_RECORD_HEADER
811 *) ((char *)record
812 +
813 record->
814 ucRecordSize);
815 }
816 break;
817 }
818 }
819 }
820
821
822 ddc_bus.hpd = hpd.hpd;
823
824 conn_id = le16_to_cpu(path->usConnObjectId);
825
826 if (!radeon_atom_apply_quirks
827 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
828 &ddc_bus, &conn_id, &hpd))
829 continue;
830
831 radeon_add_atom_connector(dev,
832 conn_id,
833 le16_to_cpu(path->
834 usDeviceTag),
835 connector_type, &ddc_bus,
836 igp_lane_info,
837 connector_object_id,
838 &hpd,
839 &router);
840
841 }
842 }
843
844 radeon_link_encoder_connector(dev);
845
846 radeon_setup_mst_connector(dev);
847 return true;
848}
849
850static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
851 int connector_type,
852 uint16_t devices)
853{
854 struct radeon_device *rdev = dev->dev_private;
855
856 if (rdev->flags & RADEON_IS_IGP) {
857 return supported_devices_connector_object_id_convert
858 [connector_type];
859 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
860 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
861 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
862 struct radeon_mode_info *mode_info = &rdev->mode_info;
863 struct atom_context *ctx = mode_info->atom_context;
864 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
865 uint16_t size, data_offset;
866 uint8_t frev, crev;
867 ATOM_XTMDS_INFO *xtmds;
868
869 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
870 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
871
872 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
873 if (connector_type == DRM_MODE_CONNECTOR_DVII)
874 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
875 else
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
877 } else {
878 if (connector_type == DRM_MODE_CONNECTOR_DVII)
879 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
880 else
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
882 }
883 } else
884 return supported_devices_connector_object_id_convert
885 [connector_type];
886 } else {
887 return supported_devices_connector_object_id_convert
888 [connector_type];
889 }
890}
891
892struct bios_connector {
893 bool valid;
894 uint16_t line_mux;
895 uint16_t devices;
896 int connector_type;
897 struct radeon_i2c_bus_rec ddc_bus;
898 struct radeon_hpd hpd;
899};
900
901bool radeon_get_atom_connector_info_from_supported_devices_table(struct
902 drm_device
903 *dev)
904{
905 struct radeon_device *rdev = dev->dev_private;
906 struct radeon_mode_info *mode_info = &rdev->mode_info;
907 struct atom_context *ctx = mode_info->atom_context;
908 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
909 uint16_t size, data_offset;
910 uint8_t frev, crev;
911 uint16_t device_support;
912 uint8_t dac;
913 union atom_supported_devices *supported_devices;
914 int i, j, max_device;
915 struct bios_connector *bios_connectors;
916 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
917 struct radeon_router router;
918
919 router.ddc_valid = false;
920 router.cd_valid = false;
921
922 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
923 if (!bios_connectors)
924 return false;
925
926 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
927 &data_offset)) {
928 kfree(bios_connectors);
929 return false;
930 }
931
932 supported_devices =
933 (union atom_supported_devices *)(ctx->bios + data_offset);
934
935 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
936
937 if (frev > 1)
938 max_device = ATOM_MAX_SUPPORTED_DEVICE;
939 else
940 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
941
942 for (i = 0; i < max_device; i++) {
943 ATOM_CONNECTOR_INFO_I2C ci =
944 supported_devices->info.asConnInfo[i];
945
946 bios_connectors[i].valid = false;
947
948 if (!(device_support & (1 << i))) {
949 continue;
950 }
951
952 if (i == ATOM_DEVICE_CV_INDEX) {
953 DRM_DEBUG_KMS("Skipping Component Video\n");
954 continue;
955 }
956
957 bios_connectors[i].connector_type =
958 supported_devices_connector_convert[ci.sucConnectorInfo.
959 sbfAccess.
960 bfConnectorType];
961
962 if (bios_connectors[i].connector_type ==
963 DRM_MODE_CONNECTOR_Unknown)
964 continue;
965
966 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
967
968 bios_connectors[i].line_mux =
969 ci.sucI2cId.ucAccess;
970
971
972 if (i == ATOM_DEVICE_TV1_INDEX) {
973 bios_connectors[i].ddc_bus.valid = false;
974 bios_connectors[i].line_mux = 50;
975 } else if (i == ATOM_DEVICE_TV2_INDEX) {
976 bios_connectors[i].ddc_bus.valid = false;
977 bios_connectors[i].line_mux = 51;
978 } else if (i == ATOM_DEVICE_CV_INDEX) {
979 bios_connectors[i].ddc_bus.valid = false;
980 bios_connectors[i].line_mux = 52;
981 } else
982 bios_connectors[i].ddc_bus =
983 radeon_lookup_i2c_gpio(rdev,
984 bios_connectors[i].line_mux);
985
986 if ((crev > 1) && (frev > 1)) {
987 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
988 switch (isb) {
989 case 0x4:
990 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
991 break;
992 case 0xa:
993 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
994 break;
995 default:
996 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
997 break;
998 }
999 } else {
1000 if (i == ATOM_DEVICE_DFP1_INDEX)
1001 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1002 else if (i == ATOM_DEVICE_DFP2_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1004 else
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1006 }
1007
1008
1009
1010
1011
1012 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1013 bios_connectors[i].connector_type =
1014 DRM_MODE_CONNECTOR_VGA;
1015
1016 if (!radeon_atom_apply_quirks
1017 (dev, (1 << i), &bios_connectors[i].connector_type,
1018 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1019 &bios_connectors[i].hpd))
1020 continue;
1021
1022 bios_connectors[i].valid = true;
1023 bios_connectors[i].devices = (1 << i);
1024
1025 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1026 radeon_add_atom_encoder(dev,
1027 radeon_get_encoder_enum(dev,
1028 (1 << i),
1029 dac),
1030 (1 << i),
1031 0);
1032 else
1033 radeon_add_legacy_encoder(dev,
1034 radeon_get_encoder_enum(dev,
1035 (1 << i),
1036 dac),
1037 (1 << i));
1038 }
1039
1040
1041 for (i = 0; i < max_device; i++) {
1042 if (bios_connectors[i].valid) {
1043 for (j = 0; j < max_device; j++) {
1044 if (bios_connectors[j].valid && (i != j)) {
1045 if (bios_connectors[i].line_mux ==
1046 bios_connectors[j].line_mux) {
1047
1048 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1049 bios_connectors[i].line_mux = 53;
1050 bios_connectors[i].ddc_bus.valid = false;
1051 continue;
1052 }
1053 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1054 bios_connectors[j].line_mux = 53;
1055 bios_connectors[j].ddc_bus.valid = false;
1056 continue;
1057 }
1058
1059 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1060 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1061 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1063 bios_connectors[i].devices |=
1064 bios_connectors[j].devices;
1065 bios_connectors[i].connector_type =
1066 DRM_MODE_CONNECTOR_DVII;
1067 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1068 bios_connectors[i].hpd =
1069 bios_connectors[j].hpd;
1070 bios_connectors[j].valid = false;
1071 }
1072 }
1073 }
1074 }
1075 }
1076 }
1077
1078
1079 for (i = 0; i < max_device; i++) {
1080 if (bios_connectors[i].valid) {
1081 uint16_t connector_object_id =
1082 atombios_get_connector_object_id(dev,
1083 bios_connectors[i].connector_type,
1084 bios_connectors[i].devices);
1085 radeon_add_atom_connector(dev,
1086 bios_connectors[i].line_mux,
1087 bios_connectors[i].devices,
1088 bios_connectors[i].
1089 connector_type,
1090 &bios_connectors[i].ddc_bus,
1091 0,
1092 connector_object_id,
1093 &bios_connectors[i].hpd,
1094 &router);
1095 }
1096 }
1097
1098 radeon_link_encoder_connector(dev);
1099
1100 kfree(bios_connectors);
1101 return true;
1102}
1103
1104union firmware_info {
1105 ATOM_FIRMWARE_INFO info;
1106 ATOM_FIRMWARE_INFO_V1_2 info_12;
1107 ATOM_FIRMWARE_INFO_V1_3 info_13;
1108 ATOM_FIRMWARE_INFO_V1_4 info_14;
1109 ATOM_FIRMWARE_INFO_V2_1 info_21;
1110 ATOM_FIRMWARE_INFO_V2_2 info_22;
1111};
1112
1113union igp_info {
1114 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1115 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1116 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1117 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1118 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1119};
1120
1121static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1122{
1123 struct radeon_mode_info *mode_info = &rdev->mode_info;
1124 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1125 union igp_info *igp_info;
1126 u8 frev, crev;
1127 u16 data_offset;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1132 data_offset);
1133 rdev->clock.vco_freq =
1134 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1135 }
1136}
1137
1138bool radeon_atom_get_clock_info(struct drm_device *dev)
1139{
1140 struct radeon_device *rdev = dev->dev_private;
1141 struct radeon_mode_info *mode_info = &rdev->mode_info;
1142 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1143 union firmware_info *firmware_info;
1144 uint8_t frev, crev;
1145 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1146 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1147 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1148 struct radeon_pll *spll = &rdev->clock.spll;
1149 struct radeon_pll *mpll = &rdev->clock.mpll;
1150 uint16_t data_offset;
1151
1152 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1153 &frev, &crev, &data_offset)) {
1154 firmware_info =
1155 (union firmware_info *)(mode_info->atom_context->bios +
1156 data_offset);
1157
1158 p1pll->reference_freq =
1159 le16_to_cpu(firmware_info->info.usReferenceClock);
1160 p1pll->reference_div = 0;
1161
1162 if ((frev < 2) && (crev < 2))
1163 p1pll->pll_out_min =
1164 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1165 else
1166 p1pll->pll_out_min =
1167 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1168 p1pll->pll_out_max =
1169 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1170
1171 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1172 p1pll->lcd_pll_out_min =
1173 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1174 if (p1pll->lcd_pll_out_min == 0)
1175 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1176 p1pll->lcd_pll_out_max =
1177 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1178 if (p1pll->lcd_pll_out_max == 0)
1179 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1180 } else {
1181 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1182 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1183 }
1184
1185 if (p1pll->pll_out_min == 0) {
1186 if (ASIC_IS_AVIVO(rdev))
1187 p1pll->pll_out_min = 64800;
1188 else
1189 p1pll->pll_out_min = 20000;
1190 }
1191
1192 p1pll->pll_in_min =
1193 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1194 p1pll->pll_in_max =
1195 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1196
1197 *p2pll = *p1pll;
1198
1199
1200 if (ASIC_IS_DCE4(rdev))
1201 spll->reference_freq =
1202 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1203 else
1204 spll->reference_freq =
1205 le16_to_cpu(firmware_info->info.usReferenceClock);
1206 spll->reference_div = 0;
1207
1208 spll->pll_out_min =
1209 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1210 spll->pll_out_max =
1211 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1212
1213
1214 if (spll->pll_out_min == 0) {
1215 if (ASIC_IS_AVIVO(rdev))
1216 spll->pll_out_min = 64800;
1217 else
1218 spll->pll_out_min = 20000;
1219 }
1220
1221 spll->pll_in_min =
1222 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1223 spll->pll_in_max =
1224 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1225
1226
1227 if (ASIC_IS_DCE4(rdev))
1228 mpll->reference_freq =
1229 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1230 else
1231 mpll->reference_freq =
1232 le16_to_cpu(firmware_info->info.usReferenceClock);
1233 mpll->reference_div = 0;
1234
1235 mpll->pll_out_min =
1236 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1237 mpll->pll_out_max =
1238 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1239
1240
1241 if (mpll->pll_out_min == 0) {
1242 if (ASIC_IS_AVIVO(rdev))
1243 mpll->pll_out_min = 64800;
1244 else
1245 mpll->pll_out_min = 20000;
1246 }
1247
1248 mpll->pll_in_min =
1249 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1250 mpll->pll_in_max =
1251 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1252
1253 rdev->clock.default_sclk =
1254 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1255 rdev->clock.default_mclk =
1256 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1257
1258 if (ASIC_IS_DCE4(rdev)) {
1259 rdev->clock.default_dispclk =
1260 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1261 if (rdev->clock.default_dispclk == 0) {
1262 if (ASIC_IS_DCE6(rdev))
1263 rdev->clock.default_dispclk = 60000;
1264 else if (ASIC_IS_DCE5(rdev))
1265 rdev->clock.default_dispclk = 54000;
1266 else
1267 rdev->clock.default_dispclk = 60000;
1268 }
1269
1270 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1271 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1272 rdev->clock.default_dispclk / 100);
1273 rdev->clock.default_dispclk = 60000;
1274 }
1275 rdev->clock.dp_extclk =
1276 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1277 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1278 }
1279 *dcpll = *p1pll;
1280
1281 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1282 if (rdev->clock.max_pixel_clock == 0)
1283 rdev->clock.max_pixel_clock = 40000;
1284
1285
1286 rdev->mode_info.firmware_flags =
1287 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1288
1289 if (ASIC_IS_DCE8(rdev))
1290 rdev->clock.vco_freq =
1291 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1292 else if (ASIC_IS_DCE5(rdev))
1293 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1294 else if (ASIC_IS_DCE41(rdev))
1295 radeon_atombios_get_dentist_vco_freq(rdev);
1296 else
1297 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1298
1299 if (rdev->clock.vco_freq == 0)
1300 rdev->clock.vco_freq = 360000;
1301
1302 return true;
1303 }
1304
1305 return false;
1306}
1307
1308bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1309{
1310 struct radeon_mode_info *mode_info = &rdev->mode_info;
1311 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1312 union igp_info *igp_info;
1313 u8 frev, crev;
1314 u16 data_offset;
1315
1316
1317 if (rdev->family == CHIP_RS600)
1318 return false;
1319
1320 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1321 &frev, &crev, &data_offset)) {
1322 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1323 data_offset);
1324 switch (crev) {
1325 case 1:
1326 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1327 return true;
1328 break;
1329 case 2:
1330 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1331 return true;
1332 break;
1333 default:
1334 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1335 break;
1336 }
1337 }
1338 return false;
1339}
1340
1341bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1342 struct radeon_encoder_int_tmds *tmds)
1343{
1344 struct drm_device *dev = encoder->base.dev;
1345 struct radeon_device *rdev = dev->dev_private;
1346 struct radeon_mode_info *mode_info = &rdev->mode_info;
1347 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1348 uint16_t data_offset;
1349 struct _ATOM_TMDS_INFO *tmds_info;
1350 uint8_t frev, crev;
1351 uint16_t maxfreq;
1352 int i;
1353
1354 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1355 &frev, &crev, &data_offset)) {
1356 tmds_info =
1357 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1358 data_offset);
1359
1360 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1361 for (i = 0; i < 4; i++) {
1362 tmds->tmds_pll[i].freq =
1363 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1364 tmds->tmds_pll[i].value =
1365 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1366 tmds->tmds_pll[i].value |=
1367 (tmds_info->asMiscInfo[i].
1368 ucPLL_VCO_Gain & 0x3f) << 6;
1369 tmds->tmds_pll[i].value |=
1370 (tmds_info->asMiscInfo[i].
1371 ucPLL_DutyCycle & 0xf) << 12;
1372 tmds->tmds_pll[i].value |=
1373 (tmds_info->asMiscInfo[i].
1374 ucPLL_VoltageSwing & 0xf) << 16;
1375
1376 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1377 tmds->tmds_pll[i].freq,
1378 tmds->tmds_pll[i].value);
1379
1380 if (maxfreq == tmds->tmds_pll[i].freq) {
1381 tmds->tmds_pll[i].freq = 0xffffffff;
1382 break;
1383 }
1384 }
1385 return true;
1386 }
1387 return false;
1388}
1389
1390bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1391 struct radeon_atom_ss *ss,
1392 int id)
1393{
1394 struct radeon_mode_info *mode_info = &rdev->mode_info;
1395 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1396 uint16_t data_offset, size;
1397 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1398 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1399 uint8_t frev, crev;
1400 int i, num_indices;
1401
1402 memset(ss, 0, sizeof(struct radeon_atom_ss));
1403 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1404 &frev, &crev, &data_offset)) {
1405 ss_info =
1406 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1407
1408 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1409 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1410 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1411 ((u8 *)&ss_info->asSS_Info[0]);
1412 for (i = 0; i < num_indices; i++) {
1413 if (ss_assign->ucSS_Id == id) {
1414 ss->percentage =
1415 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1416 ss->type = ss_assign->ucSpreadSpectrumType;
1417 ss->step = ss_assign->ucSS_Step;
1418 ss->delay = ss_assign->ucSS_Delay;
1419 ss->range = ss_assign->ucSS_Range;
1420 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1421 return true;
1422 }
1423 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1424 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1425 }
1426 }
1427 return false;
1428}
1429
1430static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1431 struct radeon_atom_ss *ss,
1432 int id)
1433{
1434 struct radeon_mode_info *mode_info = &rdev->mode_info;
1435 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1436 u16 data_offset, size;
1437 union igp_info *igp_info;
1438 u8 frev, crev;
1439 u16 percentage = 0, rate = 0;
1440
1441
1442 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1443 &frev, &crev, &data_offset)) {
1444 igp_info = (union igp_info *)
1445 (mode_info->atom_context->bios + data_offset);
1446 switch (crev) {
1447 case 6:
1448 switch (id) {
1449 case ASIC_INTERNAL_SS_ON_TMDS:
1450 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1451 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1452 break;
1453 case ASIC_INTERNAL_SS_ON_HDMI:
1454 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1455 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1456 break;
1457 case ASIC_INTERNAL_SS_ON_LVDS:
1458 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1459 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1460 break;
1461 }
1462 break;
1463 case 7:
1464 switch (id) {
1465 case ASIC_INTERNAL_SS_ON_TMDS:
1466 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1467 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1468 break;
1469 case ASIC_INTERNAL_SS_ON_HDMI:
1470 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1471 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1472 break;
1473 case ASIC_INTERNAL_SS_ON_LVDS:
1474 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1475 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1476 break;
1477 }
1478 break;
1479 case 8:
1480 switch (id) {
1481 case ASIC_INTERNAL_SS_ON_TMDS:
1482 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1483 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1484 break;
1485 case ASIC_INTERNAL_SS_ON_HDMI:
1486 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1487 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1488 break;
1489 case ASIC_INTERNAL_SS_ON_LVDS:
1490 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1491 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1492 break;
1493 }
1494 break;
1495 default:
1496 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1497 break;
1498 }
1499 if (percentage)
1500 ss->percentage = percentage;
1501 if (rate)
1502 ss->rate = rate;
1503 }
1504}
1505
1506union asic_ss_info {
1507 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1508 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1509 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1510};
1511
1512union asic_ss_assignment {
1513 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1514 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1515 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1516};
1517
1518bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1519 struct radeon_atom_ss *ss,
1520 int id, u32 clock)
1521{
1522 struct radeon_mode_info *mode_info = &rdev->mode_info;
1523 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1524 uint16_t data_offset, size;
1525 union asic_ss_info *ss_info;
1526 union asic_ss_assignment *ss_assign;
1527 uint8_t frev, crev;
1528 int i, num_indices;
1529
1530 if (id == ASIC_INTERNAL_MEMORY_SS) {
1531 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1532 return false;
1533 }
1534 if (id == ASIC_INTERNAL_ENGINE_SS) {
1535 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1536 return false;
1537 }
1538
1539 memset(ss, 0, sizeof(struct radeon_atom_ss));
1540 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1541 &frev, &crev, &data_offset)) {
1542
1543 ss_info =
1544 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1545
1546 switch (frev) {
1547 case 1:
1548 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1549 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1550
1551 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1552 for (i = 0; i < num_indices; i++) {
1553 if ((ss_assign->v1.ucClockIndication == id) &&
1554 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1555 ss->percentage =
1556 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1557 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1558 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1559 ss->percentage_divider = 100;
1560 return true;
1561 }
1562 ss_assign = (union asic_ss_assignment *)
1563 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1564 }
1565 break;
1566 case 2:
1567 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1568 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1569 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1570 for (i = 0; i < num_indices; i++) {
1571 if ((ss_assign->v2.ucClockIndication == id) &&
1572 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1573 ss->percentage =
1574 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1575 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1576 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1577 ss->percentage_divider = 100;
1578 if ((crev == 2) &&
1579 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1580 (id == ASIC_INTERNAL_MEMORY_SS)))
1581 ss->rate /= 100;
1582 return true;
1583 }
1584 ss_assign = (union asic_ss_assignment *)
1585 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1586 }
1587 break;
1588 case 3:
1589 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1590 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1591 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1592 for (i = 0; i < num_indices; i++) {
1593 if ((ss_assign->v3.ucClockIndication == id) &&
1594 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1595 ss->percentage =
1596 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1597 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1598 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1599 if (ss_assign->v3.ucSpreadSpectrumMode &
1600 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1601 ss->percentage_divider = 1000;
1602 else
1603 ss->percentage_divider = 100;
1604 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1605 (id == ASIC_INTERNAL_MEMORY_SS))
1606 ss->rate /= 100;
1607 if (rdev->flags & RADEON_IS_IGP)
1608 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1609 return true;
1610 }
1611 ss_assign = (union asic_ss_assignment *)
1612 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1613 }
1614 break;
1615 default:
1616 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1617 break;
1618 }
1619
1620 }
1621 return false;
1622}
1623
1624union lvds_info {
1625 struct _ATOM_LVDS_INFO info;
1626 struct _ATOM_LVDS_INFO_V12 info_12;
1627};
1628
1629struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1630 radeon_encoder
1631 *encoder)
1632{
1633 struct drm_device *dev = encoder->base.dev;
1634 struct radeon_device *rdev = dev->dev_private;
1635 struct radeon_mode_info *mode_info = &rdev->mode_info;
1636 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1637 uint16_t data_offset, misc;
1638 union lvds_info *lvds_info;
1639 uint8_t frev, crev;
1640 struct radeon_encoder_atom_dig *lvds = NULL;
1641 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1642
1643 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1644 &frev, &crev, &data_offset)) {
1645 lvds_info =
1646 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1647 lvds =
1648 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1649
1650 if (!lvds)
1651 return NULL;
1652
1653 lvds->native_mode.clock =
1654 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1655 lvds->native_mode.hdisplay =
1656 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1657 lvds->native_mode.vdisplay =
1658 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1659 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1660 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1661 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1662 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1663 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1664 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1665 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1666 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1667 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1668 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1669 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1670 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1671 lvds->panel_pwr_delay =
1672 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1673 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1674
1675 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1676 if (misc & ATOM_VSYNC_POLARITY)
1677 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1678 if (misc & ATOM_HSYNC_POLARITY)
1679 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1680 if (misc & ATOM_COMPOSITESYNC)
1681 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1682 if (misc & ATOM_INTERLACE)
1683 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1684 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1685 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1686
1687 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1688 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1689
1690
1691 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1692
1693 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1694
1695 encoder->native_mode = lvds->native_mode;
1696
1697 if (encoder_enum == 2)
1698 lvds->linkb = true;
1699 else
1700 lvds->linkb = false;
1701
1702
1703 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1704 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1705 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1706 bool bad_record = false;
1707 u8 *record;
1708
1709 if ((frev == 1) && (crev < 2))
1710
1711 record = (u8 *)(mode_info->atom_context->bios +
1712 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1713 else
1714
1715 record = (u8 *)(mode_info->atom_context->bios +
1716 data_offset +
1717 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1718 while (*record != ATOM_RECORD_END_TYPE) {
1719 switch (*record) {
1720 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1721 record += sizeof(ATOM_PATCH_RECORD_MODE);
1722 break;
1723 case LCD_RTS_RECORD_TYPE:
1724 record += sizeof(ATOM_LCD_RTS_RECORD);
1725 break;
1726 case LCD_CAP_RECORD_TYPE:
1727 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1728 break;
1729 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1730 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1731 if (fake_edid_record->ucFakeEDIDLength) {
1732 struct edid *edid;
1733 int edid_size =
1734 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1735 edid = kmalloc(edid_size, GFP_KERNEL);
1736 if (edid) {
1737 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1738 fake_edid_record->ucFakeEDIDLength);
1739
1740 if (drm_edid_is_valid(edid)) {
1741 rdev->mode_info.bios_hardcoded_edid = edid;
1742 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1743 } else
1744 kfree(edid);
1745 }
1746 }
1747 record += fake_edid_record->ucFakeEDIDLength ?
1748 fake_edid_record->ucFakeEDIDLength + 2 :
1749 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1750 break;
1751 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1752 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1753 lvds->native_mode.width_mm = panel_res_record->usHSize;
1754 lvds->native_mode.height_mm = panel_res_record->usVSize;
1755 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1756 break;
1757 default:
1758 DRM_ERROR("Bad LCD record %d\n", *record);
1759 bad_record = true;
1760 break;
1761 }
1762 if (bad_record)
1763 break;
1764 }
1765 }
1766 }
1767 return lvds;
1768}
1769
1770struct radeon_encoder_primary_dac *
1771radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1772{
1773 struct drm_device *dev = encoder->base.dev;
1774 struct radeon_device *rdev = dev->dev_private;
1775 struct radeon_mode_info *mode_info = &rdev->mode_info;
1776 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1777 uint16_t data_offset;
1778 struct _COMPASSIONATE_DATA *dac_info;
1779 uint8_t frev, crev;
1780 uint8_t bg, dac;
1781 struct radeon_encoder_primary_dac *p_dac = NULL;
1782
1783 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1784 &frev, &crev, &data_offset)) {
1785 dac_info = (struct _COMPASSIONATE_DATA *)
1786 (mode_info->atom_context->bios + data_offset);
1787
1788 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1789
1790 if (!p_dac)
1791 return NULL;
1792
1793 bg = dac_info->ucDAC1_BG_Adjustment;
1794 dac = dac_info->ucDAC1_DAC_Adjustment;
1795 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1796
1797 }
1798 return p_dac;
1799}
1800
1801bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1802 struct drm_display_mode *mode)
1803{
1804 struct radeon_mode_info *mode_info = &rdev->mode_info;
1805 ATOM_ANALOG_TV_INFO *tv_info;
1806 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1807 ATOM_DTD_FORMAT *dtd_timings;
1808 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1809 u8 frev, crev;
1810 u16 data_offset, misc;
1811
1812 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1813 &frev, &crev, &data_offset))
1814 return false;
1815
1816 switch (crev) {
1817 case 1:
1818 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1819 if (index >= MAX_SUPPORTED_TV_TIMING)
1820 return false;
1821
1822 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1823 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1824 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1825 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1826 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1827
1828 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1829 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1830 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1831 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1832 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1833
1834 mode->flags = 0;
1835 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1836 if (misc & ATOM_VSYNC_POLARITY)
1837 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1838 if (misc & ATOM_HSYNC_POLARITY)
1839 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1840 if (misc & ATOM_COMPOSITESYNC)
1841 mode->flags |= DRM_MODE_FLAG_CSYNC;
1842 if (misc & ATOM_INTERLACE)
1843 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1844 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1845 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1846
1847 mode->crtc_clock = mode->clock =
1848 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1849
1850 if (index == 1) {
1851
1852 mode->crtc_htotal -= 1;
1853 mode->crtc_vtotal -= 1;
1854 }
1855 break;
1856 case 2:
1857 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1858 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1859 return false;
1860
1861 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1862 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1863 le16_to_cpu(dtd_timings->usHBlanking_Time);
1864 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1865 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1866 le16_to_cpu(dtd_timings->usHSyncOffset);
1867 mode->crtc_hsync_end = mode->crtc_hsync_start +
1868 le16_to_cpu(dtd_timings->usHSyncWidth);
1869
1870 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1871 le16_to_cpu(dtd_timings->usVBlanking_Time);
1872 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1873 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1874 le16_to_cpu(dtd_timings->usVSyncOffset);
1875 mode->crtc_vsync_end = mode->crtc_vsync_start +
1876 le16_to_cpu(dtd_timings->usVSyncWidth);
1877
1878 mode->flags = 0;
1879 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1880 if (misc & ATOM_VSYNC_POLARITY)
1881 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1882 if (misc & ATOM_HSYNC_POLARITY)
1883 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1884 if (misc & ATOM_COMPOSITESYNC)
1885 mode->flags |= DRM_MODE_FLAG_CSYNC;
1886 if (misc & ATOM_INTERLACE)
1887 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1888 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1889 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1890
1891 mode->crtc_clock = mode->clock =
1892 le16_to_cpu(dtd_timings->usPixClk) * 10;
1893 break;
1894 }
1895 return true;
1896}
1897
1898enum radeon_tv_std
1899radeon_atombios_get_tv_info(struct radeon_device *rdev)
1900{
1901 struct radeon_mode_info *mode_info = &rdev->mode_info;
1902 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1903 uint16_t data_offset;
1904 uint8_t frev, crev;
1905 struct _ATOM_ANALOG_TV_INFO *tv_info;
1906 enum radeon_tv_std tv_std = TV_STD_NTSC;
1907
1908 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1909 &frev, &crev, &data_offset)) {
1910
1911 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1912 (mode_info->atom_context->bios + data_offset);
1913
1914 switch (tv_info->ucTV_BootUpDefaultStandard) {
1915 case ATOM_TV_NTSC:
1916 tv_std = TV_STD_NTSC;
1917 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1918 break;
1919 case ATOM_TV_NTSCJ:
1920 tv_std = TV_STD_NTSC_J;
1921 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1922 break;
1923 case ATOM_TV_PAL:
1924 tv_std = TV_STD_PAL;
1925 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1926 break;
1927 case ATOM_TV_PALM:
1928 tv_std = TV_STD_PAL_M;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1930 break;
1931 case ATOM_TV_PALN:
1932 tv_std = TV_STD_PAL_N;
1933 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1934 break;
1935 case ATOM_TV_PALCN:
1936 tv_std = TV_STD_PAL_CN;
1937 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1938 break;
1939 case ATOM_TV_PAL60:
1940 tv_std = TV_STD_PAL_60;
1941 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1942 break;
1943 case ATOM_TV_SECAM:
1944 tv_std = TV_STD_SECAM;
1945 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1946 break;
1947 default:
1948 tv_std = TV_STD_NTSC;
1949 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1950 break;
1951 }
1952 }
1953 return tv_std;
1954}
1955
1956struct radeon_encoder_tv_dac *
1957radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1958{
1959 struct drm_device *dev = encoder->base.dev;
1960 struct radeon_device *rdev = dev->dev_private;
1961 struct radeon_mode_info *mode_info = &rdev->mode_info;
1962 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1963 uint16_t data_offset;
1964 struct _COMPASSIONATE_DATA *dac_info;
1965 uint8_t frev, crev;
1966 uint8_t bg, dac;
1967 struct radeon_encoder_tv_dac *tv_dac = NULL;
1968
1969 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1970 &frev, &crev, &data_offset)) {
1971
1972 dac_info = (struct _COMPASSIONATE_DATA *)
1973 (mode_info->atom_context->bios + data_offset);
1974
1975 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1976
1977 if (!tv_dac)
1978 return NULL;
1979
1980 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1981 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1982 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1983
1984 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1985 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1986 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1987
1988 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1989 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1990 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1991
1992 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1993 }
1994 return tv_dac;
1995}
1996
1997static const char *thermal_controller_names[] = {
1998 "NONE",
1999 "lm63",
2000 "adm1032",
2001 "adm1030",
2002 "max6649",
2003 "lm63",
2004 "f75375",
2005 "asc7xxx",
2006};
2007
2008static const char *pp_lib_thermal_controller_names[] = {
2009 "NONE",
2010 "lm63",
2011 "adm1032",
2012 "adm1030",
2013 "max6649",
2014 "lm63",
2015 "f75375",
2016 "RV6xx",
2017 "RV770",
2018 "adt7473",
2019 "NONE",
2020 "External GPIO",
2021 "Evergreen",
2022 "emc2103",
2023 "Sumo",
2024 "Northern Islands",
2025 "Southern Islands",
2026 "lm96163",
2027 "Sea Islands",
2028};
2029
2030union power_info {
2031 struct _ATOM_POWERPLAY_INFO info;
2032 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2033 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2034 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2035 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2036 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2037};
2038
2039union pplib_clock_info {
2040 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2041 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2042 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2043 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2044 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2045 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2046};
2047
2048union pplib_power_state {
2049 struct _ATOM_PPLIB_STATE v1;
2050 struct _ATOM_PPLIB_STATE_V2 v2;
2051};
2052
2053static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2054 int state_index,
2055 u32 misc, u32 misc2)
2056{
2057 rdev->pm.power_state[state_index].misc = misc;
2058 rdev->pm.power_state[state_index].misc2 = misc2;
2059
2060 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_POWERSAVE;
2063 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2064 rdev->pm.power_state[state_index].type =
2065 POWER_STATE_TYPE_BATTERY;
2066 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BATTERY;
2069 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_BALANCED;
2072 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2073 rdev->pm.power_state[state_index].type =
2074 POWER_STATE_TYPE_PERFORMANCE;
2075 rdev->pm.power_state[state_index].flags &=
2076 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2077 }
2078 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2079 rdev->pm.power_state[state_index].type =
2080 POWER_STATE_TYPE_BALANCED;
2081 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2082 rdev->pm.power_state[state_index].type =
2083 POWER_STATE_TYPE_DEFAULT;
2084 rdev->pm.default_power_state_index = state_index;
2085 rdev->pm.power_state[state_index].default_clock_mode =
2086 &rdev->pm.power_state[state_index].clock_info[0];
2087 } else if (state_index == 0) {
2088 rdev->pm.power_state[state_index].clock_info[0].flags |=
2089 RADEON_PM_MODE_NO_DISPLAY;
2090 }
2091}
2092
2093static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2094{
2095 struct radeon_mode_info *mode_info = &rdev->mode_info;
2096 u32 misc, misc2 = 0;
2097 int num_modes = 0, i;
2098 int state_index = 0;
2099 struct radeon_i2c_bus_rec i2c_bus;
2100 union power_info *power_info;
2101 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2102 u16 data_offset;
2103 u8 frev, crev;
2104
2105 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2106 &frev, &crev, &data_offset))
2107 return state_index;
2108 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2109
2110
2111 if ((power_info->info.ucOverdriveThermalController > 0) &&
2112 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2113 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2114 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2115 power_info->info.ucOverdriveControllerAddress >> 1);
2116 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2117 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2118 if (rdev->pm.i2c_bus) {
2119 struct i2c_board_info info = { };
2120 const char *name = thermal_controller_names[power_info->info.
2121 ucOverdriveThermalController];
2122 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2123 strlcpy(info.type, name, sizeof(info.type));
2124 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2125 }
2126 }
2127 num_modes = power_info->info.ucNumOfPowerModeEntries;
2128 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2129 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2130 if (num_modes == 0)
2131 return state_index;
2132 rdev->pm.power_state = kcalloc(num_modes,
2133 sizeof(struct radeon_power_state),
2134 GFP_KERNEL);
2135 if (!rdev->pm.power_state)
2136 return state_index;
2137
2138 for (i = 0; i < num_modes; i++) {
2139 rdev->pm.power_state[state_index].clock_info =
2140 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2141 GFP_KERNEL);
2142 if (!rdev->pm.power_state[state_index].clock_info)
2143 return state_index;
2144 rdev->pm.power_state[state_index].num_clock_modes = 1;
2145 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2146 switch (frev) {
2147 case 1:
2148 rdev->pm.power_state[state_index].clock_info[0].mclk =
2149 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2150 rdev->pm.power_state[state_index].clock_info[0].sclk =
2151 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2152
2153 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2154 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2155 continue;
2156 rdev->pm.power_state[state_index].pcie_lanes =
2157 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2158 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2159 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2160 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2162 VOLTAGE_GPIO;
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2164 radeon_atombios_lookup_gpio(rdev,
2165 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2166 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2168 true;
2169 else
2170 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2171 false;
2172 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2173 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2174 VOLTAGE_VDDC;
2175 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2176 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2177 }
2178 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2179 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2180 state_index++;
2181 break;
2182 case 2:
2183 rdev->pm.power_state[state_index].clock_info[0].mclk =
2184 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2185 rdev->pm.power_state[state_index].clock_info[0].sclk =
2186 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2187
2188 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2189 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2190 continue;
2191 rdev->pm.power_state[state_index].pcie_lanes =
2192 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2193 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2194 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2195 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2196 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2198 VOLTAGE_GPIO;
2199 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2200 radeon_atombios_lookup_gpio(rdev,
2201 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2202 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2203 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2204 true;
2205 else
2206 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2207 false;
2208 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2209 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2210 VOLTAGE_VDDC;
2211 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2212 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2213 }
2214 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2215 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2216 state_index++;
2217 break;
2218 case 3:
2219 rdev->pm.power_state[state_index].clock_info[0].mclk =
2220 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2221 rdev->pm.power_state[state_index].clock_info[0].sclk =
2222 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2223
2224 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2225 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2226 continue;
2227 rdev->pm.power_state[state_index].pcie_lanes =
2228 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2229 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2230 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2231 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2232 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2234 VOLTAGE_GPIO;
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2236 radeon_atombios_lookup_gpio(rdev,
2237 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2238 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2239 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2240 true;
2241 else
2242 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2243 false;
2244 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2245 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2246 VOLTAGE_VDDC;
2247 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2248 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2249 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2250 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2251 true;
2252 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2253 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2254 }
2255 }
2256 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2257 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2258 state_index++;
2259 break;
2260 }
2261 }
2262
2263 if (rdev->pm.default_power_state_index == -1) {
2264 rdev->pm.power_state[state_index - 1].type =
2265 POWER_STATE_TYPE_DEFAULT;
2266 rdev->pm.default_power_state_index = state_index - 1;
2267 rdev->pm.power_state[state_index - 1].default_clock_mode =
2268 &rdev->pm.power_state[state_index - 1].clock_info[0];
2269 rdev->pm.power_state[state_index].flags &=
2270 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2271 rdev->pm.power_state[state_index].misc = 0;
2272 rdev->pm.power_state[state_index].misc2 = 0;
2273 }
2274 return state_index;
2275}
2276
2277static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2278 ATOM_PPLIB_THERMALCONTROLLER *controller)
2279{
2280 struct radeon_i2c_bus_rec i2c_bus;
2281
2282
2283 if (controller->ucType > 0) {
2284 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2285 rdev->pm.no_fan = true;
2286 rdev->pm.fan_pulses_per_revolution =
2287 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2288 if (rdev->pm.fan_pulses_per_revolution) {
2289 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2290 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2291 }
2292 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2293 DRM_INFO("Internal thermal controller %s fan control\n",
2294 (controller->ucFanParameters &
2295 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2297 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2298 DRM_INFO("Internal thermal controller %s fan control\n",
2299 (controller->ucFanParameters &
2300 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2301 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2302 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2303 DRM_INFO("Internal thermal controller %s fan control\n",
2304 (controller->ucFanParameters &
2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2306 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2307 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2308 DRM_INFO("Internal thermal controller %s fan control\n",
2309 (controller->ucFanParameters &
2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2311 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2312 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2313 DRM_INFO("Internal thermal controller %s fan control\n",
2314 (controller->ucFanParameters &
2315 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2316 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2317 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2318 DRM_INFO("Internal thermal controller %s fan control\n",
2319 (controller->ucFanParameters &
2320 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2321 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2322 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2323 DRM_INFO("Internal thermal controller %s fan control\n",
2324 (controller->ucFanParameters &
2325 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2326 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2327 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2328 DRM_INFO("Internal thermal controller %s fan control\n",
2329 (controller->ucFanParameters &
2330 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2331 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2332 } else if (controller->ucType ==
2333 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2334 DRM_INFO("External GPIO thermal controller %s fan control\n",
2335 (controller->ucFanParameters &
2336 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2337 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2338 } else if (controller->ucType ==
2339 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2340 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2341 (controller->ucFanParameters &
2342 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2343 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2344 } else if (controller->ucType ==
2345 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2346 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2347 (controller->ucFanParameters &
2348 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2349 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2350 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2351 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2352 pp_lib_thermal_controller_names[controller->ucType],
2353 controller->ucI2cAddress >> 1,
2354 (controller->ucFanParameters &
2355 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2356 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2357 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2358 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2359 if (rdev->pm.i2c_bus) {
2360 struct i2c_board_info info = { };
2361 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2362 info.addr = controller->ucI2cAddress >> 1;
2363 strlcpy(info.type, name, sizeof(info.type));
2364 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2365 }
2366 } else {
2367 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2368 controller->ucType,
2369 controller->ucI2cAddress >> 1,
2370 (controller->ucFanParameters &
2371 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2372 }
2373 }
2374}
2375
2376void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2377 u16 *vddc, u16 *vddci, u16 *mvdd)
2378{
2379 struct radeon_mode_info *mode_info = &rdev->mode_info;
2380 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2381 u8 frev, crev;
2382 u16 data_offset;
2383 union firmware_info *firmware_info;
2384
2385 *vddc = 0;
2386 *vddci = 0;
2387 *mvdd = 0;
2388
2389 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2390 &frev, &crev, &data_offset)) {
2391 firmware_info =
2392 (union firmware_info *)(mode_info->atom_context->bios +
2393 data_offset);
2394 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2395 if ((frev == 2) && (crev >= 2)) {
2396 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2397 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2398 }
2399 }
2400}
2401
2402static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2403 int state_index, int mode_index,
2404 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2405{
2406 int j;
2407 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2408 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2409 u16 vddc, vddci, mvdd;
2410
2411 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2412
2413 rdev->pm.power_state[state_index].misc = misc;
2414 rdev->pm.power_state[state_index].misc2 = misc2;
2415 rdev->pm.power_state[state_index].pcie_lanes =
2416 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2417 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2418 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2419 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2420 rdev->pm.power_state[state_index].type =
2421 POWER_STATE_TYPE_BATTERY;
2422 break;
2423 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2424 rdev->pm.power_state[state_index].type =
2425 POWER_STATE_TYPE_BALANCED;
2426 break;
2427 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2428 rdev->pm.power_state[state_index].type =
2429 POWER_STATE_TYPE_PERFORMANCE;
2430 break;
2431 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2432 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2433 rdev->pm.power_state[state_index].type =
2434 POWER_STATE_TYPE_PERFORMANCE;
2435 break;
2436 }
2437 rdev->pm.power_state[state_index].flags = 0;
2438 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2439 rdev->pm.power_state[state_index].flags |=
2440 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2441 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2442 rdev->pm.power_state[state_index].type =
2443 POWER_STATE_TYPE_DEFAULT;
2444 rdev->pm.default_power_state_index = state_index;
2445 rdev->pm.power_state[state_index].default_clock_mode =
2446 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2447 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2448
2449 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2450 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2451 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2452 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2453 } else {
2454 u16 max_vddci = 0;
2455
2456 if (ASIC_IS_DCE4(rdev))
2457 radeon_atom_get_max_voltage(rdev,
2458 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2459 &max_vddci);
2460
2461 for (j = 0; j < mode_index; j++) {
2462 rdev->pm.power_state[state_index].clock_info[j].mclk =
2463 rdev->clock.default_mclk;
2464 rdev->pm.power_state[state_index].clock_info[j].sclk =
2465 rdev->clock.default_sclk;
2466 if (vddc)
2467 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2468 vddc;
2469 if (max_vddci)
2470 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2471 max_vddci;
2472 }
2473 }
2474 }
2475}
2476
2477static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2478 int state_index, int mode_index,
2479 union pplib_clock_info *clock_info)
2480{
2481 u32 sclk, mclk;
2482 u16 vddc;
2483
2484 if (rdev->flags & RADEON_IS_IGP) {
2485 if (rdev->family >= CHIP_PALM) {
2486 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2487 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2488 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2489 } else {
2490 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2491 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2492 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2493 }
2494 } else if (rdev->family >= CHIP_BONAIRE) {
2495 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2496 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2497 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2498 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2499 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2500 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2501 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2502 VOLTAGE_NONE;
2503 } else if (rdev->family >= CHIP_TAHITI) {
2504 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2505 sclk |= clock_info->si.ucEngineClockHigh << 16;
2506 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2507 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2508 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2509 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2511 VOLTAGE_SW;
2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2513 le16_to_cpu(clock_info->si.usVDDC);
2514 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2515 le16_to_cpu(clock_info->si.usVDDCI);
2516 } else if (rdev->family >= CHIP_CEDAR) {
2517 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2518 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2519 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2520 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2521 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2522 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2524 VOLTAGE_SW;
2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2526 le16_to_cpu(clock_info->evergreen.usVDDC);
2527 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2528 le16_to_cpu(clock_info->evergreen.usVDDCI);
2529 } else {
2530 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2531 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2532 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2533 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2534 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2535 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2537 VOLTAGE_SW;
2538 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2539 le16_to_cpu(clock_info->r600.usVDDC);
2540 }
2541
2542
2543 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2544 case ATOM_VIRTUAL_VOLTAGE_ID0:
2545 case ATOM_VIRTUAL_VOLTAGE_ID1:
2546 case ATOM_VIRTUAL_VOLTAGE_ID2:
2547 case ATOM_VIRTUAL_VOLTAGE_ID3:
2548 case ATOM_VIRTUAL_VOLTAGE_ID4:
2549 case ATOM_VIRTUAL_VOLTAGE_ID5:
2550 case ATOM_VIRTUAL_VOLTAGE_ID6:
2551 case ATOM_VIRTUAL_VOLTAGE_ID7:
2552 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2553 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2554 &vddc) == 0)
2555 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2556 break;
2557 default:
2558 break;
2559 }
2560
2561 if (rdev->flags & RADEON_IS_IGP) {
2562
2563 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2564 return false;
2565 } else {
2566
2567 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2568 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2569 return false;
2570 }
2571 return true;
2572}
2573
2574static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2575{
2576 struct radeon_mode_info *mode_info = &rdev->mode_info;
2577 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2578 union pplib_power_state *power_state;
2579 int i, j;
2580 int state_index = 0, mode_index = 0;
2581 union pplib_clock_info *clock_info;
2582 bool valid;
2583 union power_info *power_info;
2584 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2585 u16 data_offset;
2586 u8 frev, crev;
2587
2588 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2589 &frev, &crev, &data_offset))
2590 return state_index;
2591 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2592
2593 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2594 if (power_info->pplib.ucNumStates == 0)
2595 return state_index;
2596 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2597 sizeof(struct radeon_power_state),
2598 GFP_KERNEL);
2599 if (!rdev->pm.power_state)
2600 return state_index;
2601
2602 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2603 mode_index = 0;
2604 power_state = (union pplib_power_state *)
2605 (mode_info->atom_context->bios + data_offset +
2606 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2607 i * power_info->pplib.ucStateEntrySize);
2608 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2609 (mode_info->atom_context->bios + data_offset +
2610 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2611 (power_state->v1.ucNonClockStateIndex *
2612 power_info->pplib.ucNonClockSize));
2613 rdev->pm.power_state[i].clock_info =
2614 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2615 (power_info->pplib.ucStateEntrySize - 1) : 1,
2616 sizeof(struct radeon_pm_clock_info),
2617 GFP_KERNEL);
2618 if (!rdev->pm.power_state[i].clock_info)
2619 return state_index;
2620 if (power_info->pplib.ucStateEntrySize - 1) {
2621 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2622 clock_info = (union pplib_clock_info *)
2623 (mode_info->atom_context->bios + data_offset +
2624 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2625 (power_state->v1.ucClockStateIndices[j] *
2626 power_info->pplib.ucClockInfoSize));
2627 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2628 state_index, mode_index,
2629 clock_info);
2630 if (valid)
2631 mode_index++;
2632 }
2633 } else {
2634 rdev->pm.power_state[state_index].clock_info[0].mclk =
2635 rdev->clock.default_mclk;
2636 rdev->pm.power_state[state_index].clock_info[0].sclk =
2637 rdev->clock.default_sclk;
2638 mode_index++;
2639 }
2640 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2641 if (mode_index) {
2642 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2643 non_clock_info);
2644 state_index++;
2645 }
2646 }
2647
2648 for (i = 0; i < state_index; i++) {
2649 if (rdev->pm.power_state[i].num_clock_modes > 1)
2650 rdev->pm.power_state[i].clock_info[0].flags |=
2651 RADEON_PM_MODE_NO_DISPLAY;
2652 }
2653
2654 if (rdev->pm.default_power_state_index == -1) {
2655 rdev->pm.power_state[0].type =
2656 POWER_STATE_TYPE_DEFAULT;
2657 rdev->pm.default_power_state_index = 0;
2658 rdev->pm.power_state[0].default_clock_mode =
2659 &rdev->pm.power_state[0].clock_info[0];
2660 }
2661 return state_index;
2662}
2663
2664static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2665{
2666 struct radeon_mode_info *mode_info = &rdev->mode_info;
2667 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2668 union pplib_power_state *power_state;
2669 int i, j, non_clock_array_index, clock_array_index;
2670 int state_index = 0, mode_index = 0;
2671 union pplib_clock_info *clock_info;
2672 struct _StateArray *state_array;
2673 struct _ClockInfoArray *clock_info_array;
2674 struct _NonClockInfoArray *non_clock_info_array;
2675 bool valid;
2676 union power_info *power_info;
2677 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2678 u16 data_offset;
2679 u8 frev, crev;
2680 u8 *power_state_offset;
2681
2682 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2683 &frev, &crev, &data_offset))
2684 return state_index;
2685 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2686
2687 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2688 state_array = (struct _StateArray *)
2689 (mode_info->atom_context->bios + data_offset +
2690 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2691 clock_info_array = (struct _ClockInfoArray *)
2692 (mode_info->atom_context->bios + data_offset +
2693 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2694 non_clock_info_array = (struct _NonClockInfoArray *)
2695 (mode_info->atom_context->bios + data_offset +
2696 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2697 if (state_array->ucNumEntries == 0)
2698 return state_index;
2699 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2700 sizeof(struct radeon_power_state),
2701 GFP_KERNEL);
2702 if (!rdev->pm.power_state)
2703 return state_index;
2704 power_state_offset = (u8 *)state_array->states;
2705 for (i = 0; i < state_array->ucNumEntries; i++) {
2706 mode_index = 0;
2707 power_state = (union pplib_power_state *)power_state_offset;
2708 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2709 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2710 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2711 rdev->pm.power_state[i].clock_info =
2712 kcalloc(power_state->v2.ucNumDPMLevels ?
2713 power_state->v2.ucNumDPMLevels : 1,
2714 sizeof(struct radeon_pm_clock_info),
2715 GFP_KERNEL);
2716 if (!rdev->pm.power_state[i].clock_info)
2717 return state_index;
2718 if (power_state->v2.ucNumDPMLevels) {
2719 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2720 clock_array_index = power_state->v2.clockInfoIndex[j];
2721 clock_info = (union pplib_clock_info *)
2722 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2723 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2724 state_index, mode_index,
2725 clock_info);
2726 if (valid)
2727 mode_index++;
2728 }
2729 } else {
2730 rdev->pm.power_state[state_index].clock_info[0].mclk =
2731 rdev->clock.default_mclk;
2732 rdev->pm.power_state[state_index].clock_info[0].sclk =
2733 rdev->clock.default_sclk;
2734 mode_index++;
2735 }
2736 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2737 if (mode_index) {
2738 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2739 non_clock_info);
2740 state_index++;
2741 }
2742 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2743 }
2744
2745 for (i = 0; i < state_index; i++) {
2746 if (rdev->pm.power_state[i].num_clock_modes > 1)
2747 rdev->pm.power_state[i].clock_info[0].flags |=
2748 RADEON_PM_MODE_NO_DISPLAY;
2749 }
2750
2751 if (rdev->pm.default_power_state_index == -1) {
2752 rdev->pm.power_state[0].type =
2753 POWER_STATE_TYPE_DEFAULT;
2754 rdev->pm.default_power_state_index = 0;
2755 rdev->pm.power_state[0].default_clock_mode =
2756 &rdev->pm.power_state[0].clock_info[0];
2757 }
2758 return state_index;
2759}
2760
2761void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2762{
2763 struct radeon_mode_info *mode_info = &rdev->mode_info;
2764 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2765 u16 data_offset;
2766 u8 frev, crev;
2767 int state_index = 0;
2768
2769 rdev->pm.default_power_state_index = -1;
2770
2771 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2772 &frev, &crev, &data_offset)) {
2773 switch (frev) {
2774 case 1:
2775 case 2:
2776 case 3:
2777 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2778 break;
2779 case 4:
2780 case 5:
2781 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2782 break;
2783 case 6:
2784 state_index = radeon_atombios_parse_power_table_6(rdev);
2785 break;
2786 default:
2787 break;
2788 }
2789 }
2790
2791 if (state_index == 0) {
2792 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2793 if (rdev->pm.power_state) {
2794 rdev->pm.power_state[0].clock_info =
2795 kcalloc(1,
2796 sizeof(struct radeon_pm_clock_info),
2797 GFP_KERNEL);
2798 if (rdev->pm.power_state[0].clock_info) {
2799
2800 rdev->pm.power_state[state_index].type =
2801 POWER_STATE_TYPE_DEFAULT;
2802 rdev->pm.power_state[state_index].num_clock_modes = 1;
2803 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2804 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2805 rdev->pm.power_state[state_index].default_clock_mode =
2806 &rdev->pm.power_state[state_index].clock_info[0];
2807 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2808 rdev->pm.power_state[state_index].pcie_lanes = 16;
2809 rdev->pm.default_power_state_index = state_index;
2810 rdev->pm.power_state[state_index].flags = 0;
2811 state_index++;
2812 }
2813 }
2814 }
2815
2816 rdev->pm.num_power_states = state_index;
2817
2818 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2819 rdev->pm.current_clock_mode_index = 0;
2820 if (rdev->pm.default_power_state_index >= 0)
2821 rdev->pm.current_vddc =
2822 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2823 else
2824 rdev->pm.current_vddc = 0;
2825}
2826
2827union get_clock_dividers {
2828 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2829 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2830 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2831 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2832 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2833 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2834 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2835};
2836
2837int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2838 u8 clock_type,
2839 u32 clock,
2840 bool strobe_mode,
2841 struct atom_clock_dividers *dividers)
2842{
2843 union get_clock_dividers args;
2844 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2845 u8 frev, crev;
2846
2847 memset(&args, 0, sizeof(args));
2848 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2849
2850 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2851 return -EINVAL;
2852
2853 switch (crev) {
2854 case 1:
2855
2856 args.v1.ucAction = clock_type;
2857 args.v1.ulClock = cpu_to_le32(clock);
2858
2859 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2860
2861 dividers->post_div = args.v1.ucPostDiv;
2862 dividers->fb_div = args.v1.ucFbDiv;
2863 dividers->enable_post_div = true;
2864 break;
2865 case 2:
2866 case 3:
2867 case 5:
2868
2869 if (rdev->family <= CHIP_RV770) {
2870 args.v2.ucAction = clock_type;
2871 args.v2.ulClock = cpu_to_le32(clock);
2872
2873 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2874
2875 dividers->post_div = args.v2.ucPostDiv;
2876 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2877 dividers->ref_div = args.v2.ucAction;
2878 if (rdev->family == CHIP_RV770) {
2879 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2880 true : false;
2881 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2882 } else
2883 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2884 } else {
2885 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2886 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2887
2888 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2889
2890 dividers->post_div = args.v3.ucPostDiv;
2891 dividers->enable_post_div = (args.v3.ucCntlFlag &
2892 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2893 dividers->enable_dithen = (args.v3.ucCntlFlag &
2894 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2895 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2896 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2897 dividers->ref_div = args.v3.ucRefDiv;
2898 dividers->vco_mode = (args.v3.ucCntlFlag &
2899 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2900 } else {
2901
2902 if (rdev->family >= CHIP_TAHITI)
2903 return -EINVAL;
2904 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2905 if (strobe_mode)
2906 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2907
2908 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2909
2910 dividers->post_div = args.v5.ucPostDiv;
2911 dividers->enable_post_div = (args.v5.ucCntlFlag &
2912 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2913 dividers->enable_dithen = (args.v5.ucCntlFlag &
2914 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2915 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2916 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2917 dividers->ref_div = args.v5.ucRefDiv;
2918 dividers->vco_mode = (args.v5.ucCntlFlag &
2919 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2920 }
2921 }
2922 break;
2923 case 4:
2924
2925 args.v4.ulClock = cpu_to_le32(clock);
2926
2927 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2928
2929 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2930 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2931 break;
2932 case 6:
2933
2934
2935 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2936 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);
2937
2938 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2939
2940 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2941 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2942 dividers->ref_div = args.v6_out.ucPllRefDiv;
2943 dividers->post_div = args.v6_out.ucPllPostDiv;
2944 dividers->flags = args.v6_out.ucPllCntlFlag;
2945 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2946 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2947 break;
2948 default:
2949 return -EINVAL;
2950 }
2951 return 0;
2952}
2953
2954int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2955 u32 clock,
2956 bool strobe_mode,
2957 struct atom_mpll_param *mpll_param)
2958{
2959 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2960 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2961 u8 frev, crev;
2962
2963 memset(&args, 0, sizeof(args));
2964 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2965
2966 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2967 return -EINVAL;
2968
2969 switch (frev) {
2970 case 2:
2971 switch (crev) {
2972 case 1:
2973
2974 args.ulClock = cpu_to_le32(clock);
2975 args.ucInputFlag = 0;
2976 if (strobe_mode)
2977 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2978
2979 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2980
2981 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2982 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2983 mpll_param->post_div = args.ucPostDiv;
2984 mpll_param->dll_speed = args.ucDllSpeed;
2985 mpll_param->bwcntl = args.ucBWCntl;
2986 mpll_param->vco_mode =
2987 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2988 mpll_param->yclk_sel =
2989 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2990 mpll_param->qdr =
2991 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2992 mpll_param->half_rate =
2993 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2994 break;
2995 default:
2996 return -EINVAL;
2997 }
2998 break;
2999 default:
3000 return -EINVAL;
3001 }
3002 return 0;
3003}
3004
3005void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3006{
3007 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3008 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3009
3010 args.ucEnable = enable;
3011
3012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3013}
3014
3015uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3016{
3017 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3018 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3019
3020 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3021 return le32_to_cpu(args.ulReturnEngineClock);
3022}
3023
3024uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3025{
3026 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3027 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3028
3029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3030 return le32_to_cpu(args.ulReturnMemoryClock);
3031}
3032
3033void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3034 uint32_t eng_clock)
3035{
3036 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3037 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3038
3039 args.ulTargetEngineClock = cpu_to_le32(eng_clock);
3040
3041 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3042}
3043
3044void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3045 uint32_t mem_clock)
3046{
3047 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3048 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3049
3050 if (rdev->flags & RADEON_IS_IGP)
3051 return;
3052
3053 args.ulTargetMemoryClock = cpu_to_le32(mem_clock);
3054
3055 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3056}
3057
3058void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3059 u32 eng_clock, u32 mem_clock)
3060{
3061 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3062 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3063 u32 tmp;
3064
3065 memset(&args, 0, sizeof(args));
3066
3067 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3068 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3069
3070 args.ulTargetEngineClock = cpu_to_le32(tmp);
3071 if (mem_clock)
3072 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3073
3074 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3075}
3076
3077void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3078 u32 mem_clock)
3079{
3080 u32 args;
3081 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3082
3083 args = cpu_to_le32(mem_clock);
3084
3085 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3086}
3087
3088void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3089 u32 mem_clock)
3090{
3091 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3092 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3093 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3094
3095 args.ulTargetMemoryClock = cpu_to_le32(tmp);
3096
3097 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3098}
3099
3100union set_voltage {
3101 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3102 struct _SET_VOLTAGE_PARAMETERS v1;
3103 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3104 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3105};
3106
3107void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3108{
3109 union set_voltage args;
3110 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3111 u8 frev, crev, volt_index = voltage_level;
3112
3113 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3114 return;
3115
3116
3117 if (voltage_level == 0xff01)
3118 return;
3119
3120 switch (crev) {
3121 case 1:
3122 args.v1.ucVoltageType = voltage_type;
3123 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3124 args.v1.ucVoltageIndex = volt_index;
3125 break;
3126 case 2:
3127 args.v2.ucVoltageType = voltage_type;
3128 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3129 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3130 break;
3131 case 3:
3132 args.v3.ucVoltageType = voltage_type;
3133 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3134 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3135 break;
3136 default:
3137 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3138 return;
3139 }
3140
3141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3142}
3143
3144int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3145 u16 voltage_id, u16 *voltage)
3146{
3147 union set_voltage args;
3148 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3149 u8 frev, crev;
3150
3151 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3152 return -EINVAL;
3153
3154 switch (crev) {
3155 case 1:
3156 return -EINVAL;
3157 case 2:
3158 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3159 args.v2.ucVoltageMode = 0;
3160 args.v2.usVoltageLevel = 0;
3161
3162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3163
3164 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3165 break;
3166 case 3:
3167 args.v3.ucVoltageType = voltage_type;
3168 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3169 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3170
3171 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3172
3173 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3174 break;
3175 default:
3176 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3177 return -EINVAL;
3178 }
3179
3180 return 0;
3181}
3182
3183int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3184 u16 *voltage,
3185 u16 leakage_idx)
3186{
3187 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3188}
3189
3190int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3191 u16 *leakage_id)
3192{
3193 union set_voltage args;
3194 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3195 u8 frev, crev;
3196
3197 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3198 return -EINVAL;
3199
3200 switch (crev) {
3201 case 3:
3202 case 4:
3203 args.v3.ucVoltageType = 0;
3204 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3205 args.v3.usVoltageLevel = 0;
3206
3207 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3208
3209 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3210 break;
3211 default:
3212 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3213 return -EINVAL;
3214 }
3215
3216 return 0;
3217}
3218
3219int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3220 u16 *vddc, u16 *vddci,
3221 u16 virtual_voltage_id,
3222 u16 vbios_voltage_id)
3223{
3224 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3225 u8 frev, crev;
3226 u16 data_offset, size;
3227 int i, j;
3228 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3229 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3230
3231 *vddc = 0;
3232 *vddci = 0;
3233
3234 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3235 &frev, &crev, &data_offset))
3236 return -EINVAL;
3237
3238 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3239 (rdev->mode_info.atom_context->bios + data_offset);
3240
3241 switch (frev) {
3242 case 1:
3243 return -EINVAL;
3244 case 2:
3245 switch (crev) {
3246 case 1:
3247 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3248 return -EINVAL;
3249 leakage_bin = (u16 *)
3250 (rdev->mode_info.atom_context->bios + data_offset +
3251 le16_to_cpu(profile->usLeakageBinArrayOffset));
3252 vddc_id_buf = (u16 *)
3253 (rdev->mode_info.atom_context->bios + data_offset +
3254 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3255 vddc_buf = (u16 *)
3256 (rdev->mode_info.atom_context->bios + data_offset +
3257 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3258 vddci_id_buf = (u16 *)
3259 (rdev->mode_info.atom_context->bios + data_offset +
3260 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3261 vddci_buf = (u16 *)
3262 (rdev->mode_info.atom_context->bios + data_offset +
3263 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3264
3265 if (profile->ucElbVDDC_Num > 0) {
3266 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3267 if (vddc_id_buf[i] == virtual_voltage_id) {
3268 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3269 if (vbios_voltage_id <= leakage_bin[j]) {
3270 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3271 break;
3272 }
3273 }
3274 break;
3275 }
3276 }
3277 }
3278 if (profile->ucElbVDDCI_Num > 0) {
3279 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3280 if (vddci_id_buf[i] == virtual_voltage_id) {
3281 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3282 if (vbios_voltage_id <= leakage_bin[j]) {
3283 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3284 break;
3285 }
3286 }
3287 break;
3288 }
3289 }
3290 }
3291 break;
3292 default:
3293 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3294 return -EINVAL;
3295 }
3296 break;
3297 default:
3298 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3299 return -EINVAL;
3300 }
3301
3302 return 0;
3303}
3304
3305union get_voltage_info {
3306 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3307 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3308};
3309
3310int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3311 u16 virtual_voltage_id,
3312 u16 *voltage)
3313{
3314 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3315 u32 entry_id;
3316 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3317 union get_voltage_info args;
3318
3319 for (entry_id = 0; entry_id < count; entry_id++) {
3320 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3321 virtual_voltage_id)
3322 break;
3323 }
3324
3325 if (entry_id >= count)
3326 return -EINVAL;
3327
3328 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3329 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3330 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3331 args.in.ulSCLKFreq =
3332 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3333
3334 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3335
3336 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3337
3338 return 0;
3339}
3340
3341int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3342 u16 voltage_level, u8 voltage_type,
3343 u32 *gpio_value, u32 *gpio_mask)
3344{
3345 union set_voltage args;
3346 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3347 u8 frev, crev;
3348
3349 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3350 return -EINVAL;
3351
3352 switch (crev) {
3353 case 1:
3354 return -EINVAL;
3355 case 2:
3356 args.v2.ucVoltageType = voltage_type;
3357 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3358 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3359
3360 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3361
3362 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3363
3364 args.v2.ucVoltageType = voltage_type;
3365 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3366 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3367
3368 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3369
3370 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3371 break;
3372 default:
3373 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3374 return -EINVAL;
3375 }
3376
3377 return 0;
3378}
3379
3380union voltage_object_info {
3381 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3382 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3383 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3384};
3385
3386union voltage_object {
3387 struct _ATOM_VOLTAGE_OBJECT v1;
3388 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3389 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3390};
3391
3392static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3393 u8 voltage_type)
3394{
3395 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3396 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3397 u8 *start = (u8 *)v1;
3398
3399 while (offset < size) {
3400 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3401 if (vo->ucVoltageType == voltage_type)
3402 return vo;
3403 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3404 vo->asFormula.ucNumOfVoltageEntries;
3405 }
3406 return NULL;
3407}
3408
3409static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3410 u8 voltage_type)
3411{
3412 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3413 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3414 u8 *start = (u8*)v2;
3415
3416 while (offset < size) {
3417 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3418 if (vo->ucVoltageType == voltage_type)
3419 return vo;
3420 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3421 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3422 }
3423 return NULL;
3424}
3425
3426static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3427 u8 voltage_type, u8 voltage_mode)
3428{
3429 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3430 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3431 u8 *start = (u8*)v3;
3432
3433 while (offset < size) {
3434 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3435 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3436 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3437 return vo;
3438 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3439 }
3440 return NULL;
3441}
3442
3443bool
3444radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3445 u8 voltage_type, u8 voltage_mode)
3446{
3447 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3448 u8 frev, crev;
3449 u16 data_offset, size;
3450 union voltage_object_info *voltage_info;
3451 union voltage_object *voltage_object = NULL;
3452
3453 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3454 &frev, &crev, &data_offset)) {
3455 voltage_info = (union voltage_object_info *)
3456 (rdev->mode_info.atom_context->bios + data_offset);
3457
3458 switch (frev) {
3459 case 1:
3460 case 2:
3461 switch (crev) {
3462 case 1:
3463 voltage_object = (union voltage_object *)
3464 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3465 if (voltage_object &&
3466 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3467 return true;
3468 break;
3469 case 2:
3470 voltage_object = (union voltage_object *)
3471 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3472 if (voltage_object &&
3473 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3474 return true;
3475 break;
3476 default:
3477 DRM_ERROR("unknown voltage object table\n");
3478 return false;
3479 }
3480 break;
3481 case 3:
3482 switch (crev) {
3483 case 1:
3484 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3485 voltage_type, voltage_mode))
3486 return true;
3487 break;
3488 default:
3489 DRM_ERROR("unknown voltage object table\n");
3490 return false;
3491 }
3492 break;
3493 default:
3494 DRM_ERROR("unknown voltage object table\n");
3495 return false;
3496 }
3497
3498 }
3499 return false;
3500}
3501
3502int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3503 u8 voltage_type,
3504 u8 *svd_gpio_id, u8 *svc_gpio_id)
3505{
3506 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3507 u8 frev, crev;
3508 u16 data_offset, size;
3509 union voltage_object_info *voltage_info;
3510 union voltage_object *voltage_object = NULL;
3511
3512 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3513 &frev, &crev, &data_offset)) {
3514 voltage_info = (union voltage_object_info *)
3515 (rdev->mode_info.atom_context->bios + data_offset);
3516
3517 switch (frev) {
3518 case 3:
3519 switch (crev) {
3520 case 1:
3521 voltage_object = (union voltage_object *)
3522 atom_lookup_voltage_object_v3(&voltage_info->v3,
3523 voltage_type,
3524 VOLTAGE_OBJ_SVID2);
3525 if (voltage_object) {
3526 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3527 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3528 } else {
3529 return -EINVAL;
3530 }
3531 break;
3532 default:
3533 DRM_ERROR("unknown voltage object table\n");
3534 return -EINVAL;
3535 }
3536 break;
3537 default:
3538 DRM_ERROR("unknown voltage object table\n");
3539 return -EINVAL;
3540 }
3541
3542 }
3543 return 0;
3544}
3545
3546int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3547 u8 voltage_type, u16 *max_voltage)
3548{
3549 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3550 u8 frev, crev;
3551 u16 data_offset, size;
3552 union voltage_object_info *voltage_info;
3553 union voltage_object *voltage_object = NULL;
3554
3555 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3556 &frev, &crev, &data_offset)) {
3557 voltage_info = (union voltage_object_info *)
3558 (rdev->mode_info.atom_context->bios + data_offset);
3559
3560 switch (crev) {
3561 case 1:
3562 voltage_object = (union voltage_object *)
3563 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3564 if (voltage_object) {
3565 ATOM_VOLTAGE_FORMULA *formula =
3566 &voltage_object->v1.asFormula;
3567 if (formula->ucFlag & 1)
3568 *max_voltage =
3569 le16_to_cpu(formula->usVoltageBaseLevel) +
3570 formula->ucNumOfVoltageEntries / 2 *
3571 le16_to_cpu(formula->usVoltageStep);
3572 else
3573 *max_voltage =
3574 le16_to_cpu(formula->usVoltageBaseLevel) +
3575 (formula->ucNumOfVoltageEntries - 1) *
3576 le16_to_cpu(formula->usVoltageStep);
3577 return 0;
3578 }
3579 break;
3580 case 2:
3581 voltage_object = (union voltage_object *)
3582 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3583 if (voltage_object) {
3584 ATOM_VOLTAGE_FORMULA_V2 *formula =
3585 &voltage_object->v2.asFormula;
3586 if (formula->ucNumOfVoltageEntries) {
3587 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3588 ((u8 *)&formula->asVIDAdjustEntries[0] +
3589 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3590 *max_voltage =
3591 le16_to_cpu(lut->usVoltageValue);
3592 return 0;
3593 }
3594 }
3595 break;
3596 default:
3597 DRM_ERROR("unknown voltage object table\n");
3598 return -EINVAL;
3599 }
3600
3601 }
3602 return -EINVAL;
3603}
3604
3605int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3606 u8 voltage_type, u16 *min_voltage)
3607{
3608 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3609 u8 frev, crev;
3610 u16 data_offset, size;
3611 union voltage_object_info *voltage_info;
3612 union voltage_object *voltage_object = NULL;
3613
3614 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3615 &frev, &crev, &data_offset)) {
3616 voltage_info = (union voltage_object_info *)
3617 (rdev->mode_info.atom_context->bios + data_offset);
3618
3619 switch (crev) {
3620 case 1:
3621 voltage_object = (union voltage_object *)
3622 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3623 if (voltage_object) {
3624 ATOM_VOLTAGE_FORMULA *formula =
3625 &voltage_object->v1.asFormula;
3626 *min_voltage =
3627 le16_to_cpu(formula->usVoltageBaseLevel);
3628 return 0;
3629 }
3630 break;
3631 case 2:
3632 voltage_object = (union voltage_object *)
3633 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3634 if (voltage_object) {
3635 ATOM_VOLTAGE_FORMULA_V2 *formula =
3636 &voltage_object->v2.asFormula;
3637 if (formula->ucNumOfVoltageEntries) {
3638 *min_voltage =
3639 le16_to_cpu(formula->asVIDAdjustEntries[
3640 0
3641 ].usVoltageValue);
3642 return 0;
3643 }
3644 }
3645 break;
3646 default:
3647 DRM_ERROR("unknown voltage object table\n");
3648 return -EINVAL;
3649 }
3650
3651 }
3652 return -EINVAL;
3653}
3654
3655int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3656 u8 voltage_type, u16 *voltage_step)
3657{
3658 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3659 u8 frev, crev;
3660 u16 data_offset, size;
3661 union voltage_object_info *voltage_info;
3662 union voltage_object *voltage_object = NULL;
3663
3664 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3665 &frev, &crev, &data_offset)) {
3666 voltage_info = (union voltage_object_info *)
3667 (rdev->mode_info.atom_context->bios + data_offset);
3668
3669 switch (crev) {
3670 case 1:
3671 voltage_object = (union voltage_object *)
3672 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3673 if (voltage_object) {
3674 ATOM_VOLTAGE_FORMULA *formula =
3675 &voltage_object->v1.asFormula;
3676 if (formula->ucFlag & 1)
3677 *voltage_step =
3678 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3679 else
3680 *voltage_step =
3681 le16_to_cpu(formula->usVoltageStep);
3682 return 0;
3683 }
3684 break;
3685 case 2:
3686 return -EINVAL;
3687 default:
3688 DRM_ERROR("unknown voltage object table\n");
3689 return -EINVAL;
3690 }
3691
3692 }
3693 return -EINVAL;
3694}
3695
3696int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3697 u8 voltage_type,
3698 u16 nominal_voltage,
3699 u16 *true_voltage)
3700{
3701 u16 min_voltage, max_voltage, voltage_step;
3702
3703 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3704 return -EINVAL;
3705 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3706 return -EINVAL;
3707 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3708 return -EINVAL;
3709
3710 if (nominal_voltage <= min_voltage)
3711 *true_voltage = min_voltage;
3712 else if (nominal_voltage >= max_voltage)
3713 *true_voltage = max_voltage;
3714 else
3715 *true_voltage = min_voltage +
3716 ((nominal_voltage - min_voltage) / voltage_step) *
3717 voltage_step;
3718
3719 return 0;
3720}
3721
3722int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3723 u8 voltage_type, u8 voltage_mode,
3724 struct atom_voltage_table *voltage_table)
3725{
3726 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3727 u8 frev, crev;
3728 u16 data_offset, size;
3729 int i, ret;
3730 union voltage_object_info *voltage_info;
3731 union voltage_object *voltage_object = NULL;
3732
3733 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3734 &frev, &crev, &data_offset)) {
3735 voltage_info = (union voltage_object_info *)
3736 (rdev->mode_info.atom_context->bios + data_offset);
3737
3738 switch (frev) {
3739 case 1:
3740 case 2:
3741 switch (crev) {
3742 case 1:
3743 DRM_ERROR("old table version %d, %d\n", frev, crev);
3744 return -EINVAL;
3745 case 2:
3746 voltage_object = (union voltage_object *)
3747 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3748 if (voltage_object) {
3749 ATOM_VOLTAGE_FORMULA_V2 *formula =
3750 &voltage_object->v2.asFormula;
3751 VOLTAGE_LUT_ENTRY *lut;
3752 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3753 return -EINVAL;
3754 lut = &formula->asVIDAdjustEntries[0];
3755 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3756 voltage_table->entries[i].value =
3757 le16_to_cpu(lut->usVoltageValue);
3758 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3759 voltage_table->entries[i].value,
3760 voltage_type,
3761 &voltage_table->entries[i].smio_low,
3762 &voltage_table->mask_low);
3763 if (ret)
3764 return ret;
3765 lut = (VOLTAGE_LUT_ENTRY *)
3766 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3767 }
3768 voltage_table->count = formula->ucNumOfVoltageEntries;
3769 return 0;
3770 }
3771 break;
3772 default:
3773 DRM_ERROR("unknown voltage object table\n");
3774 return -EINVAL;
3775 }
3776 break;
3777 case 3:
3778 switch (crev) {
3779 case 1:
3780 voltage_object = (union voltage_object *)
3781 atom_lookup_voltage_object_v3(&voltage_info->v3,
3782 voltage_type, voltage_mode);
3783 if (voltage_object) {
3784 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3785 &voltage_object->v3.asGpioVoltageObj;
3786 VOLTAGE_LUT_ENTRY_V2 *lut;
3787 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3788 return -EINVAL;
3789 lut = &gpio->asVolGpioLut[0];
3790 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3791 voltage_table->entries[i].value =
3792 le16_to_cpu(lut->usVoltageValue);
3793 voltage_table->entries[i].smio_low =
3794 le32_to_cpu(lut->ulVoltageId);
3795 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3796 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3797 }
3798 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3799 voltage_table->count = gpio->ucGpioEntryNum;
3800 voltage_table->phase_delay = gpio->ucPhaseDelay;
3801 return 0;
3802 }
3803 break;
3804 default:
3805 DRM_ERROR("unknown voltage object table\n");
3806 return -EINVAL;
3807 }
3808 break;
3809 default:
3810 DRM_ERROR("unknown voltage object table\n");
3811 return -EINVAL;
3812 }
3813 }
3814 return -EINVAL;
3815}
3816
3817union vram_info {
3818 struct _ATOM_VRAM_INFO_V3 v1_3;
3819 struct _ATOM_VRAM_INFO_V4 v1_4;
3820 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3821};
3822
3823int radeon_atom_get_memory_info(struct radeon_device *rdev,
3824 u8 module_index, struct atom_memory_info *mem_info)
3825{
3826 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3827 u8 frev, crev, i;
3828 u16 data_offset, size;
3829 union vram_info *vram_info;
3830
3831 memset(mem_info, 0, sizeof(struct atom_memory_info));
3832
3833 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3834 &frev, &crev, &data_offset)) {
3835 vram_info = (union vram_info *)
3836 (rdev->mode_info.atom_context->bios + data_offset);
3837 switch (frev) {
3838 case 1:
3839 switch (crev) {
3840 case 3:
3841
3842 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3843 ATOM_VRAM_MODULE_V3 *vram_module =
3844 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3845
3846 for (i = 0; i < module_index; i++) {
3847 if (le16_to_cpu(vram_module->usSize) == 0)
3848 return -EINVAL;
3849 vram_module = (ATOM_VRAM_MODULE_V3 *)
3850 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3851 }
3852 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3853 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3854 } else
3855 return -EINVAL;
3856 break;
3857 case 4:
3858
3859 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3860 ATOM_VRAM_MODULE_V4 *vram_module =
3861 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3862
3863 for (i = 0; i < module_index; i++) {
3864 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3865 return -EINVAL;
3866 vram_module = (ATOM_VRAM_MODULE_V4 *)
3867 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3868 }
3869 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3870 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3871 } else
3872 return -EINVAL;
3873 break;
3874 default:
3875 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3876 return -EINVAL;
3877 }
3878 break;
3879 case 2:
3880 switch (crev) {
3881 case 1:
3882
3883 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3884 ATOM_VRAM_MODULE_V7 *vram_module =
3885 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3886
3887 for (i = 0; i < module_index; i++) {
3888 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3889 return -EINVAL;
3890 vram_module = (ATOM_VRAM_MODULE_V7 *)
3891 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3892 }
3893 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3894 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3895 } else
3896 return -EINVAL;
3897 break;
3898 default:
3899 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3900 return -EINVAL;
3901 }
3902 break;
3903 default:
3904 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3905 return -EINVAL;
3906 }
3907 return 0;
3908 }
3909 return -EINVAL;
3910}
3911
3912int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3913 bool gddr5, u8 module_index,
3914 struct atom_memory_clock_range_table *mclk_range_table)
3915{
3916 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3917 u8 frev, crev, i;
3918 u16 data_offset, size;
3919 union vram_info *vram_info;
3920 u32 mem_timing_size = gddr5 ?
3921 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3922
3923 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3924
3925 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3926 &frev, &crev, &data_offset)) {
3927 vram_info = (union vram_info *)
3928 (rdev->mode_info.atom_context->bios + data_offset);
3929 switch (frev) {
3930 case 1:
3931 switch (crev) {
3932 case 3:
3933 DRM_ERROR("old table version %d, %d\n", frev, crev);
3934 return -EINVAL;
3935 case 4:
3936
3937 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3938 ATOM_VRAM_MODULE_V4 *vram_module =
3939 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3940 ATOM_MEMORY_TIMING_FORMAT *format;
3941
3942 for (i = 0; i < module_index; i++) {
3943 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3944 return -EINVAL;
3945 vram_module = (ATOM_VRAM_MODULE_V4 *)
3946 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3947 }
3948 mclk_range_table->num_entries = (u8)
3949 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3950 mem_timing_size);
3951 format = &vram_module->asMemTiming[0];
3952 for (i = 0; i < mclk_range_table->num_entries; i++) {
3953 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3954 format = (ATOM_MEMORY_TIMING_FORMAT *)
3955 ((u8 *)format + mem_timing_size);
3956 }
3957 } else
3958 return -EINVAL;
3959 break;
3960 default:
3961 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3962 return -EINVAL;
3963 }
3964 break;
3965 case 2:
3966 DRM_ERROR("new table version %d, %d\n", frev, crev);
3967 return -EINVAL;
3968 default:
3969 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3970 return -EINVAL;
3971 }
3972 return 0;
3973 }
3974 return -EINVAL;
3975}
3976
3977#define MEM_ID_MASK 0xff000000
3978#define MEM_ID_SHIFT 24
3979#define CLOCK_RANGE_MASK 0x00ffffff
3980#define CLOCK_RANGE_SHIFT 0
3981#define LOW_NIBBLE_MASK 0xf
3982#define DATA_EQU_PREV 0
3983#define DATA_FROM_TABLE 4
3984
3985int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3986 u8 module_index,
3987 struct atom_mc_reg_table *reg_table)
3988{
3989 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3990 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3991 u32 i = 0, j;
3992 u16 data_offset, size;
3993 union vram_info *vram_info;
3994
3995 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3996
3997 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3998 &frev, &crev, &data_offset)) {
3999 vram_info = (union vram_info *)
4000 (rdev->mode_info.atom_context->bios + data_offset);
4001 switch (frev) {
4002 case 1:
4003 DRM_ERROR("old table version %d, %d\n", frev, crev);
4004 return -EINVAL;
4005 case 2:
4006 switch (crev) {
4007 case 1:
4008 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4009 ATOM_INIT_REG_BLOCK *reg_block =
4010 (ATOM_INIT_REG_BLOCK *)
4011 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4012 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4013 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4014 ((u8 *)reg_block + (2 * sizeof(u16)) +
4015 le16_to_cpu(reg_block->usRegIndexTblSize));
4016 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4017 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4018 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4019 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4020 return -EINVAL;
4021 while (i < num_entries) {
4022 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4023 break;
4024 reg_table->mc_reg_address[i].s1 =
4025 (u16)(le16_to_cpu(format->usRegIndex));
4026 reg_table->mc_reg_address[i].pre_reg_data =
4027 (u8)(format->ucPreRegDataLength);
4028 i++;
4029 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4030 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4031 }
4032 reg_table->last = i;
4033 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4034 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4035 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4036 >> MEM_ID_SHIFT);
4037 if (module_index == t_mem_id) {
4038 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4039 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4040 >> CLOCK_RANGE_SHIFT);
4041 for (i = 0, j = 1; i < reg_table->last; i++) {
4042 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4043 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4044 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4045 j++;
4046 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4047 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4048 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4049 }
4050 }
4051 num_ranges++;
4052 }
4053 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4054 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4055 }
4056 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4057 return -EINVAL;
4058 reg_table->num_entries = num_ranges;
4059 } else
4060 return -EINVAL;
4061 break;
4062 default:
4063 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4064 return -EINVAL;
4065 }
4066 break;
4067 default:
4068 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4069 return -EINVAL;
4070 }
4071 return 0;
4072 }
4073 return -EINVAL;
4074}
4075
4076void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4077{
4078 struct radeon_device *rdev = dev->dev_private;
4079 uint32_t bios_2_scratch, bios_6_scratch;
4080
4081 if (rdev->family >= CHIP_R600) {
4082 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4083 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4084 } else {
4085 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4086 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4087 }
4088
4089
4090 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4091
4092
4093 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4094
4095
4096 if (ASIC_IS_DCE4(rdev))
4097 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4098
4099 if (rdev->family >= CHIP_R600) {
4100 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4101 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4102 } else {
4103 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4104 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4105 }
4106
4107}
4108
4109void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4110{
4111 uint32_t scratch_reg;
4112 int i;
4113
4114 if (rdev->family >= CHIP_R600)
4115 scratch_reg = R600_BIOS_0_SCRATCH;
4116 else
4117 scratch_reg = RADEON_BIOS_0_SCRATCH;
4118
4119 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4120 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4121}
4122
4123void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4124{
4125 uint32_t scratch_reg;
4126 int i;
4127
4128 if (rdev->family >= CHIP_R600)
4129 scratch_reg = R600_BIOS_0_SCRATCH;
4130 else
4131 scratch_reg = RADEON_BIOS_0_SCRATCH;
4132
4133 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4134 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4135}
4136
4137void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4138{
4139 struct drm_device *dev = encoder->dev;
4140 struct radeon_device *rdev = dev->dev_private;
4141 uint32_t bios_6_scratch;
4142
4143 if (rdev->family >= CHIP_R600)
4144 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4145 else
4146 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4147
4148 if (lock) {
4149 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4150 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4151 } else {
4152 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4153 bios_6_scratch |= ATOM_S6_ACC_MODE;
4154 }
4155
4156 if (rdev->family >= CHIP_R600)
4157 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4158 else
4159 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4160}
4161
4162
4163void
4164radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4165 struct drm_encoder *encoder,
4166 bool connected)
4167{
4168 struct drm_device *dev = connector->dev;
4169 struct radeon_device *rdev = dev->dev_private;
4170 struct radeon_connector *radeon_connector =
4171 to_radeon_connector(connector);
4172 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4173 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4174
4175 if (rdev->family >= CHIP_R600) {
4176 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4177 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4178 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4179 } else {
4180 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4181 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4182 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4183 }
4184
4185 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4186 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4187 if (connected) {
4188 DRM_DEBUG_KMS("TV1 connected\n");
4189 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4190 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4191 } else {
4192 DRM_DEBUG_KMS("TV1 disconnected\n");
4193 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4194 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4195 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4196 }
4197 }
4198 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4199 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4200 if (connected) {
4201 DRM_DEBUG_KMS("CV connected\n");
4202 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4203 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4204 } else {
4205 DRM_DEBUG_KMS("CV disconnected\n");
4206 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4207 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4208 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4209 }
4210 }
4211 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4212 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4213 if (connected) {
4214 DRM_DEBUG_KMS("LCD1 connected\n");
4215 bios_0_scratch |= ATOM_S0_LCD1;
4216 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4217 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4218 } else {
4219 DRM_DEBUG_KMS("LCD1 disconnected\n");
4220 bios_0_scratch &= ~ATOM_S0_LCD1;
4221 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4222 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4223 }
4224 }
4225 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4226 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4227 if (connected) {
4228 DRM_DEBUG_KMS("CRT1 connected\n");
4229 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4230 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4231 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4232 } else {
4233 DRM_DEBUG_KMS("CRT1 disconnected\n");
4234 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4235 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4236 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4237 }
4238 }
4239 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4240 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4241 if (connected) {
4242 DRM_DEBUG_KMS("CRT2 connected\n");
4243 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4244 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4245 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4246 } else {
4247 DRM_DEBUG_KMS("CRT2 disconnected\n");
4248 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4249 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4250 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4251 }
4252 }
4253 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4254 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4255 if (connected) {
4256 DRM_DEBUG_KMS("DFP1 connected\n");
4257 bios_0_scratch |= ATOM_S0_DFP1;
4258 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4259 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4260 } else {
4261 DRM_DEBUG_KMS("DFP1 disconnected\n");
4262 bios_0_scratch &= ~ATOM_S0_DFP1;
4263 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4264 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4265 }
4266 }
4267 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4268 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4269 if (connected) {
4270 DRM_DEBUG_KMS("DFP2 connected\n");
4271 bios_0_scratch |= ATOM_S0_DFP2;
4272 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4273 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4274 } else {
4275 DRM_DEBUG_KMS("DFP2 disconnected\n");
4276 bios_0_scratch &= ~ATOM_S0_DFP2;
4277 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4278 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4279 }
4280 }
4281 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4282 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4283 if (connected) {
4284 DRM_DEBUG_KMS("DFP3 connected\n");
4285 bios_0_scratch |= ATOM_S0_DFP3;
4286 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4287 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4288 } else {
4289 DRM_DEBUG_KMS("DFP3 disconnected\n");
4290 bios_0_scratch &= ~ATOM_S0_DFP3;
4291 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4292 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4293 }
4294 }
4295 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4296 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4297 if (connected) {
4298 DRM_DEBUG_KMS("DFP4 connected\n");
4299 bios_0_scratch |= ATOM_S0_DFP4;
4300 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4301 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4302 } else {
4303 DRM_DEBUG_KMS("DFP4 disconnected\n");
4304 bios_0_scratch &= ~ATOM_S0_DFP4;
4305 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4306 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4307 }
4308 }
4309 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4310 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4311 if (connected) {
4312 DRM_DEBUG_KMS("DFP5 connected\n");
4313 bios_0_scratch |= ATOM_S0_DFP5;
4314 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4315 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4316 } else {
4317 DRM_DEBUG_KMS("DFP5 disconnected\n");
4318 bios_0_scratch &= ~ATOM_S0_DFP5;
4319 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4320 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4321 }
4322 }
4323 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4324 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4325 if (connected) {
4326 DRM_DEBUG_KMS("DFP6 connected\n");
4327 bios_0_scratch |= ATOM_S0_DFP6;
4328 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4329 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4330 } else {
4331 DRM_DEBUG_KMS("DFP6 disconnected\n");
4332 bios_0_scratch &= ~ATOM_S0_DFP6;
4333 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4334 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4335 }
4336 }
4337
4338 if (rdev->family >= CHIP_R600) {
4339 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4340 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4341 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4342 } else {
4343 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4344 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4345 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4346 }
4347}
4348
4349void
4350radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4351{
4352 struct drm_device *dev = encoder->dev;
4353 struct radeon_device *rdev = dev->dev_private;
4354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4355 uint32_t bios_3_scratch;
4356
4357 if (ASIC_IS_DCE4(rdev))
4358 return;
4359
4360 if (rdev->family >= CHIP_R600)
4361 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4362 else
4363 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4364
4365 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4366 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4367 bios_3_scratch |= (crtc << 18);
4368 }
4369 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4370 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4371 bios_3_scratch |= (crtc << 24);
4372 }
4373 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4374 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4375 bios_3_scratch |= (crtc << 16);
4376 }
4377 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4378 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4379 bios_3_scratch |= (crtc << 20);
4380 }
4381 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4382 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4383 bios_3_scratch |= (crtc << 17);
4384 }
4385 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4386 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4387 bios_3_scratch |= (crtc << 19);
4388 }
4389 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4390 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4391 bios_3_scratch |= (crtc << 23);
4392 }
4393 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4394 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4395 bios_3_scratch |= (crtc << 25);
4396 }
4397
4398 if (rdev->family >= CHIP_R600)
4399 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4400 else
4401 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4402}
4403
4404void
4405radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4406{
4407 struct drm_device *dev = encoder->dev;
4408 struct radeon_device *rdev = dev->dev_private;
4409 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4410 uint32_t bios_2_scratch;
4411
4412 if (ASIC_IS_DCE4(rdev))
4413 return;
4414
4415 if (rdev->family >= CHIP_R600)
4416 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4417 else
4418 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4419
4420 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4421 if (on)
4422 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4423 else
4424 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4425 }
4426 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4427 if (on)
4428 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4429 else
4430 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4431 }
4432 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4433 if (on)
4434 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4435 else
4436 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4437 }
4438 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4439 if (on)
4440 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4441 else
4442 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4443 }
4444 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4445 if (on)
4446 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4447 else
4448 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4449 }
4450 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4451 if (on)
4452 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4453 else
4454 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4455 }
4456 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4457 if (on)
4458 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4459 else
4460 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4461 }
4462 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4463 if (on)
4464 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4465 else
4466 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4467 }
4468 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4469 if (on)
4470 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4471 else
4472 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4473 }
4474 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4475 if (on)
4476 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4477 else
4478 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4479 }
4480
4481 if (rdev->family >= CHIP_R600)
4482 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4483 else
4484 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4485}
4486
