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29#include <linux/pm_runtime.h>
30#include <linux/slab.h>
31#include <linux/uaccess.h>
32#include <linux/vga_switcheroo.h>
33
34#include <drm/drm_fb_helper.h>
35#include <drm/drm_file.h>
36#include <drm/drm_ioctl.h>
37#include <drm/drm_pci.h>
38#include <drm/radeon_drm.h>
39
40#include "radeon.h"
41#include "radeon_asic.h"
42
43#if defined(CONFIG_VGA_SWITCHEROO)
44bool radeon_has_atpx(void);
45#else
46static inline bool radeon_has_atpx(void) { return false; }
47#endif
48
49
50
51
52
53
54
55
56
57
58
59
60void radeon_driver_unload_kms(struct drm_device *dev)
61{
62 struct radeon_device *rdev = dev->dev_private;
63
64 if (rdev == NULL)
65 return;
66
67 if (rdev->rmmio == NULL)
68 goto done_free;
69
70 if (radeon_is_px(dev)) {
71 pm_runtime_get_sync(dev->dev);
72 pm_runtime_forbid(dev->dev);
73 }
74
75 radeon_acpi_fini(rdev);
76
77 radeon_modeset_fini(rdev);
78 radeon_device_fini(rdev);
79
80done_free:
81 kfree(rdev);
82 dev->dev_private = NULL;
83}
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
99{
100 struct radeon_device *rdev;
101 int r, acpi_status;
102
103 if (!radeon_si_support) {
104 switch (flags & RADEON_FAMILY_MASK) {
105 case CHIP_TAHITI:
106 case CHIP_PITCAIRN:
107 case CHIP_VERDE:
108 case CHIP_OLAND:
109 case CHIP_HAINAN:
110 dev_info(dev->dev,
111 "SI support disabled by module param\n");
112 return -ENODEV;
113 }
114 }
115 if (!radeon_cik_support) {
116 switch (flags & RADEON_FAMILY_MASK) {
117 case CHIP_KAVERI:
118 case CHIP_BONAIRE:
119 case CHIP_HAWAII:
120 case CHIP_KABINI:
121 case CHIP_MULLINS:
122 dev_info(dev->dev,
123 "CIK support disabled by module param\n");
124 return -ENODEV;
125 }
126 }
127
128 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
129 if (rdev == NULL) {
130 return -ENOMEM;
131 }
132 dev->dev_private = (void *)rdev;
133
134
135 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
136 flags |= RADEON_IS_AGP;
137 } else if (pci_is_pcie(dev->pdev)) {
138 flags |= RADEON_IS_PCIE;
139 } else {
140 flags |= RADEON_IS_PCI;
141 }
142
143 if ((radeon_runtime_pm != 0) &&
144 radeon_has_atpx() &&
145 ((flags & RADEON_IS_IGP) == 0) &&
146 !pci_is_thunderbolt_attached(dev->pdev))
147 flags |= RADEON_IS_PX;
148
149
150
151
152
153
154
155 r = radeon_device_init(rdev, dev, dev->pdev, flags);
156 if (r) {
157 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
158 goto out;
159 }
160
161
162
163
164
165 r = radeon_modeset_init(rdev);
166 if (r)
167 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
168
169
170
171
172 if (!r) {
173 acpi_status = radeon_acpi_init(rdev);
174 if (acpi_status)
175 dev_dbg(&dev->pdev->dev,
176 "Error during ACPI methods call\n");
177 }
178
179 if (radeon_is_px(dev)) {
180 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
181 pm_runtime_use_autosuspend(dev->dev);
182 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
183 pm_runtime_set_active(dev->dev);
184 pm_runtime_allow(dev->dev);
185 pm_runtime_mark_last_busy(dev->dev);
186 pm_runtime_put_autosuspend(dev->dev);
187 }
188
189out:
190 if (r)
191 radeon_driver_unload_kms(dev);
192
193
194 return r;
195}
196
197
198
199
200
201
202
203
204
205
206
207static void radeon_set_filp_rights(struct drm_device *dev,
208 struct drm_file **owner,
209 struct drm_file *applier,
210 uint32_t *value)
211{
212 struct radeon_device *rdev = dev->dev_private;
213
214 mutex_lock(&rdev->gem.mutex);
215 if (*value == 1) {
216
217 if (!*owner)
218 *owner = applier;
219 } else if (*value == 0) {
220
221 if (*owner == applier)
222 *owner = NULL;
223 }
224 *value = *owner == applier ? 1 : 0;
225 mutex_unlock(&rdev->gem.mutex);
226}
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
244{
245 struct radeon_device *rdev = dev->dev_private;
246 struct drm_radeon_info *info = data;
247 struct radeon_mode_info *minfo = &rdev->mode_info;
248 uint32_t *value, value_tmp, *value_ptr, value_size;
249 uint64_t value64;
250 struct drm_crtc *crtc;
251 int i, found;
252
253 value_ptr = (uint32_t *)((unsigned long)info->value);
254 value = &value_tmp;
255 value_size = sizeof(uint32_t);
256
257 switch (info->request) {
258 case RADEON_INFO_DEVICE_ID:
259 *value = dev->pdev->device;
260 break;
261 case RADEON_INFO_NUM_GB_PIPES:
262 *value = rdev->num_gb_pipes;
263 break;
264 case RADEON_INFO_NUM_Z_PIPES:
265 *value = rdev->num_z_pipes;
266 break;
267 case RADEON_INFO_ACCEL_WORKING:
268
269 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
270 *value = false;
271 else
272 *value = rdev->accel_working;
273 break;
274 case RADEON_INFO_CRTC_FROM_ID:
275 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
276 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
277 return -EFAULT;
278 }
279 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
280 crtc = (struct drm_crtc *)minfo->crtcs[i];
281 if (crtc && crtc->base.id == *value) {
282 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
283 *value = radeon_crtc->crtc_id;
284 found = 1;
285 break;
286 }
287 }
288 if (!found) {
289 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
290 return -EINVAL;
291 }
292 break;
293 case RADEON_INFO_ACCEL_WORKING2:
294 if (rdev->family == CHIP_HAWAII) {
295 if (rdev->accel_working) {
296 if (rdev->new_fw)
297 *value = 3;
298 else
299 *value = 2;
300 } else {
301 *value = 0;
302 }
303 } else {
304 *value = rdev->accel_working;
305 }
306 break;
307 case RADEON_INFO_TILING_CONFIG:
308 if (rdev->family >= CHIP_BONAIRE)
309 *value = rdev->config.cik.tile_config;
310 else if (rdev->family >= CHIP_TAHITI)
311 *value = rdev->config.si.tile_config;
312 else if (rdev->family >= CHIP_CAYMAN)
313 *value = rdev->config.cayman.tile_config;
314 else if (rdev->family >= CHIP_CEDAR)
315 *value = rdev->config.evergreen.tile_config;
316 else if (rdev->family >= CHIP_RV770)
317 *value = rdev->config.rv770.tile_config;
318 else if (rdev->family >= CHIP_R600)
319 *value = rdev->config.r600.tile_config;
320 else {
321 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
322 return -EINVAL;
323 }
324 break;
325 case RADEON_INFO_WANT_HYPERZ:
326
327
328
329
330
331
332 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
333 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
334 return -EFAULT;
335 }
336 if (*value >= 2) {
337 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
338 return -EINVAL;
339 }
340 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
341 break;
342 case RADEON_INFO_WANT_CMASK:
343
344 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
345 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
346 return -EFAULT;
347 }
348 if (*value >= 2) {
349 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
350 return -EINVAL;
351 }
352 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
353 break;
354 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
355
356 if (rdev->asic->get_xclk)
357 *value = radeon_get_xclk(rdev) * 10;
358 else
359 *value = rdev->clock.spll.reference_freq * 10;
360 break;
361 case RADEON_INFO_NUM_BACKENDS:
362 if (rdev->family >= CHIP_BONAIRE)
363 *value = rdev->config.cik.max_backends_per_se *
364 rdev->config.cik.max_shader_engines;
365 else if (rdev->family >= CHIP_TAHITI)
366 *value = rdev->config.si.max_backends_per_se *
367 rdev->config.si.max_shader_engines;
368 else if (rdev->family >= CHIP_CAYMAN)
369 *value = rdev->config.cayman.max_backends_per_se *
370 rdev->config.cayman.max_shader_engines;
371 else if (rdev->family >= CHIP_CEDAR)
372 *value = rdev->config.evergreen.max_backends;
373 else if (rdev->family >= CHIP_RV770)
374 *value = rdev->config.rv770.max_backends;
375 else if (rdev->family >= CHIP_R600)
376 *value = rdev->config.r600.max_backends;
377 else {
378 return -EINVAL;
379 }
380 break;
381 case RADEON_INFO_NUM_TILE_PIPES:
382 if (rdev->family >= CHIP_BONAIRE)
383 *value = rdev->config.cik.max_tile_pipes;
384 else if (rdev->family >= CHIP_TAHITI)
385 *value = rdev->config.si.max_tile_pipes;
386 else if (rdev->family >= CHIP_CAYMAN)
387 *value = rdev->config.cayman.max_tile_pipes;
388 else if (rdev->family >= CHIP_CEDAR)
389 *value = rdev->config.evergreen.max_tile_pipes;
390 else if (rdev->family >= CHIP_RV770)
391 *value = rdev->config.rv770.max_tile_pipes;
392 else if (rdev->family >= CHIP_R600)
393 *value = rdev->config.r600.max_tile_pipes;
394 else {
395 return -EINVAL;
396 }
397 break;
398 case RADEON_INFO_FUSION_GART_WORKING:
399 *value = 1;
400 break;
401 case RADEON_INFO_BACKEND_MAP:
402 if (rdev->family >= CHIP_BONAIRE)
403 *value = rdev->config.cik.backend_map;
404 else if (rdev->family >= CHIP_TAHITI)
405 *value = rdev->config.si.backend_map;
406 else if (rdev->family >= CHIP_CAYMAN)
407 *value = rdev->config.cayman.backend_map;
408 else if (rdev->family >= CHIP_CEDAR)
409 *value = rdev->config.evergreen.backend_map;
410 else if (rdev->family >= CHIP_RV770)
411 *value = rdev->config.rv770.backend_map;
412 else if (rdev->family >= CHIP_R600)
413 *value = rdev->config.r600.backend_map;
414 else {
415 return -EINVAL;
416 }
417 break;
418 case RADEON_INFO_VA_START:
419
420 if (rdev->family < CHIP_CAYMAN)
421 return -EINVAL;
422 *value = RADEON_VA_RESERVED_SIZE;
423 break;
424 case RADEON_INFO_IB_VM_MAX_SIZE:
425
426 if (rdev->family < CHIP_CAYMAN)
427 return -EINVAL;
428 *value = RADEON_IB_VM_MAX_SIZE;
429 break;
430 case RADEON_INFO_MAX_PIPES:
431 if (rdev->family >= CHIP_BONAIRE)
432 *value = rdev->config.cik.max_cu_per_sh;
433 else if (rdev->family >= CHIP_TAHITI)
434 *value = rdev->config.si.max_cu_per_sh;
435 else if (rdev->family >= CHIP_CAYMAN)
436 *value = rdev->config.cayman.max_pipes_per_simd;
437 else if (rdev->family >= CHIP_CEDAR)
438 *value = rdev->config.evergreen.max_pipes;
439 else if (rdev->family >= CHIP_RV770)
440 *value = rdev->config.rv770.max_pipes;
441 else if (rdev->family >= CHIP_R600)
442 *value = rdev->config.r600.max_pipes;
443 else {
444 return -EINVAL;
445 }
446 break;
447 case RADEON_INFO_TIMESTAMP:
448 if (rdev->family < CHIP_R600) {
449 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
450 return -EINVAL;
451 }
452 value = (uint32_t*)&value64;
453 value_size = sizeof(uint64_t);
454 value64 = radeon_get_gpu_clock_counter(rdev);
455 break;
456 case RADEON_INFO_MAX_SE:
457 if (rdev->family >= CHIP_BONAIRE)
458 *value = rdev->config.cik.max_shader_engines;
459 else if (rdev->family >= CHIP_TAHITI)
460 *value = rdev->config.si.max_shader_engines;
461 else if (rdev->family >= CHIP_CAYMAN)
462 *value = rdev->config.cayman.max_shader_engines;
463 else if (rdev->family >= CHIP_CEDAR)
464 *value = rdev->config.evergreen.num_ses;
465 else
466 *value = 1;
467 break;
468 case RADEON_INFO_MAX_SH_PER_SE:
469 if (rdev->family >= CHIP_BONAIRE)
470 *value = rdev->config.cik.max_sh_per_se;
471 else if (rdev->family >= CHIP_TAHITI)
472 *value = rdev->config.si.max_sh_per_se;
473 else
474 return -EINVAL;
475 break;
476 case RADEON_INFO_FASTFB_WORKING:
477 *value = rdev->fastfb_working;
478 break;
479 case RADEON_INFO_RING_WORKING:
480 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
481 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
482 return -EFAULT;
483 }
484 switch (*value) {
485 case RADEON_CS_RING_GFX:
486 case RADEON_CS_RING_COMPUTE:
487 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
488 break;
489 case RADEON_CS_RING_DMA:
490 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
491 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
492 break;
493 case RADEON_CS_RING_UVD:
494 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
495 break;
496 case RADEON_CS_RING_VCE:
497 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
498 break;
499 default:
500 return -EINVAL;
501 }
502 break;
503 case RADEON_INFO_SI_TILE_MODE_ARRAY:
504 if (rdev->family >= CHIP_BONAIRE) {
505 value = rdev->config.cik.tile_mode_array;
506 value_size = sizeof(uint32_t)*32;
507 } else if (rdev->family >= CHIP_TAHITI) {
508 value = rdev->config.si.tile_mode_array;
509 value_size = sizeof(uint32_t)*32;
510 } else {
511 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
512 return -EINVAL;
513 }
514 break;
515 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
516 if (rdev->family >= CHIP_BONAIRE) {
517 value = rdev->config.cik.macrotile_mode_array;
518 value_size = sizeof(uint32_t)*16;
519 } else {
520 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
521 return -EINVAL;
522 }
523 break;
524 case RADEON_INFO_SI_CP_DMA_COMPUTE:
525 *value = 1;
526 break;
527 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
528 if (rdev->family >= CHIP_BONAIRE) {
529 *value = rdev->config.cik.backend_enable_mask;
530 } else if (rdev->family >= CHIP_TAHITI) {
531 *value = rdev->config.si.backend_enable_mask;
532 } else {
533 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
534 }
535 break;
536 case RADEON_INFO_MAX_SCLK:
537 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
538 rdev->pm.dpm_enabled)
539 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
540 else
541 *value = rdev->pm.default_sclk * 10;
542 break;
543 case RADEON_INFO_VCE_FW_VERSION:
544 *value = rdev->vce.fw_version;
545 break;
546 case RADEON_INFO_VCE_FB_VERSION:
547 *value = rdev->vce.fb_version;
548 break;
549 case RADEON_INFO_NUM_BYTES_MOVED:
550 value = (uint32_t*)&value64;
551 value_size = sizeof(uint64_t);
552 value64 = atomic64_read(&rdev->num_bytes_moved);
553 break;
554 case RADEON_INFO_VRAM_USAGE:
555 value = (uint32_t*)&value64;
556 value_size = sizeof(uint64_t);
557 value64 = atomic64_read(&rdev->vram_usage);
558 break;
559 case RADEON_INFO_GTT_USAGE:
560 value = (uint32_t*)&value64;
561 value_size = sizeof(uint64_t);
562 value64 = atomic64_read(&rdev->gtt_usage);
563 break;
564 case RADEON_INFO_ACTIVE_CU_COUNT:
565 if (rdev->family >= CHIP_BONAIRE)
566 *value = rdev->config.cik.active_cus;
567 else if (rdev->family >= CHIP_TAHITI)
568 *value = rdev->config.si.active_cus;
569 else if (rdev->family >= CHIP_CAYMAN)
570 *value = rdev->config.cayman.active_simds;
571 else if (rdev->family >= CHIP_CEDAR)
572 *value = rdev->config.evergreen.active_simds;
573 else if (rdev->family >= CHIP_RV770)
574 *value = rdev->config.rv770.active_simds;
575 else if (rdev->family >= CHIP_R600)
576 *value = rdev->config.r600.active_simds;
577 else
578 *value = 1;
579 break;
580 case RADEON_INFO_CURRENT_GPU_TEMP:
581
582 if (rdev->asic->pm.get_temperature)
583 *value = radeon_get_temperature(rdev);
584 else
585 *value = 0;
586 break;
587 case RADEON_INFO_CURRENT_GPU_SCLK:
588
589 if (rdev->pm.dpm_enabled)
590 *value = radeon_dpm_get_current_sclk(rdev) / 100;
591 else
592 *value = rdev->pm.current_sclk / 100;
593 break;
594 case RADEON_INFO_CURRENT_GPU_MCLK:
595
596 if (rdev->pm.dpm_enabled)
597 *value = radeon_dpm_get_current_mclk(rdev) / 100;
598 else
599 *value = rdev->pm.current_mclk / 100;
600 break;
601 case RADEON_INFO_READ_REG:
602 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
603 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
604 return -EFAULT;
605 }
606 if (radeon_get_allowed_info_register(rdev, *value, value))
607 return -EINVAL;
608 break;
609 case RADEON_INFO_VA_UNMAP_WORKING:
610 *value = true;
611 break;
612 case RADEON_INFO_GPU_RESET_COUNTER:
613 *value = atomic_read(&rdev->gpu_reset_counter);
614 break;
615 default:
616 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
617 return -EINVAL;
618 }
619 if (copy_to_user(value_ptr, (char*)value, value_size)) {
620 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
621 return -EFAULT;
622 }
623 return 0;
624}
625
626
627
628
629
630
631
632
633
634
635
636
637void radeon_driver_lastclose_kms(struct drm_device *dev)
638{
639 drm_fb_helper_lastclose(dev);
640 vga_switcheroo_process_delayed_switch();
641}
642
643
644
645
646
647
648
649
650
651
652int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
653{
654 struct radeon_device *rdev = dev->dev_private;
655 int r;
656
657 file_priv->driver_priv = NULL;
658
659 r = pm_runtime_get_sync(dev->dev);
660 if (r < 0)
661 return r;
662
663
664 if (rdev->family >= CHIP_CAYMAN) {
665 struct radeon_fpriv *fpriv;
666 struct radeon_vm *vm;
667
668 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
669 if (unlikely(!fpriv)) {
670 r = -ENOMEM;
671 goto out_suspend;
672 }
673
674 if (rdev->accel_working) {
675 vm = &fpriv->vm;
676 r = radeon_vm_init(rdev, vm);
677 if (r) {
678 kfree(fpriv);
679 goto out_suspend;
680 }
681
682 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
683 if (r) {
684 radeon_vm_fini(rdev, vm);
685 kfree(fpriv);
686 goto out_suspend;
687 }
688
689
690
691 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
692 rdev->ring_tmp_bo.bo);
693 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
694 RADEON_VA_IB_OFFSET,
695 RADEON_VM_PAGE_READABLE |
696 RADEON_VM_PAGE_SNOOPED);
697 if (r) {
698 radeon_vm_fini(rdev, vm);
699 kfree(fpriv);
700 goto out_suspend;
701 }
702 }
703 file_priv->driver_priv = fpriv;
704 }
705
706out_suspend:
707 pm_runtime_mark_last_busy(dev->dev);
708 pm_runtime_put_autosuspend(dev->dev);
709 return r;
710}
711
712
713
714
715
716
717
718
719
720
721void radeon_driver_postclose_kms(struct drm_device *dev,
722 struct drm_file *file_priv)
723{
724 struct radeon_device *rdev = dev->dev_private;
725
726 pm_runtime_get_sync(dev->dev);
727
728 mutex_lock(&rdev->gem.mutex);
729 if (rdev->hyperz_filp == file_priv)
730 rdev->hyperz_filp = NULL;
731 if (rdev->cmask_filp == file_priv)
732 rdev->cmask_filp = NULL;
733 mutex_unlock(&rdev->gem.mutex);
734
735 radeon_uvd_free_handles(rdev, file_priv);
736 radeon_vce_free_handles(rdev, file_priv);
737
738
739 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
740 struct radeon_fpriv *fpriv = file_priv->driver_priv;
741 struct radeon_vm *vm = &fpriv->vm;
742 int r;
743
744 if (rdev->accel_working) {
745 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
746 if (!r) {
747 if (vm->ib_bo_va)
748 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
749 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
750 }
751 radeon_vm_fini(rdev, vm);
752 }
753
754 kfree(fpriv);
755 file_priv->driver_priv = NULL;
756 }
757 pm_runtime_mark_last_busy(dev->dev);
758 pm_runtime_put_autosuspend(dev->dev);
759}
760
761
762
763
764
765
766
767
768
769
770
771
772
773u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
774{
775 int vpos, hpos, stat;
776 u32 count;
777 struct radeon_device *rdev = dev->dev_private;
778
779 if (pipe >= rdev->num_crtc) {
780 DRM_ERROR("Invalid crtc %u\n", pipe);
781 return -EINVAL;
782 }
783
784
785
786
787
788
789
790
791
792 if (rdev->mode_info.crtcs[pipe]) {
793
794
795
796 do {
797 count = radeon_get_vblank_counter(rdev, pipe);
798
799
800
801
802 stat = radeon_get_crtc_scanoutpos(
803 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
804 &vpos, &hpos, NULL, NULL,
805 &rdev->mode_info.crtcs[pipe]->base.hwmode);
806 } while (count != radeon_get_vblank_counter(rdev, pipe));
807
808 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
809 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
810 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
811 }
812 else {
813 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
814 pipe, vpos);
815
816
817
818
819
820 if (vpos >= 0)
821 count++;
822 }
823 }
824 else {
825
826 count = radeon_get_vblank_counter(rdev, pipe);
827 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
828 }
829
830 return count;
831}
832
833
834
835
836
837
838
839
840
841
842int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
843{
844 struct radeon_device *rdev = dev->dev_private;
845 unsigned long irqflags;
846 int r;
847
848 if (crtc < 0 || crtc >= rdev->num_crtc) {
849 DRM_ERROR("Invalid crtc %d\n", crtc);
850 return -EINVAL;
851 }
852
853 spin_lock_irqsave(&rdev->irq.lock, irqflags);
854 rdev->irq.crtc_vblank_int[crtc] = true;
855 r = radeon_irq_set(rdev);
856 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
857 return r;
858}
859
860
861
862
863
864
865
866
867
868void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
869{
870 struct radeon_device *rdev = dev->dev_private;
871 unsigned long irqflags;
872
873 if (crtc < 0 || crtc >= rdev->num_crtc) {
874 DRM_ERROR("Invalid crtc %d\n", crtc);
875 return;
876 }
877
878 spin_lock_irqsave(&rdev->irq.lock, irqflags);
879 rdev->irq.crtc_vblank_int[crtc] = false;
880 radeon_irq_set(rdev);
881 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
882}
883
884const struct drm_ioctl_desc radeon_ioctls_kms[] = {
885 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
886 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
887 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
888 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
889 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
890 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
891 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
892 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
893 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
894 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
895 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
896 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
897 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
898 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
899 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
900 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
901 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
902 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
903 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
904 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
905 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
906 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
907 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
908 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
909 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
910 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
911 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
912
913 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
914 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
915 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
916 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
917 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
918 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
919 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
920 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
921 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
922 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
923 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
924 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
925 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
926 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
927 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
928};
929int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
930