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6
7#include <drm/drm.h>
8#include <drm/drmP.h>
9#include <drm/drm_atomic.h>
10#include <drm/drm_atomic_uapi.h>
11#include <drm/drm_crtc.h>
12#include <drm/drm_flip_work.h>
13#include <drm/drm_gem_framebuffer_helper.h>
14#include <drm/drm_plane_helper.h>
15#include <drm/drm_probe_helper.h>
16#ifdef CONFIG_DRM_ANALOGIX_DP
17#include <drm/bridge/analogix_dp.h>
18#endif
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/iopoll.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/component.h>
29#include <linux/overflow.h>
30
31#include <linux/reset.h>
32#include <linux/delay.h>
33
34#include "rockchip_drm_drv.h"
35#include "rockchip_drm_gem.h"
36#include "rockchip_drm_fb.h"
37#include "rockchip_drm_psr.h"
38#include "rockchip_drm_vop.h"
39#include "rockchip_rgb.h"
40
41#define VOP_WIN_SET(vop, win, name, v) \
42 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
43#define VOP_SCL_SET(vop, win, name, v) \
44 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
45#define VOP_SCL_SET_EXT(vop, win, name, v) \
46 vop_reg_set(vop, &win->phy->scl->ext->name, \
47 win->base, ~0, v, #name)
48
49#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
50 do { \
51 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
52 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
53 } while (0)
54
55#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
56 do { \
57 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
58 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
59 } while (0)
60
61#define VOP_INTR_SET_MASK(vop, name, mask, v) \
62 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
63
64#define VOP_REG_SET(vop, group, name, v) \
65 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
66
67#define VOP_INTR_SET_TYPE(vop, name, type, v) \
68 do { \
69 int i, reg = 0, mask = 0; \
70 for (i = 0; i < vop->data->intr->nintrs; i++) { \
71 if (vop->data->intr->intrs[i] & type) { \
72 reg |= (v) << i; \
73 mask |= 1 << i; \
74 } \
75 } \
76 VOP_INTR_SET_MASK(vop, name, mask, reg); \
77 } while (0)
78#define VOP_INTR_GET_TYPE(vop, name, type) \
79 vop_get_intr_type(vop, &vop->data->intr->name, type)
80
81#define VOP_WIN_GET(vop, win, name) \
82 vop_read_reg(vop, win->offset, win->phy->name)
83
84#define VOP_WIN_HAS_REG(win, name) \
85 (!!(win->phy->name.mask))
86
87#define VOP_WIN_GET_YRGBADDR(vop, win) \
88 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
89
90#define VOP_WIN_TO_INDEX(vop_win) \
91 ((vop_win) - (vop_win)->vop->win)
92
93#define to_vop(x) container_of(x, struct vop, crtc)
94#define to_vop_win(x) container_of(x, struct vop_win, base)
95
96
97
98
99
100
101static const uint32_t bt601_yuv2rgb[] = {
102 0x4A8, 0x0, 0x662,
103 0x4A8, 0x1E6F, 0x1CBF,
104 0x4A8, 0x812, 0x0,
105 0x321168, 0x0877CF, 0x2EB127
106};
107
108enum vop_pending {
109 VOP_PENDING_FB_UNREF,
110};
111
112struct vop_win {
113 struct drm_plane base;
114 const struct vop_win_data *data;
115 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
116 struct vop *vop;
117};
118
119struct rockchip_rgb;
120struct vop {
121 struct drm_crtc crtc;
122 struct device *dev;
123 struct drm_device *drm_dev;
124 bool is_enabled;
125
126 struct completion dsp_hold_completion;
127
128
129 struct drm_pending_vblank_event *event;
130
131 struct drm_flip_work fb_unref_work;
132 unsigned long pending;
133
134 struct completion line_flag_completion;
135
136 const struct vop_data *data;
137
138 uint32_t *regsbak;
139 void __iomem *regs;
140
141
142 uint32_t len;
143
144
145 spinlock_t reg_lock;
146
147 spinlock_t irq_lock;
148
149 struct mutex vop_lock;
150
151 unsigned int irq;
152
153
154 struct clk *hclk;
155
156 struct clk *dclk;
157
158 struct clk *aclk;
159
160
161 struct reset_control *dclk_rst;
162
163
164 struct rockchip_rgb *rgb;
165
166 struct vop_win win[];
167};
168
169static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
170{
171 writel(v, vop->regs + offset);
172 vop->regsbak[offset >> 2] = v;
173}
174
175static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
176{
177 return readl(vop->regs + offset);
178}
179
180static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
181 const struct vop_reg *reg)
182{
183 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
184}
185
186static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
187 uint32_t _offset, uint32_t _mask, uint32_t v,
188 const char *reg_name)
189{
190 int offset, mask, shift;
191
192 if (!reg || !reg->mask) {
193 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
194 return;
195 }
196
197 offset = reg->offset + _offset;
198 mask = reg->mask & _mask;
199 shift = reg->shift;
200
201 if (reg->write_mask) {
202 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
203 } else {
204 uint32_t cached_val = vop->regsbak[offset >> 2];
205
206 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
207 vop->regsbak[offset >> 2] = v;
208 }
209
210 if (reg->relaxed)
211 writel_relaxed(v, vop->regs + offset);
212 else
213 writel(v, vop->regs + offset);
214}
215
216static inline uint32_t vop_get_intr_type(struct vop *vop,
217 const struct vop_reg *reg, int type)
218{
219 uint32_t i, ret = 0;
220 uint32_t regs = vop_read_reg(vop, 0, reg);
221
222 for (i = 0; i < vop->data->intr->nintrs; i++) {
223 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
224 ret |= vop->data->intr->intrs[i];
225 }
226
227 return ret;
228}
229
230static inline void vop_cfg_done(struct vop *vop)
231{
232 VOP_REG_SET(vop, common, cfg_done, 1);
233}
234
235static bool has_rb_swapped(uint32_t format)
236{
237 switch (format) {
238 case DRM_FORMAT_XBGR8888:
239 case DRM_FORMAT_ABGR8888:
240 case DRM_FORMAT_BGR888:
241 case DRM_FORMAT_BGR565:
242 return true;
243 default:
244 return false;
245 }
246}
247
248static enum vop_data_format vop_convert_format(uint32_t format)
249{
250 switch (format) {
251 case DRM_FORMAT_XRGB8888:
252 case DRM_FORMAT_ARGB8888:
253 case DRM_FORMAT_XBGR8888:
254 case DRM_FORMAT_ABGR8888:
255 return VOP_FMT_ARGB8888;
256 case DRM_FORMAT_RGB888:
257 case DRM_FORMAT_BGR888:
258 return VOP_FMT_RGB888;
259 case DRM_FORMAT_RGB565:
260 case DRM_FORMAT_BGR565:
261 return VOP_FMT_RGB565;
262 case DRM_FORMAT_NV12:
263 return VOP_FMT_YUV420SP;
264 case DRM_FORMAT_NV16:
265 return VOP_FMT_YUV422SP;
266 case DRM_FORMAT_NV24:
267 return VOP_FMT_YUV444SP;
268 default:
269 DRM_ERROR("unsupported format[%08x]\n", format);
270 return -EINVAL;
271 }
272}
273
274static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
275 uint32_t dst, bool is_horizontal,
276 int vsu_mode, int *vskiplines)
277{
278 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
279
280 if (vskiplines)
281 *vskiplines = 0;
282
283 if (is_horizontal) {
284 if (mode == SCALE_UP)
285 val = GET_SCL_FT_BIC(src, dst);
286 else if (mode == SCALE_DOWN)
287 val = GET_SCL_FT_BILI_DN(src, dst);
288 } else {
289 if (mode == SCALE_UP) {
290 if (vsu_mode == SCALE_UP_BIL)
291 val = GET_SCL_FT_BILI_UP(src, dst);
292 else
293 val = GET_SCL_FT_BIC(src, dst);
294 } else if (mode == SCALE_DOWN) {
295 if (vskiplines) {
296 *vskiplines = scl_get_vskiplines(src, dst);
297 val = scl_get_bili_dn_vskip(src, dst,
298 *vskiplines);
299 } else {
300 val = GET_SCL_FT_BILI_DN(src, dst);
301 }
302 }
303 }
304
305 return val;
306}
307
308static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
309 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
310 uint32_t dst_h, const struct drm_format_info *info)
311{
312 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
313 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
314 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
315 bool is_yuv = false;
316 uint16_t cbcr_src_w = src_w / info->hsub;
317 uint16_t cbcr_src_h = src_h / info->vsub;
318 uint16_t vsu_mode;
319 uint16_t lb_mode;
320 uint32_t val;
321 int vskiplines;
322
323 if (info->is_yuv)
324 is_yuv = true;
325
326 if (dst_w > 3840) {
327 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
328 return;
329 }
330
331 if (!win->phy->scl->ext) {
332 VOP_SCL_SET(vop, win, scale_yrgb_x,
333 scl_cal_scale2(src_w, dst_w));
334 VOP_SCL_SET(vop, win, scale_yrgb_y,
335 scl_cal_scale2(src_h, dst_h));
336 if (is_yuv) {
337 VOP_SCL_SET(vop, win, scale_cbcr_x,
338 scl_cal_scale2(cbcr_src_w, dst_w));
339 VOP_SCL_SET(vop, win, scale_cbcr_y,
340 scl_cal_scale2(cbcr_src_h, dst_h));
341 }
342 return;
343 }
344
345 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
346 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
347
348 if (is_yuv) {
349 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
350 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
351 if (cbcr_hor_scl_mode == SCALE_DOWN)
352 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
353 else
354 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
355 } else {
356 if (yrgb_hor_scl_mode == SCALE_DOWN)
357 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
358 else
359 lb_mode = scl_vop_cal_lb_mode(src_w, false);
360 }
361
362 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
363 if (lb_mode == LB_RGB_3840X2) {
364 if (yrgb_ver_scl_mode != SCALE_NONE) {
365 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
366 return;
367 }
368 if (cbcr_ver_scl_mode != SCALE_NONE) {
369 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
370 return;
371 }
372 vsu_mode = SCALE_UP_BIL;
373 } else if (lb_mode == LB_RGB_2560X4) {
374 vsu_mode = SCALE_UP_BIL;
375 } else {
376 vsu_mode = SCALE_UP_BIC;
377 }
378
379 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
380 true, 0, NULL);
381 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
382 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
383 false, vsu_mode, &vskiplines);
384 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
385
386 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
387 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
388
389 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
390 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
391 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
392 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
393 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
394 if (is_yuv) {
395 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
396 dst_w, true, 0, NULL);
397 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
398 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
399 dst_h, false, vsu_mode, &vskiplines);
400 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
401
402 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
403 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
404 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
405 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
406 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
407 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
408 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
409 }
410}
411
412static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
413{
414 unsigned long flags;
415
416 if (WARN_ON(!vop->is_enabled))
417 return;
418
419 spin_lock_irqsave(&vop->irq_lock, flags);
420
421 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
422 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
423
424 spin_unlock_irqrestore(&vop->irq_lock, flags);
425}
426
427static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
428{
429 unsigned long flags;
430
431 if (WARN_ON(!vop->is_enabled))
432 return;
433
434 spin_lock_irqsave(&vop->irq_lock, flags);
435
436 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
437
438 spin_unlock_irqrestore(&vop->irq_lock, flags);
439}
440
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461
462
463static bool vop_line_flag_irq_is_enabled(struct vop *vop)
464{
465 uint32_t line_flag_irq;
466 unsigned long flags;
467
468 spin_lock_irqsave(&vop->irq_lock, flags);
469
470 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
471
472 spin_unlock_irqrestore(&vop->irq_lock, flags);
473
474 return !!line_flag_irq;
475}
476
477static void vop_line_flag_irq_enable(struct vop *vop)
478{
479 unsigned long flags;
480
481 if (WARN_ON(!vop->is_enabled))
482 return;
483
484 spin_lock_irqsave(&vop->irq_lock, flags);
485
486 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
487 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
488
489 spin_unlock_irqrestore(&vop->irq_lock, flags);
490}
491
492static void vop_line_flag_irq_disable(struct vop *vop)
493{
494 unsigned long flags;
495
496 if (WARN_ON(!vop->is_enabled))
497 return;
498
499 spin_lock_irqsave(&vop->irq_lock, flags);
500
501 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
502
503 spin_unlock_irqrestore(&vop->irq_lock, flags);
504}
505
506static int vop_core_clks_enable(struct vop *vop)
507{
508 int ret;
509
510 ret = clk_enable(vop->hclk);
511 if (ret < 0)
512 return ret;
513
514 ret = clk_enable(vop->aclk);
515 if (ret < 0)
516 goto err_disable_hclk;
517
518 return 0;
519
520err_disable_hclk:
521 clk_disable(vop->hclk);
522 return ret;
523}
524
525static void vop_core_clks_disable(struct vop *vop)
526{
527 clk_disable(vop->aclk);
528 clk_disable(vop->hclk);
529}
530
531static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
532{
533 if (win->phy->scl && win->phy->scl->ext) {
534 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
535 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
536 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
537 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
538 }
539
540 VOP_WIN_SET(vop, win, enable, 0);
541}
542
543static int vop_enable(struct drm_crtc *crtc)
544{
545 struct vop *vop = to_vop(crtc);
546 int ret, i;
547
548 ret = pm_runtime_get_sync(vop->dev);
549 if (ret < 0) {
550 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
551 return ret;
552 }
553
554 ret = vop_core_clks_enable(vop);
555 if (WARN_ON(ret < 0))
556 goto err_put_pm_runtime;
557
558 ret = clk_enable(vop->dclk);
559 if (WARN_ON(ret < 0))
560 goto err_disable_core;
561
562
563
564
565
566
567
568 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
569 if (ret) {
570 DRM_DEV_ERROR(vop->dev,
571 "failed to attach dma mapping, %d\n", ret);
572 goto err_disable_dclk;
573 }
574
575 spin_lock(&vop->reg_lock);
576 for (i = 0; i < vop->len; i += 4)
577 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
578
579
580
581
582
583
584 for (i = 0; i < vop->data->win_size; i++) {
585 struct vop_win *vop_win = &vop->win[i];
586 const struct vop_win_data *win = vop_win->data;
587
588 vop_win_disable(vop, win);
589 }
590 spin_unlock(&vop->reg_lock);
591
592 vop_cfg_done(vop);
593
594
595
596
597 vop->is_enabled = true;
598
599 spin_lock(&vop->reg_lock);
600
601 VOP_REG_SET(vop, common, standby, 1);
602
603 spin_unlock(&vop->reg_lock);
604
605 drm_crtc_vblank_on(crtc);
606
607 return 0;
608
609err_disable_dclk:
610 clk_disable(vop->dclk);
611err_disable_core:
612 vop_core_clks_disable(vop);
613err_put_pm_runtime:
614 pm_runtime_put_sync(vop->dev);
615 return ret;
616}
617
618static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
619 struct drm_crtc_state *old_state)
620{
621 struct vop *vop = to_vop(crtc);
622
623 WARN_ON(vop->event);
624
625 mutex_lock(&vop->vop_lock);
626 drm_crtc_vblank_off(crtc);
627
628
629
630
631
632
633
634
635 reinit_completion(&vop->dsp_hold_completion);
636 vop_dsp_hold_valid_irq_enable(vop);
637
638 spin_lock(&vop->reg_lock);
639
640 VOP_REG_SET(vop, common, standby, 1);
641
642 spin_unlock(&vop->reg_lock);
643
644 wait_for_completion(&vop->dsp_hold_completion);
645
646 vop_dsp_hold_valid_irq_disable(vop);
647
648 vop->is_enabled = false;
649
650
651
652
653 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
654
655 clk_disable(vop->dclk);
656 vop_core_clks_disable(vop);
657 pm_runtime_put(vop->dev);
658 mutex_unlock(&vop->vop_lock);
659
660 if (crtc->state->event && !crtc->state->active) {
661 spin_lock_irq(&crtc->dev->event_lock);
662 drm_crtc_send_vblank_event(crtc, crtc->state->event);
663 spin_unlock_irq(&crtc->dev->event_lock);
664
665 crtc->state->event = NULL;
666 }
667}
668
669static void vop_plane_destroy(struct drm_plane *plane)
670{
671 drm_plane_cleanup(plane);
672}
673
674static int vop_plane_atomic_check(struct drm_plane *plane,
675 struct drm_plane_state *state)
676{
677 struct drm_crtc *crtc = state->crtc;
678 struct drm_crtc_state *crtc_state;
679 struct drm_framebuffer *fb = state->fb;
680 struct vop_win *vop_win = to_vop_win(plane);
681 const struct vop_win_data *win = vop_win->data;
682 int ret;
683 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
684 DRM_PLANE_HELPER_NO_SCALING;
685 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
686 DRM_PLANE_HELPER_NO_SCALING;
687
688 if (!crtc || !fb)
689 return 0;
690
691 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
692 if (WARN_ON(!crtc_state))
693 return -EINVAL;
694
695 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
696 min_scale, max_scale,
697 true, true);
698 if (ret)
699 return ret;
700
701 if (!state->visible)
702 return 0;
703
704 ret = vop_convert_format(fb->format->format);
705 if (ret < 0)
706 return ret;
707
708
709
710
711
712 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
713 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
714 return -EINVAL;
715 }
716
717 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
718 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
719 return -EINVAL;
720 }
721
722 return 0;
723}
724
725static void vop_plane_atomic_disable(struct drm_plane *plane,
726 struct drm_plane_state *old_state)
727{
728 struct vop_win *vop_win = to_vop_win(plane);
729 const struct vop_win_data *win = vop_win->data;
730 struct vop *vop = to_vop(old_state->crtc);
731
732 if (!old_state->crtc)
733 return;
734
735 spin_lock(&vop->reg_lock);
736
737 vop_win_disable(vop, win);
738
739 spin_unlock(&vop->reg_lock);
740}
741
742static void vop_plane_atomic_update(struct drm_plane *plane,
743 struct drm_plane_state *old_state)
744{
745 struct drm_plane_state *state = plane->state;
746 struct drm_crtc *crtc = state->crtc;
747 struct vop_win *vop_win = to_vop_win(plane);
748 const struct vop_win_data *win = vop_win->data;
749 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
750 struct vop *vop = to_vop(state->crtc);
751 struct drm_framebuffer *fb = state->fb;
752 unsigned int actual_w, actual_h;
753 unsigned int dsp_stx, dsp_sty;
754 uint32_t act_info, dsp_info, dsp_st;
755 struct drm_rect *src = &state->src;
756 struct drm_rect *dest = &state->dst;
757 struct drm_gem_object *obj, *uv_obj;
758 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
759 unsigned long offset;
760 dma_addr_t dma_addr;
761 uint32_t val;
762 bool rb_swap;
763 int win_index = VOP_WIN_TO_INDEX(vop_win);
764 int format;
765 int is_yuv = fb->format->is_yuv;
766 int i;
767
768
769
770
771 if (WARN_ON(!crtc))
772 return;
773
774 if (WARN_ON(!vop->is_enabled))
775 return;
776
777 if (!state->visible) {
778 vop_plane_atomic_disable(plane, old_state);
779 return;
780 }
781
782 obj = fb->obj[0];
783 rk_obj = to_rockchip_obj(obj);
784
785 actual_w = drm_rect_width(src) >> 16;
786 actual_h = drm_rect_height(src) >> 16;
787 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
788
789 dsp_info = (drm_rect_height(dest) - 1) << 16;
790 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
791
792 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
793 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
794 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
795
796 offset = (src->x1 >> 16) * fb->format->cpp[0];
797 offset += (src->y1 >> 16) * fb->pitches[0];
798 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
799
800
801
802
803
804 if (state->rotation & DRM_MODE_REFLECT_Y)
805 dma_addr += (actual_h - 1) * fb->pitches[0];
806
807 format = vop_convert_format(fb->format->format);
808
809 spin_lock(&vop->reg_lock);
810
811 VOP_WIN_SET(vop, win, format, format);
812 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
813 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
814 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
815 VOP_WIN_SET(vop, win, y_mir_en,
816 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
817 VOP_WIN_SET(vop, win, x_mir_en,
818 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
819
820 if (is_yuv) {
821 int hsub = fb->format->hsub;
822 int vsub = fb->format->vsub;
823 int bpp = fb->format->cpp[1];
824
825 uv_obj = fb->obj[1];
826 rk_uv_obj = to_rockchip_obj(uv_obj);
827
828 offset = (src->x1 >> 16) * bpp / hsub;
829 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
830
831 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
832 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
833 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
834
835 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
836 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
837 win_yuv2yuv,
838 y2r_coefficients[i],
839 bt601_yuv2rgb[i]);
840 }
841 }
842
843 if (win->phy->scl)
844 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
845 drm_rect_width(dest), drm_rect_height(dest),
846 fb->format);
847
848 VOP_WIN_SET(vop, win, act_info, act_info);
849 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
850 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
851
852 rb_swap = has_rb_swapped(fb->format->format);
853 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
854
855
856
857
858
859
860
861
862 if (fb->format->has_alpha && win_index > 0) {
863 VOP_WIN_SET(vop, win, dst_alpha_ctl,
864 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
865 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
866 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
867 SRC_BLEND_M0(ALPHA_PER_PIX) |
868 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
869 SRC_FACTOR_M0(ALPHA_ONE);
870 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
871 } else {
872 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
873 }
874
875 VOP_WIN_SET(vop, win, enable, 1);
876 spin_unlock(&vop->reg_lock);
877}
878
879static int vop_plane_atomic_async_check(struct drm_plane *plane,
880 struct drm_plane_state *state)
881{
882 struct vop_win *vop_win = to_vop_win(plane);
883 const struct vop_win_data *win = vop_win->data;
884 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
885 DRM_PLANE_HELPER_NO_SCALING;
886 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
887 DRM_PLANE_HELPER_NO_SCALING;
888 struct drm_crtc_state *crtc_state;
889
890 if (plane != state->crtc->cursor)
891 return -EINVAL;
892
893 if (!plane->state)
894 return -EINVAL;
895
896 if (!plane->state->fb)
897 return -EINVAL;
898
899 if (state->state)
900 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
901 state->crtc);
902 else
903 crtc_state = plane->crtc->state;
904
905 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
906 min_scale, max_scale,
907 true, true);
908}
909
910static void vop_plane_atomic_async_update(struct drm_plane *plane,
911 struct drm_plane_state *new_state)
912{
913 struct vop *vop = to_vop(plane->state->crtc);
914 struct drm_framebuffer *old_fb = plane->state->fb;
915
916 plane->state->crtc_x = new_state->crtc_x;
917 plane->state->crtc_y = new_state->crtc_y;
918 plane->state->crtc_h = new_state->crtc_h;
919 plane->state->crtc_w = new_state->crtc_w;
920 plane->state->src_x = new_state->src_x;
921 plane->state->src_y = new_state->src_y;
922 plane->state->src_h = new_state->src_h;
923 plane->state->src_w = new_state->src_w;
924 swap(plane->state->fb, new_state->fb);
925
926 if (vop->is_enabled) {
927 rockchip_drm_psr_inhibit_get_state(new_state->state);
928 vop_plane_atomic_update(plane, plane->state);
929 spin_lock(&vop->reg_lock);
930 vop_cfg_done(vop);
931 spin_unlock(&vop->reg_lock);
932 rockchip_drm_psr_inhibit_put_state(new_state->state);
933
934
935
936
937
938
939
940
941
942 if (old_fb && plane->state->fb != old_fb) {
943 drm_framebuffer_get(old_fb);
944 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
945 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
946 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
947 }
948 }
949}
950
951static const struct drm_plane_helper_funcs plane_helper_funcs = {
952 .atomic_check = vop_plane_atomic_check,
953 .atomic_update = vop_plane_atomic_update,
954 .atomic_disable = vop_plane_atomic_disable,
955 .atomic_async_check = vop_plane_atomic_async_check,
956 .atomic_async_update = vop_plane_atomic_async_update,
957 .prepare_fb = drm_gem_fb_prepare_fb,
958};
959
960static const struct drm_plane_funcs vop_plane_funcs = {
961 .update_plane = drm_atomic_helper_update_plane,
962 .disable_plane = drm_atomic_helper_disable_plane,
963 .destroy = vop_plane_destroy,
964 .reset = drm_atomic_helper_plane_reset,
965 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
966 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
967};
968
969static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
970{
971 struct vop *vop = to_vop(crtc);
972 unsigned long flags;
973
974 if (WARN_ON(!vop->is_enabled))
975 return -EPERM;
976
977 spin_lock_irqsave(&vop->irq_lock, flags);
978
979 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
980 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
981
982 spin_unlock_irqrestore(&vop->irq_lock, flags);
983
984 return 0;
985}
986
987static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
988{
989 struct vop *vop = to_vop(crtc);
990 unsigned long flags;
991
992 if (WARN_ON(!vop->is_enabled))
993 return;
994
995 spin_lock_irqsave(&vop->irq_lock, flags);
996
997 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
998
999 spin_unlock_irqrestore(&vop->irq_lock, flags);
1000}
1001
1002static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1003 const struct drm_display_mode *mode,
1004 struct drm_display_mode *adjusted_mode)
1005{
1006 struct vop *vop = to_vop(crtc);
1007
1008 adjusted_mode->clock =
1009 DIV_ROUND_UP(clk_round_rate(vop->dclk,
1010 adjusted_mode->clock * 1000), 1000);
1011
1012 return true;
1013}
1014
1015static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1016 struct drm_crtc_state *old_state)
1017{
1018 struct vop *vop = to_vop(crtc);
1019 const struct vop_data *vop_data = vop->data;
1020 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1021 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1022 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1023 u16 hdisplay = adjusted_mode->hdisplay;
1024 u16 htotal = adjusted_mode->htotal;
1025 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1026 u16 hact_end = hact_st + hdisplay;
1027 u16 vdisplay = adjusted_mode->vdisplay;
1028 u16 vtotal = adjusted_mode->vtotal;
1029 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1030 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1031 u16 vact_end = vact_st + vdisplay;
1032 uint32_t pin_pol, val;
1033 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1034 int ret;
1035
1036 mutex_lock(&vop->vop_lock);
1037
1038 WARN_ON(vop->event);
1039
1040 ret = vop_enable(crtc);
1041 if (ret) {
1042 mutex_unlock(&vop->vop_lock);
1043 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1044 return;
1045 }
1046
1047 pin_pol = BIT(DCLK_INVERT);
1048 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1049 BIT(HSYNC_POSITIVE) : 0;
1050 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1051 BIT(VSYNC_POSITIVE) : 0;
1052 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1053 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1054
1055 switch (s->output_type) {
1056 case DRM_MODE_CONNECTOR_LVDS:
1057 VOP_REG_SET(vop, output, rgb_en, 1);
1058 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1059 break;
1060 case DRM_MODE_CONNECTOR_eDP:
1061 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1062 VOP_REG_SET(vop, output, edp_en, 1);
1063 break;
1064 case DRM_MODE_CONNECTOR_HDMIA:
1065 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1066 VOP_REG_SET(vop, output, hdmi_en, 1);
1067 break;
1068 case DRM_MODE_CONNECTOR_DSI:
1069 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1070 VOP_REG_SET(vop, output, mipi_en, 1);
1071 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1072 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1073 break;
1074 case DRM_MODE_CONNECTOR_DisplayPort:
1075 pin_pol &= ~BIT(DCLK_INVERT);
1076 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1077 VOP_REG_SET(vop, output, dp_en, 1);
1078 break;
1079 default:
1080 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1081 s->output_type);
1082 }
1083
1084
1085
1086
1087 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1088 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1089 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1090
1091 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1092 VOP_REG_SET(vop, common, pre_dither_down, 1);
1093 else
1094 VOP_REG_SET(vop, common, pre_dither_down, 0);
1095
1096 if (dither_bpc == 6) {
1097 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1098 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1099 VOP_REG_SET(vop, common, dither_down_en, 1);
1100 } else {
1101 VOP_REG_SET(vop, common, dither_down_en, 0);
1102 }
1103
1104 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1105
1106 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1107 val = hact_st << 16;
1108 val |= hact_end;
1109 VOP_REG_SET(vop, modeset, hact_st_end, val);
1110 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1111
1112 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1113 val = vact_st << 16;
1114 val |= vact_end;
1115 VOP_REG_SET(vop, modeset, vact_st_end, val);
1116 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1117
1118 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1119
1120 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1121
1122 VOP_REG_SET(vop, common, standby, 0);
1123 mutex_unlock(&vop->vop_lock);
1124}
1125
1126static bool vop_fs_irq_is_pending(struct vop *vop)
1127{
1128 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1129}
1130
1131static void vop_wait_for_irq_handler(struct vop *vop)
1132{
1133 bool pending;
1134 int ret;
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1145 !pending, 0, 10 * 1000);
1146 if (ret)
1147 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1148
1149 synchronize_irq(vop->irq);
1150}
1151
1152static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1153 struct drm_crtc_state *old_crtc_state)
1154{
1155 struct drm_atomic_state *old_state = old_crtc_state->state;
1156 struct drm_plane_state *old_plane_state, *new_plane_state;
1157 struct vop *vop = to_vop(crtc);
1158 struct drm_plane *plane;
1159 int i;
1160
1161 if (WARN_ON(!vop->is_enabled))
1162 return;
1163
1164 spin_lock(&vop->reg_lock);
1165
1166 vop_cfg_done(vop);
1167
1168 spin_unlock(&vop->reg_lock);
1169
1170
1171
1172
1173
1174
1175 vop_wait_for_irq_handler(vop);
1176
1177 spin_lock_irq(&crtc->dev->event_lock);
1178 if (crtc->state->event) {
1179 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1180 WARN_ON(vop->event);
1181
1182 vop->event = crtc->state->event;
1183 crtc->state->event = NULL;
1184 }
1185 spin_unlock_irq(&crtc->dev->event_lock);
1186
1187 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1188 new_plane_state, i) {
1189 if (!old_plane_state->fb)
1190 continue;
1191
1192 if (old_plane_state->fb == new_plane_state->fb)
1193 continue;
1194
1195 drm_framebuffer_get(old_plane_state->fb);
1196 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1197 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1198 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1199 }
1200}
1201
1202static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1203 .mode_fixup = vop_crtc_mode_fixup,
1204 .atomic_flush = vop_crtc_atomic_flush,
1205 .atomic_enable = vop_crtc_atomic_enable,
1206 .atomic_disable = vop_crtc_atomic_disable,
1207};
1208
1209static void vop_crtc_destroy(struct drm_crtc *crtc)
1210{
1211 drm_crtc_cleanup(crtc);
1212}
1213
1214static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1215{
1216 struct rockchip_crtc_state *rockchip_state;
1217
1218 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1219 if (!rockchip_state)
1220 return NULL;
1221
1222 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1223 return &rockchip_state->base;
1224}
1225
1226static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1227 struct drm_crtc_state *state)
1228{
1229 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1230
1231 __drm_atomic_helper_crtc_destroy_state(&s->base);
1232 kfree(s);
1233}
1234
1235static void vop_crtc_reset(struct drm_crtc *crtc)
1236{
1237 struct rockchip_crtc_state *crtc_state =
1238 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1239
1240 if (crtc->state)
1241 vop_crtc_destroy_state(crtc, crtc->state);
1242
1243 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1244}
1245
1246#ifdef CONFIG_DRM_ANALOGIX_DP
1247static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1248{
1249 struct drm_connector *connector;
1250 struct drm_connector_list_iter conn_iter;
1251
1252 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1253 drm_for_each_connector_iter(connector, &conn_iter) {
1254 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1255 drm_connector_list_iter_end(&conn_iter);
1256 return connector;
1257 }
1258 }
1259 drm_connector_list_iter_end(&conn_iter);
1260
1261 return NULL;
1262}
1263
1264static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1265 const char *source_name)
1266{
1267 struct vop *vop = to_vop(crtc);
1268 struct drm_connector *connector;
1269 int ret;
1270
1271 connector = vop_get_edp_connector(vop);
1272 if (!connector)
1273 return -EINVAL;
1274
1275 if (source_name && strcmp(source_name, "auto") == 0)
1276 ret = analogix_dp_start_crc(connector);
1277 else if (!source_name)
1278 ret = analogix_dp_stop_crc(connector);
1279 else
1280 ret = -EINVAL;
1281
1282 return ret;
1283}
1284
1285static int
1286vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1287 size_t *values_cnt)
1288{
1289 if (source_name && strcmp(source_name, "auto") != 0)
1290 return -EINVAL;
1291
1292 *values_cnt = 3;
1293 return 0;
1294}
1295
1296#else
1297static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1298 const char *source_name)
1299{
1300 return -ENODEV;
1301}
1302
1303static int
1304vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1305 size_t *values_cnt)
1306{
1307 return -ENODEV;
1308}
1309#endif
1310
1311static const struct drm_crtc_funcs vop_crtc_funcs = {
1312 .set_config = drm_atomic_helper_set_config,
1313 .page_flip = drm_atomic_helper_page_flip,
1314 .destroy = vop_crtc_destroy,
1315 .reset = vop_crtc_reset,
1316 .atomic_duplicate_state = vop_crtc_duplicate_state,
1317 .atomic_destroy_state = vop_crtc_destroy_state,
1318 .enable_vblank = vop_crtc_enable_vblank,
1319 .disable_vblank = vop_crtc_disable_vblank,
1320 .set_crc_source = vop_crtc_set_crc_source,
1321 .verify_crc_source = vop_crtc_verify_crc_source,
1322};
1323
1324static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1325{
1326 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1327 struct drm_framebuffer *fb = val;
1328
1329 drm_crtc_vblank_put(&vop->crtc);
1330 drm_framebuffer_put(fb);
1331}
1332
1333static void vop_handle_vblank(struct vop *vop)
1334{
1335 struct drm_device *drm = vop->drm_dev;
1336 struct drm_crtc *crtc = &vop->crtc;
1337
1338 spin_lock(&drm->event_lock);
1339 if (vop->event) {
1340 drm_crtc_send_vblank_event(crtc, vop->event);
1341 drm_crtc_vblank_put(crtc);
1342 vop->event = NULL;
1343 }
1344 spin_unlock(&drm->event_lock);
1345
1346 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1347 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1348}
1349
1350static irqreturn_t vop_isr(int irq, void *data)
1351{
1352 struct vop *vop = data;
1353 struct drm_crtc *crtc = &vop->crtc;
1354 uint32_t active_irqs;
1355 int ret = IRQ_NONE;
1356
1357
1358
1359
1360
1361 if (!pm_runtime_get_if_in_use(vop->dev))
1362 return IRQ_NONE;
1363
1364 if (vop_core_clks_enable(vop)) {
1365 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1366 goto out;
1367 }
1368
1369
1370
1371
1372
1373 spin_lock(&vop->irq_lock);
1374
1375 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1376
1377 if (active_irqs)
1378 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1379
1380 spin_unlock(&vop->irq_lock);
1381
1382
1383 if (!active_irqs)
1384 goto out_disable;
1385
1386 if (active_irqs & DSP_HOLD_VALID_INTR) {
1387 complete(&vop->dsp_hold_completion);
1388 active_irqs &= ~DSP_HOLD_VALID_INTR;
1389 ret = IRQ_HANDLED;
1390 }
1391
1392 if (active_irqs & LINE_FLAG_INTR) {
1393 complete(&vop->line_flag_completion);
1394 active_irqs &= ~LINE_FLAG_INTR;
1395 ret = IRQ_HANDLED;
1396 }
1397
1398 if (active_irqs & FS_INTR) {
1399 drm_crtc_handle_vblank(crtc);
1400 vop_handle_vblank(vop);
1401 active_irqs &= ~FS_INTR;
1402 ret = IRQ_HANDLED;
1403 }
1404
1405
1406 if (active_irqs)
1407 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1408 active_irqs);
1409
1410out_disable:
1411 vop_core_clks_disable(vop);
1412out:
1413 pm_runtime_put(vop->dev);
1414 return ret;
1415}
1416
1417static void vop_plane_add_properties(struct drm_plane *plane,
1418 const struct vop_win_data *win_data)
1419{
1420 unsigned int flags = 0;
1421
1422 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1423 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1424 if (flags)
1425 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1426 DRM_MODE_ROTATE_0 | flags);
1427}
1428
1429static int vop_create_crtc(struct vop *vop)
1430{
1431 const struct vop_data *vop_data = vop->data;
1432 struct device *dev = vop->dev;
1433 struct drm_device *drm_dev = vop->drm_dev;
1434 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1435 struct drm_crtc *crtc = &vop->crtc;
1436 struct device_node *port;
1437 int ret;
1438 int i;
1439
1440
1441
1442
1443
1444
1445 for (i = 0; i < vop_data->win_size; i++) {
1446 struct vop_win *vop_win = &vop->win[i];
1447 const struct vop_win_data *win_data = vop_win->data;
1448
1449 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1450 win_data->type != DRM_PLANE_TYPE_CURSOR)
1451 continue;
1452
1453 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1454 0, &vop_plane_funcs,
1455 win_data->phy->data_formats,
1456 win_data->phy->nformats,
1457 NULL, win_data->type, NULL);
1458 if (ret) {
1459 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1460 ret);
1461 goto err_cleanup_planes;
1462 }
1463
1464 plane = &vop_win->base;
1465 drm_plane_helper_add(plane, &plane_helper_funcs);
1466 vop_plane_add_properties(plane, win_data);
1467 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1468 primary = plane;
1469 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1470 cursor = plane;
1471 }
1472
1473 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1474 &vop_crtc_funcs, NULL);
1475 if (ret)
1476 goto err_cleanup_planes;
1477
1478 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1479
1480
1481
1482
1483
1484 for (i = 0; i < vop_data->win_size; i++) {
1485 struct vop_win *vop_win = &vop->win[i];
1486 const struct vop_win_data *win_data = vop_win->data;
1487 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1488
1489 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1490 continue;
1491
1492 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1493 possible_crtcs,
1494 &vop_plane_funcs,
1495 win_data->phy->data_formats,
1496 win_data->phy->nformats,
1497 NULL, win_data->type, NULL);
1498 if (ret) {
1499 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1500 ret);
1501 goto err_cleanup_crtc;
1502 }
1503 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1504 vop_plane_add_properties(&vop_win->base, win_data);
1505 }
1506
1507 port = of_get_child_by_name(dev->of_node, "port");
1508 if (!port) {
1509 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1510 dev->of_node);
1511 ret = -ENOENT;
1512 goto err_cleanup_crtc;
1513 }
1514
1515 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1516 vop_fb_unref_worker);
1517
1518 init_completion(&vop->dsp_hold_completion);
1519 init_completion(&vop->line_flag_completion);
1520 crtc->port = port;
1521
1522 return 0;
1523
1524err_cleanup_crtc:
1525 drm_crtc_cleanup(crtc);
1526err_cleanup_planes:
1527 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1528 head)
1529 drm_plane_cleanup(plane);
1530 return ret;
1531}
1532
1533static void vop_destroy_crtc(struct vop *vop)
1534{
1535 struct drm_crtc *crtc = &vop->crtc;
1536 struct drm_device *drm_dev = vop->drm_dev;
1537 struct drm_plane *plane, *tmp;
1538
1539 of_node_put(crtc->port);
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1550 head)
1551 vop_plane_destroy(plane);
1552
1553
1554
1555
1556
1557 drm_crtc_cleanup(crtc);
1558 drm_flip_work_cleanup(&vop->fb_unref_work);
1559}
1560
1561static int vop_initial(struct vop *vop)
1562{
1563 const struct vop_data *vop_data = vop->data;
1564 struct reset_control *ahb_rst;
1565 int i, ret;
1566
1567 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1568 if (IS_ERR(vop->hclk)) {
1569 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1570 return PTR_ERR(vop->hclk);
1571 }
1572 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1573 if (IS_ERR(vop->aclk)) {
1574 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1575 return PTR_ERR(vop->aclk);
1576 }
1577 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1578 if (IS_ERR(vop->dclk)) {
1579 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1580 return PTR_ERR(vop->dclk);
1581 }
1582
1583 ret = pm_runtime_get_sync(vop->dev);
1584 if (ret < 0) {
1585 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1586 return ret;
1587 }
1588
1589 ret = clk_prepare(vop->dclk);
1590 if (ret < 0) {
1591 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1592 goto err_put_pm_runtime;
1593 }
1594
1595
1596 ret = clk_prepare_enable(vop->hclk);
1597 if (ret < 0) {
1598 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1599 goto err_unprepare_dclk;
1600 }
1601
1602 ret = clk_prepare_enable(vop->aclk);
1603 if (ret < 0) {
1604 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1605 goto err_disable_hclk;
1606 }
1607
1608
1609
1610
1611 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1612 if (IS_ERR(ahb_rst)) {
1613 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1614 ret = PTR_ERR(ahb_rst);
1615 goto err_disable_aclk;
1616 }
1617 reset_control_assert(ahb_rst);
1618 usleep_range(10, 20);
1619 reset_control_deassert(ahb_rst);
1620
1621 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1622 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1623
1624 for (i = 0; i < vop->len; i += sizeof(u32))
1625 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1626
1627 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1628 VOP_REG_SET(vop, common, dsp_blank, 0);
1629
1630 for (i = 0; i < vop_data->win_size; i++) {
1631 const struct vop_win_data *win = &vop_data->win[i];
1632 int channel = i * 2 + 1;
1633
1634 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1635 vop_win_disable(vop, win);
1636 VOP_WIN_SET(vop, win, gate, 1);
1637 }
1638
1639 vop_cfg_done(vop);
1640
1641
1642
1643
1644 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1645 if (IS_ERR(vop->dclk_rst)) {
1646 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1647 ret = PTR_ERR(vop->dclk_rst);
1648 goto err_disable_aclk;
1649 }
1650 reset_control_assert(vop->dclk_rst);
1651 usleep_range(10, 20);
1652 reset_control_deassert(vop->dclk_rst);
1653
1654 clk_disable(vop->hclk);
1655 clk_disable(vop->aclk);
1656
1657 vop->is_enabled = false;
1658
1659 pm_runtime_put_sync(vop->dev);
1660
1661 return 0;
1662
1663err_disable_aclk:
1664 clk_disable_unprepare(vop->aclk);
1665err_disable_hclk:
1666 clk_disable_unprepare(vop->hclk);
1667err_unprepare_dclk:
1668 clk_unprepare(vop->dclk);
1669err_put_pm_runtime:
1670 pm_runtime_put_sync(vop->dev);
1671 return ret;
1672}
1673
1674
1675
1676
1677static void vop_win_init(struct vop *vop)
1678{
1679 const struct vop_data *vop_data = vop->data;
1680 unsigned int i;
1681
1682 for (i = 0; i < vop_data->win_size; i++) {
1683 struct vop_win *vop_win = &vop->win[i];
1684 const struct vop_win_data *win_data = &vop_data->win[i];
1685
1686 vop_win->data = win_data;
1687 vop_win->vop = vop;
1688
1689 if (vop_data->win_yuv2yuv)
1690 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
1691 }
1692}
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1705{
1706 struct vop *vop = to_vop(crtc);
1707 unsigned long jiffies_left;
1708 int ret = 0;
1709
1710 if (!crtc || !vop->is_enabled)
1711 return -ENODEV;
1712
1713 mutex_lock(&vop->vop_lock);
1714 if (mstimeout <= 0) {
1715 ret = -EINVAL;
1716 goto out;
1717 }
1718
1719 if (vop_line_flag_irq_is_enabled(vop)) {
1720 ret = -EBUSY;
1721 goto out;
1722 }
1723
1724 reinit_completion(&vop->line_flag_completion);
1725 vop_line_flag_irq_enable(vop);
1726
1727 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1728 msecs_to_jiffies(mstimeout));
1729 vop_line_flag_irq_disable(vop);
1730
1731 if (jiffies_left == 0) {
1732 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1733 ret = -ETIMEDOUT;
1734 goto out;
1735 }
1736
1737out:
1738 mutex_unlock(&vop->vop_lock);
1739 return ret;
1740}
1741EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1742
1743static int vop_bind(struct device *dev, struct device *master, void *data)
1744{
1745 struct platform_device *pdev = to_platform_device(dev);
1746 const struct vop_data *vop_data;
1747 struct drm_device *drm_dev = data;
1748 struct vop *vop;
1749 struct resource *res;
1750 int ret, irq;
1751
1752 vop_data = of_device_get_match_data(dev);
1753 if (!vop_data)
1754 return -ENODEV;
1755
1756
1757 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1758 GFP_KERNEL);
1759 if (!vop)
1760 return -ENOMEM;
1761
1762 vop->dev = dev;
1763 vop->data = vop_data;
1764 vop->drm_dev = drm_dev;
1765 dev_set_drvdata(dev, vop);
1766
1767 vop_win_init(vop);
1768
1769 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1770 vop->len = resource_size(res);
1771 vop->regs = devm_ioremap_resource(dev, res);
1772 if (IS_ERR(vop->regs))
1773 return PTR_ERR(vop->regs);
1774
1775 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1776 if (!vop->regsbak)
1777 return -ENOMEM;
1778
1779 irq = platform_get_irq(pdev, 0);
1780 if (irq < 0) {
1781 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1782 return irq;
1783 }
1784 vop->irq = (unsigned int)irq;
1785
1786 spin_lock_init(&vop->reg_lock);
1787 spin_lock_init(&vop->irq_lock);
1788 mutex_init(&vop->vop_lock);
1789
1790 ret = vop_create_crtc(vop);
1791 if (ret)
1792 return ret;
1793
1794 pm_runtime_enable(&pdev->dev);
1795
1796 ret = vop_initial(vop);
1797 if (ret < 0) {
1798 DRM_DEV_ERROR(&pdev->dev,
1799 "cannot initial vop dev - err %d\n", ret);
1800 goto err_disable_pm_runtime;
1801 }
1802
1803 ret = devm_request_irq(dev, vop->irq, vop_isr,
1804 IRQF_SHARED, dev_name(dev), vop);
1805 if (ret)
1806 goto err_disable_pm_runtime;
1807
1808 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1809 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1810 if (IS_ERR(vop->rgb)) {
1811 ret = PTR_ERR(vop->rgb);
1812 goto err_disable_pm_runtime;
1813 }
1814 }
1815
1816 return 0;
1817
1818err_disable_pm_runtime:
1819 pm_runtime_disable(&pdev->dev);
1820 vop_destroy_crtc(vop);
1821 return ret;
1822}
1823
1824static void vop_unbind(struct device *dev, struct device *master, void *data)
1825{
1826 struct vop *vop = dev_get_drvdata(dev);
1827
1828 if (vop->rgb)
1829 rockchip_rgb_fini(vop->rgb);
1830
1831 pm_runtime_disable(dev);
1832 vop_destroy_crtc(vop);
1833
1834 clk_unprepare(vop->aclk);
1835 clk_unprepare(vop->hclk);
1836 clk_unprepare(vop->dclk);
1837}
1838
1839const struct component_ops vop_component_ops = {
1840 .bind = vop_bind,
1841 .unbind = vop_unbind,
1842};
1843EXPORT_SYMBOL_GPL(vop_component_ops);
1844