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9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/crc-ccitt.h>
12#include <linux/of_address.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
16#include <linux/slab.h>
17
18#include <linux/phy/phy.h>
19#include <linux/phy/phy-mipi-dphy.h>
20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_mipi_dsi.h>
24#include <drm/drm_panel.h>
25#include <drm/drm_probe_helper.h>
26
27#include "sun4i_crtc.h"
28#include "sun4i_drv.h"
29#include "sun4i_tcon.h"
30#include "sun6i_mipi_dsi.h"
31
32#include <video/mipi_display.h>
33
34#define SUN6I_DSI_CTL_REG 0x000
35#define SUN6I_DSI_CTL_EN BIT(0)
36
37#define SUN6I_DSI_BASIC_CTL_REG 0x00c
38#define SUN6I_DSI_BASIC_CTL_TRAIL_INV(n) (((n) & 0xf) << 4)
39#define SUN6I_DSI_BASIC_CTL_TRAIL_FILL BIT(3)
40#define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2)
41#define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1)
42#define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0)
43
44#define SUN6I_DSI_BASIC_CTL0_REG 0x010
45#define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
46#define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17)
47#define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16)
48#define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0)
49
50#define SUN6I_DSI_BASIC_CTL1_REG 0x014
51#define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4)
52#define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2)
53#define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1)
54#define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0)
55
56#define SUN6I_DSI_BASIC_SIZE0_REG 0x018
57#define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16)
58#define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff)
59
60#define SUN6I_DSI_BASIC_SIZE1_REG 0x01c
61#define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16)
62#define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff)
63
64#define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04)
65#define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28)
66#define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24)
67#define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20)
68#define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4)
69#define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf)
70
71#define SUN6I_DSI_INST_LOOP_SEL_REG 0x040
72
73#define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10)
74#define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16)
75#define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff)
76
77#define SUN6I_DSI_INST_JUMP_SEL_REG 0x048
78
79#define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04)
80#define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20)
81#define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16)
82#define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff)
83
84#define SUN6I_DSI_TRANS_START_REG 0x060
85
86#define SUN6I_DSI_TRANS_ZERO_REG 0x078
87
88#define SUN6I_DSI_TCON_DRQ_REG 0x07c
89#define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28)
90#define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff)
91
92#define SUN6I_DSI_PIXEL_CTL0_REG 0x080
93#define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16)
94#define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf)
95
96#define SUN6I_DSI_PIXEL_CTL1_REG 0x084
97
98#define SUN6I_DSI_PIXEL_PH_REG 0x090
99#define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24)
100#define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8)
101#define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6)
102#define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f)
103
104#define SUN6I_DSI_PIXEL_PF0_REG 0x098
105#define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff)
106
107#define SUN6I_DSI_PIXEL_PF1_REG 0x09c
108#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16)
109#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff)
110
111#define SUN6I_DSI_SYNC_HSS_REG 0x0b0
112
113#define SUN6I_DSI_SYNC_HSE_REG 0x0b4
114
115#define SUN6I_DSI_SYNC_VSS_REG 0x0b8
116
117#define SUN6I_DSI_SYNC_VSE_REG 0x0bc
118
119#define SUN6I_DSI_BLK_HSA0_REG 0x0c0
120
121#define SUN6I_DSI_BLK_HSA1_REG 0x0c4
122#define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16)
123#define SUN6I_DSI_BLK_PD(n) ((n) & 0xff)
124
125#define SUN6I_DSI_BLK_HBP0_REG 0x0c8
126
127#define SUN6I_DSI_BLK_HBP1_REG 0x0cc
128
129#define SUN6I_DSI_BLK_HFP0_REG 0x0d0
130
131#define SUN6I_DSI_BLK_HFP1_REG 0x0d4
132
133#define SUN6I_DSI_BLK_HBLK0_REG 0x0e0
134
135#define SUN6I_DSI_BLK_HBLK1_REG 0x0e4
136
137#define SUN6I_DSI_BLK_VBLK0_REG 0x0e8
138
139#define SUN6I_DSI_BLK_VBLK1_REG 0x0ec
140
141#define SUN6I_DSI_BURST_LINE_REG 0x0f0
142#define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16)
143#define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff)
144
145#define SUN6I_DSI_BURST_DRQ_REG 0x0f4
146#define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16)
147#define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff)
148
149#define SUN6I_DSI_CMD_CTL_REG 0x200
150#define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26)
151#define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25)
152#define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9)
153
154#define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04)
155
156#define SUN6I_DSI_DEBUG_DATA_REG 0x2f8
157
158#define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04)
159
160#define SUN6I_DSI_SYNC_POINT 40
161
162enum sun6i_dsi_start_inst {
163 DSI_START_LPRX,
164 DSI_START_LPTX,
165 DSI_START_HSC,
166 DSI_START_HSD,
167};
168
169enum sun6i_dsi_inst_id {
170 DSI_INST_ID_LP11 = 0,
171 DSI_INST_ID_TBA,
172 DSI_INST_ID_HSC,
173 DSI_INST_ID_HSD,
174 DSI_INST_ID_LPDT,
175 DSI_INST_ID_HSCEXIT,
176 DSI_INST_ID_NOP,
177 DSI_INST_ID_DLY,
178 DSI_INST_ID_END = 15,
179};
180
181enum sun6i_dsi_inst_mode {
182 DSI_INST_MODE_STOP = 0,
183 DSI_INST_MODE_TBA,
184 DSI_INST_MODE_HS,
185 DSI_INST_MODE_ESCAPE,
186 DSI_INST_MODE_HSCEXIT,
187 DSI_INST_MODE_NOP,
188};
189
190enum sun6i_dsi_inst_escape {
191 DSI_INST_ESCA_LPDT = 0,
192 DSI_INST_ESCA_ULPS,
193 DSI_INST_ESCA_UN1,
194 DSI_INST_ESCA_UN2,
195 DSI_INST_ESCA_RESET,
196 DSI_INST_ESCA_UN3,
197 DSI_INST_ESCA_UN4,
198 DSI_INST_ESCA_UN5,
199};
200
201enum sun6i_dsi_inst_packet {
202 DSI_INST_PACK_PIXEL = 0,
203 DSI_INST_PACK_COMMAND,
204};
205
206static const u32 sun6i_dsi_ecc_array[] = {
207 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
208 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
209 BIT(23)),
210 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
211 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
212 BIT(23)),
213 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
214 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
215 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
216 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
217 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
218 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
219 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
220 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
221 BIT(23)),
222};
223
224static u32 sun6i_dsi_ecc_compute(unsigned int data)
225{
226 int i;
227 u8 ecc = 0;
228
229 for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
230 u32 field = sun6i_dsi_ecc_array[i];
231 bool init = false;
232 u8 val = 0;
233 int j;
234
235 for (j = 0; j < 24; j++) {
236 if (!(BIT(j) & field))
237 continue;
238
239 if (!init) {
240 val = (BIT(j) & data) ? 1 : 0;
241 init = true;
242 } else {
243 val ^= (BIT(j) & data) ? 1 : 0;
244 }
245 }
246
247 ecc |= val << i;
248 }
249
250 return ecc;
251}
252
253static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
254{
255 return crc_ccitt(0xffff, buffer, len);
256}
257
258static u16 sun6i_dsi_crc_repeat(u8 pd, u8 *buffer, size_t len)
259{
260 memset(buffer, pd, len);
261
262 return sun6i_dsi_crc_compute(buffer, len);
263}
264
265static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
266{
267 u32 val = dt & 0x3f;
268
269 val |= (vc & 3) << 6;
270 val |= (d0 & 0xff) << 8;
271 val |= (d1 & 0xff) << 16;
272 val |= sun6i_dsi_ecc_compute(val) << 24;
273
274 return val;
275}
276
277static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
278{
279 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
280 wc & 0xff, wc >> 8);
281}
282
283static u32 sun6i_dsi_build_blk1_pkt(u16 pd, u8 *buffer, size_t len)
284{
285 u32 val = SUN6I_DSI_BLK_PD(pd);
286
287 return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len));
288}
289
290static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
291{
292 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
293 SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
294}
295
296static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
297{
298 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
299 SUN6I_DSI_BASIC_CTL0_INST_ST,
300 SUN6I_DSI_BASIC_CTL0_INST_ST);
301}
302
303static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
304{
305 u32 val;
306
307 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
308 val,
309 !(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
310 100, 5000);
311}
312
313static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
314 enum sun6i_dsi_inst_id id,
315 enum sun6i_dsi_inst_mode mode,
316 bool clock, u8 data,
317 enum sun6i_dsi_inst_packet packet,
318 enum sun6i_dsi_inst_escape escape)
319{
320 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
321 SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
322 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
323 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
324 (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
325 SUN6I_DSI_INST_FUNC_LANE_DEN(data));
326}
327
328static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
329 struct mipi_dsi_device *device)
330{
331 u8 lanes_mask = GENMASK(device->lanes - 1, 0);
332
333 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
334 true, lanes_mask, 0, 0);
335
336 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
337 false, 1, 0, 0);
338
339 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
340 true, 0, DSI_INST_PACK_PIXEL, 0);
341
342 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
343 false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
344
345 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
346 false, 1, DSI_INST_PACK_COMMAND,
347 DSI_INST_ESCA_LPDT);
348
349 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
350 true, 0, 0, 0);
351
352 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
353 false, lanes_mask, 0, 0);
354
355 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
356 true, lanes_mask, 0, 0);
357
358 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
359 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
360 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
361 SUN6I_DSI_INST_JUMP_CFG_NUM(1));
362};
363
364static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
365 struct drm_display_mode *mode)
366{
367 u16 start = clamp(mode->vtotal - mode->vdisplay - 10, 8, 100);
368 u16 delay = mode->vtotal - (mode->vsync_end - mode->vdisplay) + start;
369
370 if (delay > mode->vtotal)
371 delay = delay % mode->vtotal;
372
373 return max_t(u16, delay, 1);
374}
375
376static u16 sun6i_dsi_get_line_num(struct sun6i_dsi *dsi,
377 struct drm_display_mode *mode)
378{
379 struct mipi_dsi_device *device = dsi->device;
380 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
381
382 return mode->htotal * Bpp / device->lanes;
383}
384
385static u16 sun6i_dsi_get_drq_edge0(struct sun6i_dsi *dsi,
386 struct drm_display_mode *mode,
387 u16 line_num, u16 edge1)
388{
389 u16 edge0 = edge1;
390
391 edge0 += (mode->hdisplay + 40) * SUN6I_DSI_TCON_DIV / 8;
392
393 if (edge0 > line_num)
394 return edge0 - line_num;
395
396 return 1;
397}
398
399static u16 sun6i_dsi_get_drq_edge1(struct sun6i_dsi *dsi,
400 struct drm_display_mode *mode,
401 u16 line_num)
402{
403 struct mipi_dsi_device *device = dsi->device;
404 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
405 unsigned int hbp = mode->htotal - mode->hsync_end;
406 u16 edge1;
407
408 edge1 = SUN6I_DSI_SYNC_POINT;
409 edge1 += (mode->hdisplay + hbp + 20) * Bpp / device->lanes;
410
411 if (edge1 > line_num)
412 return line_num;
413
414 return edge1;
415}
416
417static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
418 struct drm_display_mode *mode)
419{
420 struct mipi_dsi_device *device = dsi->device;
421 u32 val = 0;
422
423 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
424 u16 line_num = sun6i_dsi_get_line_num(dsi, mode);
425 u16 edge0, edge1;
426
427 edge1 = sun6i_dsi_get_drq_edge1(dsi, mode, line_num);
428 edge0 = sun6i_dsi_get_drq_edge0(dsi, mode, line_num, edge1);
429
430 regmap_write(dsi->regs, SUN6I_DSI_BURST_DRQ_REG,
431 SUN6I_DSI_BURST_DRQ_EDGE0(edge0) |
432 SUN6I_DSI_BURST_DRQ_EDGE1(edge1));
433
434 regmap_write(dsi->regs, SUN6I_DSI_BURST_LINE_REG,
435 SUN6I_DSI_BURST_LINE_NUM(line_num) |
436 SUN6I_DSI_BURST_LINE_SYNC_POINT(SUN6I_DSI_SYNC_POINT));
437
438 val = SUN6I_DSI_TCON_DRQ_ENABLE_MODE;
439 } else if ((mode->hsync_end - mode->hdisplay) > 20) {
440
441 u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
442
443 drq *= mipi_dsi_pixel_format_to_bpp(device->format);
444 drq /= 32;
445
446 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
447 SUN6I_DSI_TCON_DRQ_SET(drq));
448 }
449
450 regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
451}
452
453static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
454 struct drm_display_mode *mode)
455{
456 struct mipi_dsi_device *device = dsi->device;
457 u16 delay = 50 - 1;
458
459 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
460 u32 hsync_porch = (mode->htotal - mode->hdisplay) * 150;
461
462 delay = (hsync_porch / ((mode->clock / 1000) * 8));
463 delay -= 50;
464 }
465
466 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_SEL_REG,
467 2 << (4 * DSI_INST_ID_LP11) |
468 3 << (4 * DSI_INST_ID_DLY));
469
470 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
471 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
472 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
473 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
474 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
475 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
476}
477
478static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
479 struct drm_display_mode *mode)
480{
481 struct mipi_dsi_device *device = dsi->device;
482 u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
483 u8 dt, fmt;
484 u16 wc;
485
486
487
488
489
490 switch (device->format) {
491 case MIPI_DSI_FMT_RGB888:
492 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
493 fmt = 8;
494 break;
495 case MIPI_DSI_FMT_RGB666:
496 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
497 fmt = 9;
498 break;
499 case MIPI_DSI_FMT_RGB666_PACKED:
500 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
501 fmt = 10;
502 break;
503 case MIPI_DSI_FMT_RGB565:
504 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
505 fmt = 11;
506 break;
507 default:
508 return;
509 }
510 val |= SUN6I_DSI_PIXEL_PH_DT(dt);
511
512 wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
513 val |= SUN6I_DSI_PIXEL_PH_WC(wc);
514 val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
515
516 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
517
518 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
519 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
520
521 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
522 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
523 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
524
525 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
526 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
527 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
528}
529
530static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
531 struct drm_display_mode *mode)
532{
533 struct mipi_dsi_device *device = dsi->device;
534 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
535 u16 hbp = 0, hfp = 0, hsa = 0, hblk = 0, vblk = 0;
536 u32 basic_ctl = 0;
537 size_t bytes;
538 u8 *buffer;
539
540
541
542 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
543 hblk = mode->hdisplay * Bpp;
544 basic_ctl = SUN6I_DSI_BASIC_CTL_VIDEO_BURST |
545 SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS |
546 SUN6I_DSI_BASIC_CTL_HBP_DIS;
547
548 if (device->lanes == 4)
549 basic_ctl |= SUN6I_DSI_BASIC_CTL_TRAIL_FILL |
550 SUN6I_DSI_BASIC_CTL_TRAIL_INV(0xc);
551 } else {
552
553
554
555
556
557#define HSA_PACKET_OVERHEAD 10
558 hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
559 (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
560
561
562
563
564
565
566#define HBP_PACKET_OVERHEAD 6
567 hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
568 (mode->htotal - mode->hsync_end) * Bpp - HBP_PACKET_OVERHEAD);
569
570
571
572
573
574
575#define HFP_PACKET_OVERHEAD 6
576 hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
577 (mode->hsync_start - mode->hdisplay) * Bpp - HFP_PACKET_OVERHEAD);
578
579
580
581
582
583
584#define HBLK_PACKET_OVERHEAD 10
585 hblk = max((unsigned int)HBLK_PACKET_OVERHEAD,
586 (mode->htotal - (mode->hsync_end - mode->hsync_start)) * Bpp -
587 HBLK_PACKET_OVERHEAD);
588
589
590
591
592
593
594
595 vblk = 0;
596 }
597
598
599 bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
600 buffer = kmalloc(bytes, GFP_KERNEL);
601 if (WARN_ON(!buffer))
602 return;
603
604 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, basic_ctl);
605
606 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
607 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
608 device->channel,
609 0, 0));
610
611 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
612 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
613 device->channel,
614 0, 0));
615
616 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
617 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
618 device->channel,
619 0, 0));
620
621 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
622 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
623 device->channel,
624 0, 0));
625
626 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
627 SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
628 mode->vsync_start) |
629 SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal -
630 mode->vsync_end));
631
632 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
633 SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
634 SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
635
636
637 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
638 sun6i_dsi_build_blk0_pkt(device->channel, hsa));
639 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
640 sun6i_dsi_build_blk1_pkt(0, buffer, hsa));
641
642
643 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
644 sun6i_dsi_build_blk0_pkt(device->channel, hbp));
645 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
646 sun6i_dsi_build_blk1_pkt(0, buffer, hbp));
647
648
649 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
650 sun6i_dsi_build_blk0_pkt(device->channel, hfp));
651 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
652 sun6i_dsi_build_blk1_pkt(0, buffer, hfp));
653
654
655 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
656 sun6i_dsi_build_blk0_pkt(device->channel, hblk));
657 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
658 sun6i_dsi_build_blk1_pkt(0, buffer, hblk));
659
660
661 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
662 sun6i_dsi_build_blk0_pkt(device->channel, vblk));
663 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
664 sun6i_dsi_build_blk1_pkt(0, buffer, vblk));
665
666 kfree(buffer);
667}
668
669static int sun6i_dsi_start(struct sun6i_dsi *dsi,
670 enum sun6i_dsi_start_inst func)
671{
672 switch (func) {
673 case DSI_START_LPTX:
674 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
675 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
676 DSI_INST_ID_END << (4 * DSI_INST_ID_LPDT));
677 break;
678 case DSI_START_LPRX:
679 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
680 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
681 DSI_INST_ID_DLY << (4 * DSI_INST_ID_LPDT) |
682 DSI_INST_ID_TBA << (4 * DSI_INST_ID_DLY) |
683 DSI_INST_ID_END << (4 * DSI_INST_ID_TBA));
684 break;
685 case DSI_START_HSC:
686 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
687 DSI_INST_ID_HSC << (4 * DSI_INST_ID_LP11) |
688 DSI_INST_ID_END << (4 * DSI_INST_ID_HSC));
689 break;
690 case DSI_START_HSD:
691 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
692 DSI_INST_ID_NOP << (4 * DSI_INST_ID_LP11) |
693 DSI_INST_ID_HSD << (4 * DSI_INST_ID_NOP) |
694 DSI_INST_ID_DLY << (4 * DSI_INST_ID_HSD) |
695 DSI_INST_ID_NOP << (4 * DSI_INST_ID_DLY) |
696 DSI_INST_ID_END << (4 * DSI_INST_ID_HSCEXIT));
697 break;
698 default:
699 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
700 DSI_INST_ID_END << (4 * DSI_INST_ID_LP11));
701 break;
702 }
703
704 sun6i_dsi_inst_abort(dsi);
705 sun6i_dsi_inst_commit(dsi);
706
707 if (func == DSI_START_HSC)
708 regmap_write_bits(dsi->regs,
709 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
710 SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
711
712 return 0;
713}
714
715static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
716{
717 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
718 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
719 struct mipi_dsi_device *device = dsi->device;
720 union phy_configure_opts opts = { 0 };
721 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
722 u16 delay;
723
724 DRM_DEBUG_DRIVER("Enabling DSI output\n");
725
726 pm_runtime_get_sync(dsi->dev);
727
728 delay = sun6i_dsi_get_video_start_delay(dsi, mode);
729 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
730 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
731 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
732 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
733 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
734
735 sun6i_dsi_setup_burst(dsi, mode);
736 sun6i_dsi_setup_inst_loop(dsi, mode);
737 sun6i_dsi_setup_format(dsi, mode);
738 sun6i_dsi_setup_timings(dsi, mode);
739
740 phy_init(dsi->dphy);
741
742 phy_mipi_dphy_get_default_config(mode->clock * 1000,
743 mipi_dsi_pixel_format_to_bpp(device->format),
744 device->lanes, cfg);
745
746 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
747 phy_configure(dsi->dphy, &opts);
748 phy_power_on(dsi->dphy);
749
750 if (!IS_ERR(dsi->panel))
751 drm_panel_prepare(dsi->panel);
752
753
754
755
756
757
758
759
760
761
762
763
764
765 if (!IS_ERR(dsi->panel))
766 drm_panel_enable(dsi->panel);
767
768 sun6i_dsi_start(dsi, DSI_START_HSC);
769
770 udelay(1000);
771
772 sun6i_dsi_start(dsi, DSI_START_HSD);
773}
774
775static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
776{
777 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
778
779 DRM_DEBUG_DRIVER("Disabling DSI output\n");
780
781 if (!IS_ERR(dsi->panel)) {
782 drm_panel_disable(dsi->panel);
783 drm_panel_unprepare(dsi->panel);
784 }
785
786 phy_power_off(dsi->dphy);
787 phy_exit(dsi->dphy);
788
789 pm_runtime_put(dsi->dev);
790}
791
792static int sun6i_dsi_get_modes(struct drm_connector *connector)
793{
794 struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
795
796 return drm_panel_get_modes(dsi->panel);
797}
798
799static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
800 .get_modes = sun6i_dsi_get_modes,
801};
802
803static enum drm_connector_status
804sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
805{
806 return connector_status_connected;
807}
808
809static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
810 .detect = sun6i_dsi_connector_detect,
811 .fill_modes = drm_helper_probe_single_connector_modes,
812 .destroy = drm_connector_cleanup,
813 .reset = drm_atomic_helper_connector_reset,
814 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
815 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
816};
817
818static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
819 .disable = sun6i_dsi_encoder_disable,
820 .enable = sun6i_dsi_encoder_enable,
821};
822
823static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
824 .destroy = drm_encoder_cleanup,
825};
826
827static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
828 const struct mipi_dsi_msg *msg)
829{
830 u32 pkt = msg->type;
831
832 if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
833 pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
834 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
835 } else {
836 pkt |= (((u8 *)msg->tx_buf)[0] << 8);
837 if (msg->tx_len > 1)
838 pkt |= (((u8 *)msg->tx_buf)[1] << 16);
839 }
840
841 pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
842
843 return pkt;
844}
845
846static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
847 const struct mipi_dsi_msg *msg)
848{
849 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
850 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
851 regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
852 0xff, (4 - 1));
853
854 sun6i_dsi_start(dsi, DSI_START_LPTX);
855
856 return msg->tx_len;
857}
858
859static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
860 const struct mipi_dsi_msg *msg)
861{
862 int ret, len = 0;
863 u8 *bounce;
864 u16 crc;
865
866 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
867 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
868
869 bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
870 if (!bounce)
871 return -ENOMEM;
872
873 memcpy(bounce, msg->tx_buf, msg->tx_len);
874 len += msg->tx_len;
875
876 crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
877 memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
878 len += sizeof(crc);
879
880 regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
881 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
882 kfree(bounce);
883
884 sun6i_dsi_start(dsi, DSI_START_LPTX);
885
886 ret = sun6i_dsi_inst_wait_for_completion(dsi);
887 if (ret < 0) {
888 sun6i_dsi_inst_abort(dsi);
889 return ret;
890 }
891
892
893
894
895
896
897 return msg->tx_len;
898}
899
900static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
901 const struct mipi_dsi_msg *msg)
902{
903 u32 val;
904 int ret;
905 u8 byte0;
906
907 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
908 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
909 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
910 (4 - 1));
911
912 sun6i_dsi_start(dsi, DSI_START_LPRX);
913
914 ret = sun6i_dsi_inst_wait_for_completion(dsi);
915 if (ret < 0) {
916 sun6i_dsi_inst_abort(dsi);
917 return ret;
918 }
919
920
921
922
923
924
925 regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
926 if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
927 return -EIO;
928
929 regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
930 byte0 = val & 0xff;
931 if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
932 return -EIO;
933
934 ((u8 *)msg->rx_buf)[0] = (val >> 8);
935
936 return 1;
937}
938
939static int sun6i_dsi_attach(struct mipi_dsi_host *host,
940 struct mipi_dsi_device *device)
941{
942 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
943
944 dsi->device = device;
945 dsi->panel = of_drm_find_panel(device->dev.of_node);
946 if (IS_ERR(dsi->panel))
947 return PTR_ERR(dsi->panel);
948
949 dev_info(host->dev, "Attached device %s\n", device->name);
950
951 return 0;
952}
953
954static int sun6i_dsi_detach(struct mipi_dsi_host *host,
955 struct mipi_dsi_device *device)
956{
957 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
958
959 dsi->panel = NULL;
960 dsi->device = NULL;
961
962 return 0;
963}
964
965static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
966 const struct mipi_dsi_msg *msg)
967{
968 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
969 int ret;
970
971 ret = sun6i_dsi_inst_wait_for_completion(dsi);
972 if (ret < 0)
973 sun6i_dsi_inst_abort(dsi);
974
975 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
976 SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
977 SUN6I_DSI_CMD_CTL_RX_FLAG |
978 SUN6I_DSI_CMD_CTL_TX_FLAG);
979
980 switch (msg->type) {
981 case MIPI_DSI_DCS_SHORT_WRITE:
982 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
983 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
984 ret = sun6i_dsi_dcs_write_short(dsi, msg);
985 break;
986
987 case MIPI_DSI_DCS_LONG_WRITE:
988 ret = sun6i_dsi_dcs_write_long(dsi, msg);
989 break;
990
991 case MIPI_DSI_DCS_READ:
992 if (msg->rx_len == 1) {
993 ret = sun6i_dsi_dcs_read(dsi, msg);
994 break;
995 }
996
997
998 default:
999 ret = -EINVAL;
1000 }
1001
1002 return ret;
1003}
1004
1005static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
1006 .attach = sun6i_dsi_attach,
1007 .detach = sun6i_dsi_detach,
1008 .transfer = sun6i_dsi_transfer,
1009};
1010
1011static const struct regmap_config sun6i_dsi_regmap_config = {
1012 .reg_bits = 32,
1013 .val_bits = 32,
1014 .reg_stride = 4,
1015 .max_register = SUN6I_DSI_CMD_TX_REG(255),
1016 .name = "mipi-dsi",
1017};
1018
1019static int sun6i_dsi_bind(struct device *dev, struct device *master,
1020 void *data)
1021{
1022 struct drm_device *drm = data;
1023 struct sun4i_drv *drv = drm->dev_private;
1024 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1025 int ret;
1026
1027 if (!dsi->panel)
1028 return -EPROBE_DEFER;
1029
1030 dsi->drv = drv;
1031
1032 drm_encoder_helper_add(&dsi->encoder,
1033 &sun6i_dsi_enc_helper_funcs);
1034 ret = drm_encoder_init(drm,
1035 &dsi->encoder,
1036 &sun6i_dsi_enc_funcs,
1037 DRM_MODE_ENCODER_DSI,
1038 NULL);
1039 if (ret) {
1040 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
1041 return ret;
1042 }
1043 dsi->encoder.possible_crtcs = BIT(0);
1044
1045 drm_connector_helper_add(&dsi->connector,
1046 &sun6i_dsi_connector_helper_funcs);
1047 ret = drm_connector_init(drm, &dsi->connector,
1048 &sun6i_dsi_connector_funcs,
1049 DRM_MODE_CONNECTOR_DSI);
1050 if (ret) {
1051 dev_err(dsi->dev,
1052 "Couldn't initialise the DSI connector\n");
1053 goto err_cleanup_connector;
1054 }
1055
1056 drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
1057 drm_panel_attach(dsi->panel, &dsi->connector);
1058
1059 return 0;
1060
1061err_cleanup_connector:
1062 drm_encoder_cleanup(&dsi->encoder);
1063 return ret;
1064}
1065
1066static void sun6i_dsi_unbind(struct device *dev, struct device *master,
1067 void *data)
1068{
1069 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1070
1071 drm_panel_detach(dsi->panel);
1072}
1073
1074static const struct component_ops sun6i_dsi_ops = {
1075 .bind = sun6i_dsi_bind,
1076 .unbind = sun6i_dsi_unbind,
1077};
1078
1079static int sun6i_dsi_probe(struct platform_device *pdev)
1080{
1081 struct device *dev = &pdev->dev;
1082 struct sun6i_dsi *dsi;
1083 struct resource *res;
1084 void __iomem *base;
1085 int ret;
1086
1087 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1088 if (!dsi)
1089 return -ENOMEM;
1090 dev_set_drvdata(dev, dsi);
1091 dsi->dev = dev;
1092 dsi->host.ops = &sun6i_dsi_host_ops;
1093 dsi->host.dev = dev;
1094
1095 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1096 base = devm_ioremap_resource(dev, res);
1097 if (IS_ERR(base)) {
1098 dev_err(dev, "Couldn't map the DSI encoder registers\n");
1099 return PTR_ERR(base);
1100 }
1101
1102 dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
1103 &sun6i_dsi_regmap_config);
1104 if (IS_ERR(dsi->regs)) {
1105 dev_err(dev, "Couldn't create the DSI encoder regmap\n");
1106 return PTR_ERR(dsi->regs);
1107 }
1108
1109 dsi->reset = devm_reset_control_get_shared(dev, NULL);
1110 if (IS_ERR(dsi->reset)) {
1111 dev_err(dev, "Couldn't get our reset line\n");
1112 return PTR_ERR(dsi->reset);
1113 }
1114
1115 dsi->mod_clk = devm_clk_get(dev, "mod");
1116 if (IS_ERR(dsi->mod_clk)) {
1117 dev_err(dev, "Couldn't get the DSI mod clock\n");
1118 return PTR_ERR(dsi->mod_clk);
1119 }
1120
1121
1122
1123
1124
1125 clk_set_rate_exclusive(dsi->mod_clk, 297000000);
1126
1127 dsi->dphy = devm_phy_get(dev, "dphy");
1128 if (IS_ERR(dsi->dphy)) {
1129 dev_err(dev, "Couldn't get the MIPI D-PHY\n");
1130 ret = PTR_ERR(dsi->dphy);
1131 goto err_unprotect_clk;
1132 }
1133
1134 pm_runtime_enable(dev);
1135
1136 ret = mipi_dsi_host_register(&dsi->host);
1137 if (ret) {
1138 dev_err(dev, "Couldn't register MIPI-DSI host\n");
1139 goto err_pm_disable;
1140 }
1141
1142 ret = component_add(&pdev->dev, &sun6i_dsi_ops);
1143 if (ret) {
1144 dev_err(dev, "Couldn't register our component\n");
1145 goto err_remove_dsi_host;
1146 }
1147
1148 return 0;
1149
1150err_remove_dsi_host:
1151 mipi_dsi_host_unregister(&dsi->host);
1152err_pm_disable:
1153 pm_runtime_disable(dev);
1154err_unprotect_clk:
1155 clk_rate_exclusive_put(dsi->mod_clk);
1156 return ret;
1157}
1158
1159static int sun6i_dsi_remove(struct platform_device *pdev)
1160{
1161 struct device *dev = &pdev->dev;
1162 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1163
1164 component_del(&pdev->dev, &sun6i_dsi_ops);
1165 mipi_dsi_host_unregister(&dsi->host);
1166 pm_runtime_disable(dev);
1167 clk_rate_exclusive_put(dsi->mod_clk);
1168
1169 return 0;
1170}
1171
1172static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
1173{
1174 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1175
1176 reset_control_deassert(dsi->reset);
1177 clk_prepare_enable(dsi->mod_clk);
1178
1179
1180
1181
1182
1183
1184
1185 regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
1186
1187 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
1188 SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
1189
1190 regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
1191 regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
1192
1193 if (dsi->device)
1194 sun6i_dsi_inst_init(dsi, dsi->device);
1195
1196 regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
1197
1198 return 0;
1199}
1200
1201static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
1202{
1203 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1204
1205 clk_disable_unprepare(dsi->mod_clk);
1206 reset_control_assert(dsi->reset);
1207
1208 return 0;
1209}
1210
1211static const struct dev_pm_ops sun6i_dsi_pm_ops = {
1212 SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
1213 sun6i_dsi_runtime_resume,
1214 NULL)
1215};
1216
1217static const struct of_device_id sun6i_dsi_of_table[] = {
1218 { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
1219 { }
1220};
1221MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
1222
1223static struct platform_driver sun6i_dsi_platform_driver = {
1224 .probe = sun6i_dsi_probe,
1225 .remove = sun6i_dsi_remove,
1226 .driver = {
1227 .name = "sun6i-mipi-dsi",
1228 .of_match_table = sun6i_dsi_of_table,
1229 .pm = &sun6i_dsi_pm_ops,
1230 },
1231};
1232module_platform_driver(sun6i_dsi_platform_driver);
1233
1234MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1235MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1236MODULE_LICENSE("GPL");
1237
