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5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/gpio.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/of_gpio.h>
12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/pinctrl/pinmux.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/reset.h>
18#include <linux/regulator/consumer.h>
19#include <linux/workqueue.h>
20
21#include <drm/drm_dp_helper.h>
22#include <drm/drm_panel.h>
23
24#include "dpaux.h"
25#include "drm.h"
26#include "trace.h"
27
28static DEFINE_MUTEX(dpaux_lock);
29static LIST_HEAD(dpaux_list);
30
31struct tegra_dpaux {
32 struct drm_dp_aux aux;
33 struct device *dev;
34
35 void __iomem *regs;
36 int irq;
37
38 struct tegra_output *output;
39
40 struct reset_control *rst;
41 struct clk *clk_parent;
42 struct clk *clk;
43
44 struct regulator *vdd;
45
46 struct completion complete;
47 struct work_struct work;
48 struct list_head list;
49
50#ifdef CONFIG_GENERIC_PINCONF
51 struct pinctrl_dev *pinctrl;
52 struct pinctrl_desc desc;
53#endif
54};
55
56static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
57{
58 return container_of(aux, struct tegra_dpaux, aux);
59}
60
61static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
62{
63 return container_of(work, struct tegra_dpaux, work);
64}
65
66static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
67 unsigned int offset)
68{
69 u32 value = readl(dpaux->regs + (offset << 2));
70
71 trace_dpaux_readl(dpaux->dev, offset, value);
72
73 return value;
74}
75
76static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
77 u32 value, unsigned int offset)
78{
79 trace_dpaux_writel(dpaux->dev, offset, value);
80 writel(value, dpaux->regs + (offset << 2));
81}
82
83static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
84 size_t size)
85{
86 size_t i, j;
87
88 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
89 size_t num = min_t(size_t, size - i * 4, 4);
90 u32 value = 0;
91
92 for (j = 0; j < num; j++)
93 value |= buffer[i * 4 + j] << (j * 8);
94
95 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
96 }
97}
98
99static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
100 size_t size)
101{
102 size_t i, j;
103
104 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
105 size_t num = min_t(size_t, size - i * 4, 4);
106 u32 value;
107
108 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
109
110 for (j = 0; j < num; j++)
111 buffer[i * 4 + j] = value >> (j * 8);
112 }
113}
114
115static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
116 struct drm_dp_aux_msg *msg)
117{
118 unsigned long timeout = msecs_to_jiffies(250);
119 struct tegra_dpaux *dpaux = to_dpaux(aux);
120 unsigned long status;
121 ssize_t ret = 0;
122 u32 value;
123
124
125 if (msg->size > 16)
126 return -EINVAL;
127
128
129
130
131
132 if (msg->size < 1) {
133 switch (msg->request & ~DP_AUX_I2C_MOT) {
134 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
135 case DP_AUX_I2C_WRITE:
136 case DP_AUX_I2C_READ:
137 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
138 break;
139
140 default:
141 return -EINVAL;
142 }
143 } else {
144
145 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
146 }
147
148 switch (msg->request & ~DP_AUX_I2C_MOT) {
149 case DP_AUX_I2C_WRITE:
150 if (msg->request & DP_AUX_I2C_MOT)
151 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
152 else
153 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
154
155 break;
156
157 case DP_AUX_I2C_READ:
158 if (msg->request & DP_AUX_I2C_MOT)
159 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
160 else
161 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
162
163 break;
164
165 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
166 if (msg->request & DP_AUX_I2C_MOT)
167 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
168 else
169 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
170
171 break;
172
173 case DP_AUX_NATIVE_WRITE:
174 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
175 break;
176
177 case DP_AUX_NATIVE_READ:
178 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
179 break;
180
181 default:
182 return -EINVAL;
183 }
184
185 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
186 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
187
188 if ((msg->request & DP_AUX_I2C_READ) == 0) {
189 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
190 ret = msg->size;
191 }
192
193
194 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
195 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
197
198 status = wait_for_completion_timeout(&dpaux->complete, timeout);
199 if (!status)
200 return -ETIMEDOUT;
201
202
203 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
204 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
205
206 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
207 return -ETIMEDOUT;
208
209 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
210 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
211 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
212 return -EIO;
213
214 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
215 case 0x00:
216 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
217 break;
218
219 case 0x01:
220 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
221 break;
222
223 case 0x02:
224 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
225 break;
226
227 case 0x04:
228 msg->reply = DP_AUX_I2C_REPLY_NACK;
229 break;
230
231 case 0x08:
232 msg->reply = DP_AUX_I2C_REPLY_DEFER;
233 break;
234 }
235
236 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
237 if (msg->request & DP_AUX_I2C_READ) {
238 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
239
240 if (WARN_ON(count != msg->size))
241 count = min_t(size_t, count, msg->size);
242
243 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
244 ret = count;
245 }
246 }
247
248 return ret;
249}
250
251static void tegra_dpaux_hotplug(struct work_struct *work)
252{
253 struct tegra_dpaux *dpaux = work_to_dpaux(work);
254
255 if (dpaux->output)
256 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
257}
258
259static irqreturn_t tegra_dpaux_irq(int irq, void *data)
260{
261 struct tegra_dpaux *dpaux = data;
262 irqreturn_t ret = IRQ_HANDLED;
263 u32 value;
264
265
266 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
267 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
268
269 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
270 schedule_work(&dpaux->work);
271
272 if (value & DPAUX_INTR_IRQ_EVENT) {
273
274 }
275
276 if (value & DPAUX_INTR_AUX_DONE)
277 complete(&dpaux->complete);
278
279 return ret;
280}
281
282enum tegra_dpaux_functions {
283 DPAUX_PADCTL_FUNC_AUX,
284 DPAUX_PADCTL_FUNC_I2C,
285 DPAUX_PADCTL_FUNC_OFF,
286};
287
288static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
289{
290 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
291
292 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
293
294 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
295}
296
297static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
298{
299 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
300
301 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
302
303 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
304}
305
306static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
307{
308 u32 value;
309
310 switch (function) {
311 case DPAUX_PADCTL_FUNC_AUX:
312 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
313 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
314 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
315 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
316 DPAUX_HYBRID_PADCTL_MODE_AUX;
317 break;
318
319 case DPAUX_PADCTL_FUNC_I2C:
320 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
321 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
322 DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
323 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
324 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
325 DPAUX_HYBRID_PADCTL_MODE_I2C;
326 break;
327
328 case DPAUX_PADCTL_FUNC_OFF:
329 tegra_dpaux_pad_power_down(dpaux);
330 return 0;
331
332 default:
333 return -ENOTSUPP;
334 }
335
336 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
337 tegra_dpaux_pad_power_up(dpaux);
338
339 return 0;
340}
341
342#ifdef CONFIG_GENERIC_PINCONF
343static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
344 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
345 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
346};
347
348static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
349
350static const char * const tegra_dpaux_groups[] = {
351 "dpaux-io",
352};
353
354static const char * const tegra_dpaux_functions[] = {
355 "aux",
356 "i2c",
357 "off",
358};
359
360static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
361{
362 return ARRAY_SIZE(tegra_dpaux_groups);
363}
364
365static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
366 unsigned int group)
367{
368 return tegra_dpaux_groups[group];
369}
370
371static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
372 unsigned group, const unsigned **pins,
373 unsigned *num_pins)
374{
375 *pins = tegra_dpaux_pin_numbers;
376 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
377
378 return 0;
379}
380
381static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
382 .get_groups_count = tegra_dpaux_get_groups_count,
383 .get_group_name = tegra_dpaux_get_group_name,
384 .get_group_pins = tegra_dpaux_get_group_pins,
385 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
386 .dt_free_map = pinconf_generic_dt_free_map,
387};
388
389static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
390{
391 return ARRAY_SIZE(tegra_dpaux_functions);
392}
393
394static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
395 unsigned int function)
396{
397 return tegra_dpaux_functions[function];
398}
399
400static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
401 unsigned int function,
402 const char * const **groups,
403 unsigned * const num_groups)
404{
405 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
406 *groups = tegra_dpaux_groups;
407
408 return 0;
409}
410
411static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
412 unsigned int function, unsigned int group)
413{
414 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
415
416 return tegra_dpaux_pad_config(dpaux, function);
417}
418
419static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
420 .get_functions_count = tegra_dpaux_get_functions_count,
421 .get_function_name = tegra_dpaux_get_function_name,
422 .get_function_groups = tegra_dpaux_get_function_groups,
423 .set_mux = tegra_dpaux_set_mux,
424};
425#endif
426
427static int tegra_dpaux_probe(struct platform_device *pdev)
428{
429 struct tegra_dpaux *dpaux;
430 struct resource *regs;
431 u32 value;
432 int err;
433
434 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
435 if (!dpaux)
436 return -ENOMEM;
437
438 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
439 init_completion(&dpaux->complete);
440 INIT_LIST_HEAD(&dpaux->list);
441 dpaux->dev = &pdev->dev;
442
443 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
445 if (IS_ERR(dpaux->regs))
446 return PTR_ERR(dpaux->regs);
447
448 dpaux->irq = platform_get_irq(pdev, 0);
449 if (dpaux->irq < 0) {
450 dev_err(&pdev->dev, "failed to get IRQ\n");
451 return -ENXIO;
452 }
453
454 if (!pdev->dev.pm_domain) {
455 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
456 if (IS_ERR(dpaux->rst)) {
457 dev_err(&pdev->dev,
458 "failed to get reset control: %ld\n",
459 PTR_ERR(dpaux->rst));
460 return PTR_ERR(dpaux->rst);
461 }
462 }
463
464 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
465 if (IS_ERR(dpaux->clk)) {
466 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
467 PTR_ERR(dpaux->clk));
468 return PTR_ERR(dpaux->clk);
469 }
470
471 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
472 if (IS_ERR(dpaux->clk_parent)) {
473 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
474 PTR_ERR(dpaux->clk_parent));
475 return PTR_ERR(dpaux->clk_parent);
476 }
477
478 err = clk_set_rate(dpaux->clk_parent, 270000000);
479 if (err < 0) {
480 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
481 err);
482 return err;
483 }
484
485 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
486 if (IS_ERR(dpaux->vdd)) {
487 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
488 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
489 dev_err(&pdev->dev,
490 "failed to get VDD supply: %ld\n",
491 PTR_ERR(dpaux->vdd));
492
493 return PTR_ERR(dpaux->vdd);
494 }
495 }
496
497 platform_set_drvdata(pdev, dpaux);
498 pm_runtime_enable(&pdev->dev);
499 pm_runtime_get_sync(&pdev->dev);
500
501 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
502 dev_name(dpaux->dev), dpaux);
503 if (err < 0) {
504 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
505 dpaux->irq, err);
506 return err;
507 }
508
509 disable_irq(dpaux->irq);
510
511 dpaux->aux.transfer = tegra_dpaux_transfer;
512 dpaux->aux.dev = &pdev->dev;
513
514 err = drm_dp_aux_register(&dpaux->aux);
515 if (err < 0)
516 return err;
517
518
519
520
521
522
523
524
525
526 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
527 if (err < 0)
528 return err;
529
530#ifdef CONFIG_GENERIC_PINCONF
531 dpaux->desc.name = dev_name(&pdev->dev);
532 dpaux->desc.pins = tegra_dpaux_pins;
533 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
534 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
535 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
536 dpaux->desc.owner = THIS_MODULE;
537
538 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
539 if (IS_ERR(dpaux->pinctrl)) {
540 dev_err(&pdev->dev, "failed to register pincontrol\n");
541 return PTR_ERR(dpaux->pinctrl);
542 }
543#endif
544
545 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
546 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
547 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
548 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
549
550 mutex_lock(&dpaux_lock);
551 list_add_tail(&dpaux->list, &dpaux_list);
552 mutex_unlock(&dpaux_lock);
553
554 return 0;
555}
556
557static int tegra_dpaux_remove(struct platform_device *pdev)
558{
559 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
560
561 cancel_work_sync(&dpaux->work);
562
563
564 tegra_dpaux_pad_power_down(dpaux);
565
566 pm_runtime_put(&pdev->dev);
567 pm_runtime_disable(&pdev->dev);
568
569 drm_dp_aux_unregister(&dpaux->aux);
570
571 mutex_lock(&dpaux_lock);
572 list_del(&dpaux->list);
573 mutex_unlock(&dpaux_lock);
574
575 return 0;
576}
577
578#ifdef CONFIG_PM
579static int tegra_dpaux_suspend(struct device *dev)
580{
581 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
582 int err = 0;
583
584 if (dpaux->rst) {
585 err = reset_control_assert(dpaux->rst);
586 if (err < 0) {
587 dev_err(dev, "failed to assert reset: %d\n", err);
588 return err;
589 }
590 }
591
592 usleep_range(1000, 2000);
593
594 clk_disable_unprepare(dpaux->clk_parent);
595 clk_disable_unprepare(dpaux->clk);
596
597 return err;
598}
599
600static int tegra_dpaux_resume(struct device *dev)
601{
602 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
603 int err;
604
605 err = clk_prepare_enable(dpaux->clk);
606 if (err < 0) {
607 dev_err(dev, "failed to enable clock: %d\n", err);
608 return err;
609 }
610
611 err = clk_prepare_enable(dpaux->clk_parent);
612 if (err < 0) {
613 dev_err(dev, "failed to enable parent clock: %d\n", err);
614 goto disable_clk;
615 }
616
617 usleep_range(1000, 2000);
618
619 if (dpaux->rst) {
620 err = reset_control_deassert(dpaux->rst);
621 if (err < 0) {
622 dev_err(dev, "failed to deassert reset: %d\n", err);
623 goto disable_parent;
624 }
625
626 usleep_range(1000, 2000);
627 }
628
629 return 0;
630
631disable_parent:
632 clk_disable_unprepare(dpaux->clk_parent);
633disable_clk:
634 clk_disable_unprepare(dpaux->clk);
635 return err;
636}
637#endif
638
639static const struct dev_pm_ops tegra_dpaux_pm_ops = {
640 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
641};
642
643static const struct of_device_id tegra_dpaux_of_match[] = {
644 { .compatible = "nvidia,tegra194-dpaux", },
645 { .compatible = "nvidia,tegra186-dpaux", },
646 { .compatible = "nvidia,tegra210-dpaux", },
647 { .compatible = "nvidia,tegra124-dpaux", },
648 { },
649};
650MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
651
652struct platform_driver tegra_dpaux_driver = {
653 .driver = {
654 .name = "tegra-dpaux",
655 .of_match_table = tegra_dpaux_of_match,
656 .pm = &tegra_dpaux_pm_ops,
657 },
658 .probe = tegra_dpaux_probe,
659 .remove = tegra_dpaux_remove,
660};
661
662struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
663{
664 struct tegra_dpaux *dpaux;
665
666 mutex_lock(&dpaux_lock);
667
668 list_for_each_entry(dpaux, &dpaux_list, list)
669 if (np == dpaux->dev->of_node) {
670 mutex_unlock(&dpaux_lock);
671 return &dpaux->aux;
672 }
673
674 mutex_unlock(&dpaux_lock);
675
676 return NULL;
677}
678
679int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
680{
681 struct tegra_dpaux *dpaux = to_dpaux(aux);
682 unsigned long timeout;
683 int err;
684
685 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
686 dpaux->output = output;
687
688 err = regulator_enable(dpaux->vdd);
689 if (err < 0)
690 return err;
691
692 timeout = jiffies + msecs_to_jiffies(250);
693
694 while (time_before(jiffies, timeout)) {
695 enum drm_connector_status status;
696
697 status = drm_dp_aux_detect(aux);
698 if (status == connector_status_connected) {
699 enable_irq(dpaux->irq);
700 return 0;
701 }
702
703 usleep_range(1000, 2000);
704 }
705
706 return -ETIMEDOUT;
707}
708
709int drm_dp_aux_detach(struct drm_dp_aux *aux)
710{
711 struct tegra_dpaux *dpaux = to_dpaux(aux);
712 unsigned long timeout;
713 int err;
714
715 disable_irq(dpaux->irq);
716
717 err = regulator_disable(dpaux->vdd);
718 if (err < 0)
719 return err;
720
721 timeout = jiffies + msecs_to_jiffies(250);
722
723 while (time_before(jiffies, timeout)) {
724 enum drm_connector_status status;
725
726 status = drm_dp_aux_detect(aux);
727 if (status == connector_status_disconnected) {
728 dpaux->output = NULL;
729 return 0;
730 }
731
732 usleep_range(1000, 2000);
733 }
734
735 return -ETIMEDOUT;
736}
737
738enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
739{
740 struct tegra_dpaux *dpaux = to_dpaux(aux);
741 u32 value;
742
743 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
744
745 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
746 return connector_status_connected;
747
748 return connector_status_disconnected;
749}
750
751int drm_dp_aux_enable(struct drm_dp_aux *aux)
752{
753 struct tegra_dpaux *dpaux = to_dpaux(aux);
754
755 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
756}
757
758int drm_dp_aux_disable(struct drm_dp_aux *aux)
759{
760 struct tegra_dpaux *dpaux = to_dpaux(aux);
761
762 tegra_dpaux_pad_power_down(dpaux);
763
764 return 0;
765}
766
767int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
768{
769 int err;
770
771 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
772 encoding);
773 if (err < 0)
774 return err;
775
776 return 0;
777}
778
779int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
780 u8 pattern)
781{
782 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
783 u8 status[DP_LINK_STATUS_SIZE], values[4];
784 unsigned int i;
785 int err;
786
787 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
788 if (err < 0)
789 return err;
790
791 if (tp == DP_TRAINING_PATTERN_DISABLE)
792 return 0;
793
794 for (i = 0; i < link->num_lanes; i++)
795 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
796 DP_TRAIN_PRE_EMPH_LEVEL_0 |
797 DP_TRAIN_MAX_SWING_REACHED |
798 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
799
800 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
801 link->num_lanes);
802 if (err < 0)
803 return err;
804
805 usleep_range(500, 1000);
806
807 err = drm_dp_dpcd_read_link_status(aux, status);
808 if (err < 0)
809 return err;
810
811 switch (tp) {
812 case DP_TRAINING_PATTERN_1:
813 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
814 return -EAGAIN;
815
816 break;
817
818 case DP_TRAINING_PATTERN_2:
819 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
820 return -EAGAIN;
821
822 break;
823
824 default:
825 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
826 return -EINVAL;
827 }
828
829 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
830 if (err < 0)
831 return err;
832
833 return 0;
834}
835
