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6
7#include <drm/drm_atomic.h>
8#include <drm/drm_atomic_helper.h>
9#include <drm/drm_crtc.h>
10#include <drm/drm_flip_work.h>
11#include <drm/drm_plane_helper.h>
12#include <linux/workqueue.h>
13#include <linux/completion.h>
14#include <linux/dma-mapping.h>
15#include <linux/of_graph.h>
16#include <linux/math64.h>
17
18#include "tilcdc_drv.h"
19#include "tilcdc_regs.h"
20
21#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
22#define TILCDC_PALETTE_SIZE 32
23#define TILCDC_PALETTE_FIRST_ENTRY 0x4000
24
25struct tilcdc_crtc {
26 struct drm_crtc base;
27
28 struct drm_plane primary;
29 const struct tilcdc_panel_info *info;
30 struct drm_pending_vblank_event *event;
31 struct mutex enable_lock;
32 bool enabled;
33 bool shutdown;
34 wait_queue_head_t frame_done_wq;
35 bool frame_done;
36 spinlock_t irq_lock;
37
38 unsigned int lcd_fck_rate;
39
40 ktime_t last_vblank;
41 unsigned int hvtotal_us;
42
43 struct drm_framebuffer *next_fb;
44
45
46 bool simulate_vesa_sync;
47
48 int sync_lost_count;
49 bool frame_intact;
50 struct work_struct recover_work;
51
52 dma_addr_t palette_dma_handle;
53 u16 *palette_base;
54 struct completion palette_loaded;
55};
56#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
57
58static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
59{
60 struct drm_device *dev = crtc->dev;
61 struct tilcdc_drm_private *priv = dev->dev_private;
62 struct drm_gem_cma_object *gem;
63 dma_addr_t start, end;
64 u64 dma_base_and_ceiling;
65
66 gem = drm_fb_cma_get_gem_obj(fb, 0);
67
68 start = gem->paddr + fb->offsets[0] +
69 crtc->y * fb->pitches[0] +
70 crtc->x * fb->format->cpp[0];
71
72 end = start + (crtc->mode.vdisplay * fb->pitches[0]);
73
74
75
76
77
78
79 if (priv->rev == 1)
80 end -= 1;
81
82 dma_base_and_ceiling = (u64)end << 32 | start;
83 tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
84}
85
86
87
88
89
90
91
92static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
93{
94 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
95 struct drm_device *dev = crtc->dev;
96 struct tilcdc_drm_private *priv = dev->dev_private;
97 int ret;
98
99 reinit_completion(&tilcdc_crtc->palette_loaded);
100
101
102 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
103 tilcdc_crtc->palette_dma_handle);
104 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
105 (u32) tilcdc_crtc->palette_dma_handle +
106 TILCDC_PALETTE_SIZE - 1);
107
108
109 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
110 LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
111 LCDC_PALETTE_LOAD_MODE_MASK);
112
113
114 if (priv->rev == 1)
115 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
116 else
117 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
118
119
120 tilcdc_clear_irqstatus(dev, 0xffffffff);
121 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
122
123 ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded,
124 msecs_to_jiffies(50));
125 if (ret == 0)
126 dev_err(dev->dev, "%s: Palette loading timeout", __func__);
127
128
129 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
130 if (priv->rev == 1)
131 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
132 else
133 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
134}
135
136static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
137{
138 struct tilcdc_drm_private *priv = dev->dev_private;
139
140 tilcdc_clear_irqstatus(dev, 0xffffffff);
141
142 if (priv->rev == 1) {
143 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
144 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
145 LCDC_V1_UNDERFLOW_INT_ENA);
146 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
147 LCDC_V1_END_OF_FRAME_INT_ENA);
148 } else {
149 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
150 LCDC_V2_UNDERFLOW_INT_ENA |
151 LCDC_V2_END_OF_FRAME0_INT_ENA |
152 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
153 }
154}
155
156static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
157{
158 struct tilcdc_drm_private *priv = dev->dev_private;
159
160
161 if (priv->rev == 1) {
162 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
163 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
164 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
165 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
166 LCDC_V1_END_OF_FRAME_INT_ENA);
167 } else {
168 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
169 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
170 LCDC_V2_END_OF_FRAME0_INT_ENA |
171 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
172 }
173}
174
175static void reset(struct drm_crtc *crtc)
176{
177 struct drm_device *dev = crtc->dev;
178 struct tilcdc_drm_private *priv = dev->dev_private;
179
180 if (priv->rev != 2)
181 return;
182
183 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
184 usleep_range(250, 1000);
185 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
186}
187
188
189
190
191
192static unsigned int tilcdc_pclk_diff(unsigned long rate,
193 unsigned long real_rate)
194{
195 int r = rate / 100, rr = real_rate / 100;
196
197 return (unsigned int)(abs(((rr - r) * 100) / r));
198}
199
200static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
201{
202 struct drm_device *dev = crtc->dev;
203 struct tilcdc_drm_private *priv = dev->dev_private;
204 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
205 unsigned long clk_rate, real_rate, req_rate;
206 unsigned int clkdiv;
207 int ret;
208
209 clkdiv = 2;
210
211
212 req_rate = crtc->mode.clock * 1000;
213
214 ret = clk_set_rate(priv->clk, req_rate * clkdiv);
215 clk_rate = clk_get_rate(priv->clk);
216 if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) {
217
218
219
220
221
222
223
224 if (!clk_rate) {
225
226 dev_err(dev->dev,
227 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
228 return;
229 }
230
231 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate);
232
233
234
235
236
237
238
239
240 real_rate = clkdiv * req_rate;
241
242 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
243 dev_warn(dev->dev,
244 "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
245 clk_rate, real_rate);
246 }
247 }
248
249 tilcdc_crtc->lcd_fck_rate = clk_rate;
250
251 DBG("lcd_clk=%u, mode clock=%d, div=%u",
252 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
253
254
255 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
256 LCDC_RASTER_MODE);
257
258 if (priv->rev == 2)
259 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
260 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
261 LCDC_V2_CORE_CLK_EN);
262}
263
264static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode)
265{
266 return (uint) div_u64(1000llu * mode->htotal * mode->vtotal,
267 mode->clock);
268}
269
270static void tilcdc_crtc_set_mode(struct drm_crtc *crtc)
271{
272 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct tilcdc_drm_private *priv = dev->dev_private;
275 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
276 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
277 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
278 struct drm_framebuffer *fb = crtc->primary->state->fb;
279
280 if (WARN_ON(!info))
281 return;
282
283 if (WARN_ON(!fb))
284 return;
285
286
287 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
288 switch (info->dma_burst_sz) {
289 case 1:
290 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
291 break;
292 case 2:
293 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
294 break;
295 case 4:
296 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
297 break;
298 case 8:
299 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
300 break;
301 case 16:
302 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
303 break;
304 default:
305 dev_err(dev->dev, "invalid burst size\n");
306 return;
307 }
308 reg |= (info->fifo_th << 8);
309 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
310
311
312 hbp = mode->htotal - mode->hsync_end;
313 hfp = mode->hsync_start - mode->hdisplay;
314 hsw = mode->hsync_end - mode->hsync_start;
315 vbp = mode->vtotal - mode->vsync_end;
316 vfp = mode->vsync_start - mode->vdisplay;
317 vsw = mode->vsync_end - mode->vsync_start;
318
319 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
320 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
321
322
323 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
324 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
325 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
326
327
328
329
330
331 if (priv->rev == 2) {
332
333 reg &= ~0x78000033;
334 reg |= ((hfp-1) & 0x300) >> 8;
335 reg |= ((hbp-1) & 0x300) >> 4;
336 reg |= ((hsw-1) & 0x3c0) << 21;
337 }
338 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
339
340 reg = (((mode->hdisplay >> 4) - 1) << 4) |
341 (((hbp-1) & 0xff) << 24) |
342 (((hfp-1) & 0xff) << 16) |
343 (((hsw-1) & 0x3f) << 10);
344 if (priv->rev == 2)
345 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
346 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
347
348 reg = ((mode->vdisplay - 1) & 0x3ff) |
349 ((vbp & 0xff) << 24) |
350 ((vfp & 0xff) << 16) |
351 (((vsw-1) & 0x3f) << 10);
352 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
353
354
355
356
357
358
359 if (priv->rev == 2) {
360 if ((mode->vdisplay - 1) & 0x400) {
361 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
362 LCDC_LPP_B10);
363 } else {
364 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
365 LCDC_LPP_B10);
366 }
367 }
368
369
370 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
371 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
372 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
373 0x000ff000 );
374 reg |= LCDC_TFT_MODE;
375 if (info->tft_alt_mode)
376 reg |= LCDC_TFT_ALT_ENABLE;
377 if (priv->rev == 2) {
378 switch (fb->format->format) {
379 case DRM_FORMAT_BGR565:
380 case DRM_FORMAT_RGB565:
381 break;
382 case DRM_FORMAT_XBGR8888:
383 case DRM_FORMAT_XRGB8888:
384 reg |= LCDC_V2_TFT_24BPP_UNPACK;
385
386 case DRM_FORMAT_BGR888:
387 case DRM_FORMAT_RGB888:
388 reg |= LCDC_V2_TFT_24BPP_MODE;
389 break;
390 default:
391 dev_err(dev->dev, "invalid pixel format\n");
392 return;
393 }
394 }
395 reg |= info->fdd < 12;
396 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
397
398 if (info->invert_pxl_clk)
399 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
400 else
401 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
402
403 if (info->sync_ctrl)
404 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
405 else
406 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
407
408 if (info->sync_edge)
409 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
410 else
411 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
412
413 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
414 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
415 else
416 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
417
418 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
419 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
420 else
421 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
422
423 if (info->raster_order)
424 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
425 else
426 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
427
428 tilcdc_crtc_set_clk(crtc);
429
430 tilcdc_crtc_load_palette(crtc);
431
432 set_scanout(crtc, fb);
433
434 crtc->hwmode = crtc->state->adjusted_mode;
435
436 tilcdc_crtc->hvtotal_us =
437 tilcdc_mode_hvtotal(&crtc->hwmode);
438}
439
440static void tilcdc_crtc_enable(struct drm_crtc *crtc)
441{
442 struct drm_device *dev = crtc->dev;
443 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
444 unsigned long flags;
445
446 mutex_lock(&tilcdc_crtc->enable_lock);
447 if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
448 mutex_unlock(&tilcdc_crtc->enable_lock);
449 return;
450 }
451
452 pm_runtime_get_sync(dev->dev);
453
454 reset(crtc);
455
456 tilcdc_crtc_set_mode(crtc);
457
458 tilcdc_crtc_enable_irqs(dev);
459
460 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
461 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
462 LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
463 LCDC_PALETTE_LOAD_MODE_MASK);
464
465
466
467
468
469
470
471 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
472 tilcdc_crtc->last_vblank = ktime_get();
473 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
474 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
475
476 drm_crtc_vblank_on(crtc);
477
478 tilcdc_crtc->enabled = true;
479 mutex_unlock(&tilcdc_crtc->enable_lock);
480}
481
482static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,
483 struct drm_crtc_state *old_state)
484{
485 tilcdc_crtc_enable(crtc);
486}
487
488static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
489{
490 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
491 struct drm_device *dev = crtc->dev;
492 int ret;
493
494 mutex_lock(&tilcdc_crtc->enable_lock);
495 if (shutdown)
496 tilcdc_crtc->shutdown = true;
497 if (!tilcdc_crtc->enabled) {
498 mutex_unlock(&tilcdc_crtc->enable_lock);
499 return;
500 }
501 tilcdc_crtc->frame_done = false;
502 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
503
504
505
506
507
508 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
509 tilcdc_crtc->frame_done,
510 msecs_to_jiffies(500));
511 if (ret == 0)
512 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
513 __func__);
514
515 drm_crtc_vblank_off(crtc);
516
517 tilcdc_crtc_disable_irqs(dev);
518
519 pm_runtime_put_sync(dev->dev);
520
521 tilcdc_crtc->enabled = false;
522 mutex_unlock(&tilcdc_crtc->enable_lock);
523}
524
525static void tilcdc_crtc_disable(struct drm_crtc *crtc)
526{
527 tilcdc_crtc_off(crtc, false);
528}
529
530static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,
531 struct drm_crtc_state *old_state)
532{
533 tilcdc_crtc_disable(crtc);
534}
535
536void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
537{
538 tilcdc_crtc_off(crtc, true);
539}
540
541static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
542{
543 return crtc->state && crtc->state->enable && crtc->state->active;
544}
545
546static void tilcdc_crtc_recover_work(struct work_struct *work)
547{
548 struct tilcdc_crtc *tilcdc_crtc =
549 container_of(work, struct tilcdc_crtc, recover_work);
550 struct drm_crtc *crtc = &tilcdc_crtc->base;
551
552 dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
553
554 drm_modeset_lock(&crtc->mutex, NULL);
555
556 if (!tilcdc_crtc_is_on(crtc))
557 goto out;
558
559 tilcdc_crtc_disable(crtc);
560 tilcdc_crtc_enable(crtc);
561out:
562 drm_modeset_unlock(&crtc->mutex);
563}
564
565static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
566{
567 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
568
569 tilcdc_crtc_shutdown(crtc);
570
571 flush_workqueue(priv->wq);
572
573 of_node_put(crtc->port);
574 drm_crtc_cleanup(crtc);
575}
576
577int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
578 struct drm_framebuffer *fb,
579 struct drm_pending_vblank_event *event)
580{
581 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
582 struct drm_device *dev = crtc->dev;
583
584 if (tilcdc_crtc->event) {
585 dev_err(dev->dev, "already pending page flip!\n");
586 return -EBUSY;
587 }
588
589 tilcdc_crtc->event = event;
590
591 mutex_lock(&tilcdc_crtc->enable_lock);
592
593 if (tilcdc_crtc->enabled) {
594 unsigned long flags;
595 ktime_t next_vblank;
596 s64 tdiff;
597
598 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
599
600 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
601 tilcdc_crtc->hvtotal_us);
602 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
603
604 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
605 tilcdc_crtc->next_fb = fb;
606 else
607 set_scanout(crtc, fb);
608
609 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
610 }
611
612 mutex_unlock(&tilcdc_crtc->enable_lock);
613
614 return 0;
615}
616
617static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
618 const struct drm_display_mode *mode,
619 struct drm_display_mode *adjusted_mode)
620{
621 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
622
623 if (!tilcdc_crtc->simulate_vesa_sync)
624 return true;
625
626
627
628
629
630
631
632 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
633 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
634
635 if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
636 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
637 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
638 } else {
639 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
640 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
641 }
642
643 return true;
644}
645
646static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
647 struct drm_crtc_state *state)
648{
649 struct drm_display_mode *mode = &state->mode;
650 int ret;
651
652
653 if (!state->active)
654 return 0;
655
656 if (state->state->planes[0].ptr != crtc->primary ||
657 state->state->planes[0].state == NULL ||
658 state->state->planes[0].state->crtc != crtc) {
659 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
660 return -EINVAL;
661 }
662
663 ret = tilcdc_crtc_mode_valid(crtc, mode);
664 if (ret) {
665 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
666 return -EINVAL;
667 }
668
669 return 0;
670}
671
672static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc)
673{
674 return 0;
675}
676
677static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc)
678{
679}
680
681static void tilcdc_crtc_reset(struct drm_crtc *crtc)
682{
683 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
684 struct drm_device *dev = crtc->dev;
685 int ret;
686
687 drm_atomic_helper_crtc_reset(crtc);
688
689
690 pm_runtime_get_sync(dev->dev);
691 if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
692
693 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE);
694 tilcdc_clear_irqstatus(dev, 0xffffffff);
695
696 tilcdc_crtc->frame_done = false;
697 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
698
699 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
700 tilcdc_crtc->frame_done,
701 msecs_to_jiffies(500));
702 if (ret == 0)
703 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
704 __func__);
705 }
706 pm_runtime_put_sync(dev->dev);
707}
708
709static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
710 .destroy = tilcdc_crtc_destroy,
711 .set_config = drm_atomic_helper_set_config,
712 .page_flip = drm_atomic_helper_page_flip,
713 .reset = tilcdc_crtc_reset,
714 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
715 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
716 .enable_vblank = tilcdc_crtc_enable_vblank,
717 .disable_vblank = tilcdc_crtc_disable_vblank,
718};
719
720static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
721 .mode_fixup = tilcdc_crtc_mode_fixup,
722 .atomic_check = tilcdc_crtc_atomic_check,
723 .atomic_enable = tilcdc_crtc_atomic_enable,
724 .atomic_disable = tilcdc_crtc_atomic_disable,
725};
726
727int tilcdc_crtc_max_width(struct drm_crtc *crtc)
728{
729 struct drm_device *dev = crtc->dev;
730 struct tilcdc_drm_private *priv = dev->dev_private;
731 int max_width = 0;
732
733 if (priv->rev == 1)
734 max_width = 1024;
735 else if (priv->rev == 2)
736 max_width = 2048;
737
738 return max_width;
739}
740
741int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
742{
743 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
744 unsigned int bandwidth;
745 uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
746
747
748
749
750
751 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
752 return MODE_VIRTUAL_X;
753
754
755 if (mode->hdisplay & 0xf)
756 return MODE_VIRTUAL_X;
757
758 if (mode->vdisplay > 2048)
759 return MODE_VIRTUAL_Y;
760
761 DBG("Processing mode %dx%d@%d with pixel clock %d",
762 mode->hdisplay, mode->vdisplay,
763 drm_mode_vrefresh(mode), mode->clock);
764
765 hbp = mode->htotal - mode->hsync_end;
766 hfp = mode->hsync_start - mode->hdisplay;
767 hsw = mode->hsync_end - mode->hsync_start;
768 vbp = mode->vtotal - mode->vsync_end;
769 vfp = mode->vsync_start - mode->vdisplay;
770 vsw = mode->vsync_end - mode->vsync_start;
771
772 if ((hbp-1) & ~0x3ff) {
773 DBG("Pruning mode: Horizontal Back Porch out of range");
774 return MODE_HBLANK_WIDE;
775 }
776
777 if ((hfp-1) & ~0x3ff) {
778 DBG("Pruning mode: Horizontal Front Porch out of range");
779 return MODE_HBLANK_WIDE;
780 }
781
782 if ((hsw-1) & ~0x3ff) {
783 DBG("Pruning mode: Horizontal Sync Width out of range");
784 return MODE_HSYNC_WIDE;
785 }
786
787 if (vbp & ~0xff) {
788 DBG("Pruning mode: Vertical Back Porch out of range");
789 return MODE_VBLANK_WIDE;
790 }
791
792 if (vfp & ~0xff) {
793 DBG("Pruning mode: Vertical Front Porch out of range");
794 return MODE_VBLANK_WIDE;
795 }
796
797 if ((vsw-1) & ~0x3f) {
798 DBG("Pruning mode: Vertical Sync Width out of range");
799 return MODE_VSYNC_WIDE;
800 }
801
802
803
804
805
806 if (mode->clock > priv->max_pixelclock) {
807 DBG("Pruning mode: pixel clock too high");
808 return MODE_CLOCK_HIGH;
809 }
810
811
812
813
814
815 if (mode->hdisplay > priv->max_width)
816 return MODE_BAD_WIDTH;
817
818
819 bandwidth = mode->hdisplay * mode->vdisplay *
820 drm_mode_vrefresh(mode);
821 if (bandwidth > priv->max_bandwidth) {
822 DBG("Pruning mode: exceeds defined bandwidth limit");
823 return MODE_BAD;
824 }
825
826 return MODE_OK;
827}
828
829void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
830 const struct tilcdc_panel_info *info)
831{
832 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
833 tilcdc_crtc->info = info;
834}
835
836void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
837 bool simulate_vesa_sync)
838{
839 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
840
841 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
842}
843
844void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
845{
846 struct drm_device *dev = crtc->dev;
847 struct tilcdc_drm_private *priv = dev->dev_private;
848 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
849
850 drm_modeset_lock(&crtc->mutex, NULL);
851 if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
852 if (tilcdc_crtc_is_on(crtc)) {
853 pm_runtime_get_sync(dev->dev);
854 tilcdc_crtc_disable(crtc);
855
856 tilcdc_crtc_set_clk(crtc);
857
858 tilcdc_crtc_enable(crtc);
859 pm_runtime_put_sync(dev->dev);
860 }
861 }
862 drm_modeset_unlock(&crtc->mutex);
863}
864
865#define SYNC_LOST_COUNT_LIMIT 50
866
867irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
868{
869 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
870 struct drm_device *dev = crtc->dev;
871 struct tilcdc_drm_private *priv = dev->dev_private;
872 uint32_t stat, reg;
873
874 stat = tilcdc_read_irqstatus(dev);
875 tilcdc_clear_irqstatus(dev, stat);
876
877 if (stat & LCDC_END_OF_FRAME0) {
878 unsigned long flags;
879 bool skip_event = false;
880 ktime_t now;
881
882 now = ktime_get();
883
884 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
885
886 tilcdc_crtc->last_vblank = now;
887
888 if (tilcdc_crtc->next_fb) {
889 set_scanout(crtc, tilcdc_crtc->next_fb);
890 tilcdc_crtc->next_fb = NULL;
891 skip_event = true;
892 }
893
894 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
895
896 drm_crtc_handle_vblank(crtc);
897
898 if (!skip_event) {
899 struct drm_pending_vblank_event *event;
900
901 spin_lock_irqsave(&dev->event_lock, flags);
902
903 event = tilcdc_crtc->event;
904 tilcdc_crtc->event = NULL;
905 if (event)
906 drm_crtc_send_vblank_event(crtc, event);
907
908 spin_unlock_irqrestore(&dev->event_lock, flags);
909 }
910
911 if (tilcdc_crtc->frame_intact)
912 tilcdc_crtc->sync_lost_count = 0;
913 else
914 tilcdc_crtc->frame_intact = true;
915 }
916
917 if (stat & LCDC_FIFO_UNDERFLOW)
918 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
919 __func__, stat);
920
921 if (stat & LCDC_PL_LOAD_DONE) {
922 complete(&tilcdc_crtc->palette_loaded);
923 if (priv->rev == 1)
924 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
925 LCDC_V1_PL_INT_ENA);
926 else
927 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
928 LCDC_V2_PL_INT_ENA);
929 }
930
931 if (stat & LCDC_SYNC_LOST) {
932 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
933 __func__, stat);
934 tilcdc_crtc->frame_intact = false;
935 if (priv->rev == 1) {
936 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
937 if (reg & LCDC_RASTER_ENABLE) {
938 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
939 LCDC_RASTER_ENABLE);
940 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
941 LCDC_RASTER_ENABLE);
942 }
943 } else {
944 if (tilcdc_crtc->sync_lost_count++ >
945 SYNC_LOST_COUNT_LIMIT) {
946 dev_err(dev->dev,
947 "%s(0x%08x): Sync lost flood detected, recovering",
948 __func__, stat);
949 queue_work(system_wq,
950 &tilcdc_crtc->recover_work);
951 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
952 LCDC_SYNC_LOST);
953 tilcdc_crtc->sync_lost_count = 0;
954 }
955 }
956 }
957
958 if (stat & LCDC_FRAME_DONE) {
959 tilcdc_crtc->frame_done = true;
960 wake_up(&tilcdc_crtc->frame_done_wq);
961
962 if (priv->rev == 1)
963 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
964 LCDC_V1_FRAME_DONE_INT_ENA);
965 }
966
967
968 if (priv->rev == 2) {
969
970
971
972 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
973 }
974
975 return IRQ_HANDLED;
976}
977
978int tilcdc_crtc_create(struct drm_device *dev)
979{
980 struct tilcdc_drm_private *priv = dev->dev_private;
981 struct tilcdc_crtc *tilcdc_crtc;
982 struct drm_crtc *crtc;
983 int ret;
984
985 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
986 if (!tilcdc_crtc)
987 return -ENOMEM;
988
989 init_completion(&tilcdc_crtc->palette_loaded);
990 tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
991 TILCDC_PALETTE_SIZE,
992 &tilcdc_crtc->palette_dma_handle,
993 GFP_KERNEL | __GFP_ZERO);
994 if (!tilcdc_crtc->palette_base)
995 return -ENOMEM;
996 *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
997
998 crtc = &tilcdc_crtc->base;
999
1000 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
1001 if (ret < 0)
1002 goto fail;
1003
1004 mutex_init(&tilcdc_crtc->enable_lock);
1005
1006 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
1007
1008 spin_lock_init(&tilcdc_crtc->irq_lock);
1009 INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1010
1011 ret = drm_crtc_init_with_planes(dev, crtc,
1012 &tilcdc_crtc->primary,
1013 NULL,
1014 &tilcdc_crtc_funcs,
1015 "tilcdc crtc");
1016 if (ret < 0)
1017 goto fail;
1018
1019 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1020
1021 if (priv->is_componentized) {
1022 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);
1023 if (!crtc->port) {
1024 dev_err(dev->dev, "Port node not found in %pOF\n",
1025 dev->dev->of_node);
1026 ret = -EINVAL;
1027 goto fail;
1028 }
1029 }
1030
1031 priv->crtc = crtc;
1032 return 0;
1033
1034fail:
1035 tilcdc_crtc_destroy(crtc);
1036 return ret;
1037}
1038