LXR linux/drivers/gpu/drm/tilcdc/tilcdc

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2012 Texas Instruments
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 */
   6
   7#ifndef __TILCDC_DRV_H__
   8#define __TILCDC_DRV_H__
   9
  10#include <linux/clk.h>
  11#include <linux/cpufreq.h>
  12#include <linux/module.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm.h>
  15#include <linux/pm_runtime.h>
  16#include <linux/slab.h>
  17#include <linux/of.h>
  18#include <linux/of_device.h>
  19#include <linux/list.h>
  20
  21#include <drm/drmP.h>
  22#include <drm/drm_bridge.h>
  23#include <drm/drm_fb_cma_helper.h>
  24#include <drm/drm_gem_cma_helper.h>
  25
  26/* Defaulting to pixel clock defined on AM335x */
  27#define TILCDC_DEFAULT_MAX_PIXELCLOCK  126000
  28/* Defaulting to max width as defined on AM335x */
  29#define TILCDC_DEFAULT_MAX_WIDTH  2048
  30/*
  31 * This may need some tweaking, but want to allow at least 1280x1024@60
  32 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
  33 * be supportable
  34 */
  35#define TILCDC_DEFAULT_MAX_BANDWIDTH  (1280*1024*60)
  36
  37
  38struct tilcdc_drm_private {
  39        void __iomem *mmio;
  40
  41        struct clk *clk;         /* functional clock */
  42        int rev;                 /* IP revision */
  43
  44        /* don't attempt resolutions w/ higher W * H * Hz: */
  45        uint32_t max_bandwidth;
  46        /*
  47         * Pixel Clock will be restricted to some value as
  48         * defined in the device datasheet measured in KHz
  49         */
  50        uint32_t max_pixelclock;
  51        /*
  52         * Max allowable width is limited on a per device basis
  53         * measured in pixels
  54         */
  55        uint32_t max_width;
  56
  57        /* Supported pixel formats */
  58        const uint32_t *pixelformats;
  59        uint32_t num_pixelformats;
  60
  61#ifdef CONFIG_CPU_FREQ
  62        struct notifier_block freq_transition;
  63#endif
  64
  65        struct workqueue_struct *wq;
  66
  67        struct drm_crtc *crtc;
  68
  69        unsigned int num_encoders;
  70        struct drm_encoder *encoders[8];
  71
  72        unsigned int num_connectors;
  73        struct drm_connector *connectors[8];
  74
  75        struct drm_encoder *external_encoder;
  76        struct drm_connector *external_connector;
  77        const struct drm_connector_helper_funcs *connector_funcs;
  78
  79        bool is_registered;
  80        bool is_componentized;
  81};
  82
  83/* Sub-module for display.  Since we don't know at compile time what panels
  84 * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
  85 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
  86 * separate drivers.  If they are probed and found to be present, they
  87 * register themselves with tilcdc_register_module().
  88 */
  89struct tilcdc_module;
  90
  91struct tilcdc_module_ops {
  92        /* create appropriate encoders/connectors: */
  93        int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
  94#ifdef CONFIG_DEBUG_FS
  95        /* create debugfs nodes (can be NULL): */
  96        int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
  97#endif
  98};
  99
 100struct tilcdc_module {
 101        const char *name;
 102        struct list_head list;
 103        const struct tilcdc_module_ops *funcs;
 104};
 105
 106void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
 107                const struct tilcdc_module_ops *funcs);
 108void tilcdc_module_cleanup(struct tilcdc_module *mod);
 109
 110/* Panel config that needs to be set in the crtc, but is not coming from
 111 * the mode timings.  The display module is expected to call
 112 * tilcdc_crtc_set_panel_info() to set this during modeset.
 113 */
 114struct tilcdc_panel_info {
 115
 116        /* AC Bias Pin Frequency */
 117        uint32_t ac_bias;
 118
 119        /* AC Bias Pin Transitions per Interrupt */
 120        uint32_t ac_bias_intrpt;
 121
 122        /* DMA burst size */
 123        uint32_t dma_burst_sz;
 124
 125        /* Bits per pixel */
 126        uint32_t bpp;
 127
 128        /* FIFO DMA Request Delay */
 129        uint32_t fdd;
 130
 131        /* TFT Alternative Signal Mapping (Only for active) */
 132        bool tft_alt_mode;
 133
 134        /* Invert pixel clock */
 135        bool invert_pxl_clk;
 136
 137        /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
 138        uint32_t sync_edge;
 139
 140        /* Horizontal and Vertical Sync: Control: 0=ignore */
 141        uint32_t sync_ctrl;
 142
 143        /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
 144        uint32_t raster_order;
 145
 146        /* DMA FIFO threshold */
 147        uint32_t fifo_th;
 148};
 149
 150#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 151
 152int tilcdc_crtc_create(struct drm_device *dev);
 153irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
 154void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
 155void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 156                const struct tilcdc_panel_info *info);
 157void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 158                                        bool simulate_vesa_sync);
 159int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
 160int tilcdc_crtc_max_width(struct drm_crtc *crtc);
 161void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
 162int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 163                struct drm_framebuffer *fb,
 164                struct drm_pending_vblank_event *event);
 165
 166int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
 167
 168#endif /* __TILCDC_DRV_H__ */
 169