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32#include <drm/drm_atomic.h>
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_atomic_uapi.h>
35#include <drm/drm_print.h>
36#include <drm/drm_probe_helper.h>
37#include <linux/clk.h>
38#include <drm/drm_fb_cma_helper.h>
39#include <linux/component.h>
40#include <linux/of_device.h>
41#include "vc4_drv.h"
42#include "vc4_regs.h"
43
44struct vc4_crtc_state {
45 struct drm_crtc_state base;
46
47 struct drm_mm_node mm;
48 bool feed_txp;
49 bool txp_armed;
50
51 struct {
52 unsigned int left;
53 unsigned int right;
54 unsigned int top;
55 unsigned int bottom;
56 } margins;
57};
58
59static inline struct vc4_crtc_state *
60to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
61{
62 return (struct vc4_crtc_state *)crtc_state;
63}
64
65#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
66#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
67
68static const struct debugfs_reg32 crtc_regs[] = {
69 VC4_REG32(PV_CONTROL),
70 VC4_REG32(PV_V_CONTROL),
71 VC4_REG32(PV_VSYNCD_EVEN),
72 VC4_REG32(PV_HORZA),
73 VC4_REG32(PV_HORZB),
74 VC4_REG32(PV_VERTA),
75 VC4_REG32(PV_VERTB),
76 VC4_REG32(PV_VERTA_EVEN),
77 VC4_REG32(PV_VERTB_EVEN),
78 VC4_REG32(PV_INTEN),
79 VC4_REG32(PV_INTSTAT),
80 VC4_REG32(PV_STAT),
81 VC4_REG32(PV_HACT_ACT),
82};
83
84bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
85 bool in_vblank_irq, int *vpos, int *hpos,
86 ktime_t *stime, ktime_t *etime,
87 const struct drm_display_mode *mode)
88{
89 struct vc4_dev *vc4 = to_vc4_dev(dev);
90 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
91 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
92 u32 val;
93 int fifo_lines;
94 int vblank_lines;
95 bool ret = false;
96
97
98
99
100 if (stime)
101 *stime = ktime_get();
102
103
104
105
106
107 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
108
109
110 if (etime)
111 *etime = ktime_get();
112
113
114
115
116 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
117 *hpos = 0;
118
119 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
120 *vpos /= 2;
121
122
123 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
124 *hpos += mode->crtc_htotal / 2;
125 }
126
127
128 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
129
130 if (fifo_lines > 0)
131 ret = true;
132
133
134 if (*vpos > fifo_lines) {
135
136
137
138
139
140
141
142
143
144
145
146
147 *vpos -= fifo_lines + 1;
148
149 return ret;
150 }
151
152
153
154
155
156
157
158
159
160
161 vblank_lines = mode->vtotal - mode->vdisplay;
162
163 if (in_vblank_irq) {
164
165
166
167
168
169
170
171
172
173 *vpos = -vblank_lines;
174
175 if (stime)
176 *stime = vc4_crtc->t_vblank;
177 if (etime)
178 *etime = vc4_crtc->t_vblank;
179
180
181
182
183
184
185
186
187
188
189 } else {
190
191
192
193
194
195
196 *vpos = 0;
197 }
198
199 return ret;
200}
201
202static void vc4_crtc_destroy(struct drm_crtc *crtc)
203{
204 drm_crtc_cleanup(crtc);
205}
206
207static void
208vc4_crtc_lut_load(struct drm_crtc *crtc)
209{
210 struct drm_device *dev = crtc->dev;
211 struct vc4_dev *vc4 = to_vc4_dev(dev);
212 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
213 u32 i;
214
215
216
217
218
219 HVS_WRITE(SCALER_GAMADDR,
220 SCALER_GAMADDR_AUTOINC |
221 (vc4_crtc->channel * 3 * crtc->gamma_size));
222
223 for (i = 0; i < crtc->gamma_size; i++)
224 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
225 for (i = 0; i < crtc->gamma_size; i++)
226 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
227 for (i = 0; i < crtc->gamma_size; i++)
228 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
229}
230
231static void
232vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
233{
234 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
235 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
236 u32 length = drm_color_lut_size(crtc->state->gamma_lut);
237 u32 i;
238
239 for (i = 0; i < length; i++) {
240 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
241 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
242 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
243 }
244
245 vc4_crtc_lut_load(crtc);
246}
247
248static u32 vc4_get_fifo_full_level(u32 format)
249{
250 static const u32 fifo_len_bytes = 64;
251 static const u32 hvs_latency_pix = 6;
252
253 switch (format) {
254 case PV_CONTROL_FORMAT_DSIV_16:
255 case PV_CONTROL_FORMAT_DSIC_16:
256 return fifo_len_bytes - 2 * hvs_latency_pix;
257 case PV_CONTROL_FORMAT_DSIV_18:
258 return fifo_len_bytes - 14;
259 case PV_CONTROL_FORMAT_24:
260 case PV_CONTROL_FORMAT_DSIV_24:
261 default:
262 return fifo_len_bytes - 3 * hvs_latency_pix;
263 }
264}
265
266
267
268
269
270
271
272
273static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
274{
275 struct drm_connector *connector;
276 struct drm_connector_list_iter conn_iter;
277
278 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
279 drm_for_each_connector_iter(connector, &conn_iter) {
280 if (connector->state->crtc == crtc) {
281 drm_connector_list_iter_end(&conn_iter);
282 return connector->encoder;
283 }
284 }
285 drm_connector_list_iter_end(&conn_iter);
286
287 return NULL;
288}
289
290static void vc4_crtc_config_pv(struct drm_crtc *crtc)
291{
292 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
293 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
294 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
295 struct drm_crtc_state *state = crtc->state;
296 struct drm_display_mode *mode = &state->adjusted_mode;
297 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
298 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
299 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
300 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
301 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
302
303
304 CRTC_WRITE(PV_CONTROL, 0);
305 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
306 CRTC_WRITE(PV_CONTROL, 0);
307
308 CRTC_WRITE(PV_HORZA,
309 VC4_SET_FIELD((mode->htotal -
310 mode->hsync_end) * pixel_rep,
311 PV_HORZA_HBP) |
312 VC4_SET_FIELD((mode->hsync_end -
313 mode->hsync_start) * pixel_rep,
314 PV_HORZA_HSYNC));
315 CRTC_WRITE(PV_HORZB,
316 VC4_SET_FIELD((mode->hsync_start -
317 mode->hdisplay) * pixel_rep,
318 PV_HORZB_HFP) |
319 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
320
321 CRTC_WRITE(PV_VERTA,
322 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
323 PV_VERTA_VBP) |
324 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
325 PV_VERTA_VSYNC));
326 CRTC_WRITE(PV_VERTB,
327 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
328 PV_VERTB_VFP) |
329 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
330
331 if (interlace) {
332 CRTC_WRITE(PV_VERTA_EVEN,
333 VC4_SET_FIELD(mode->crtc_vtotal -
334 mode->crtc_vsync_end - 1,
335 PV_VERTA_VBP) |
336 VC4_SET_FIELD(mode->crtc_vsync_end -
337 mode->crtc_vsync_start,
338 PV_VERTA_VSYNC));
339 CRTC_WRITE(PV_VERTB_EVEN,
340 VC4_SET_FIELD(mode->crtc_vsync_start -
341 mode->crtc_vdisplay,
342 PV_VERTB_VFP) |
343 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
344
345
346
347
348
349
350 CRTC_WRITE(PV_V_CONTROL,
351 PV_VCONTROL_CONTINUOUS |
352 (is_dsi ? PV_VCONTROL_DSI : 0) |
353 PV_VCONTROL_INTERLACE |
354 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
355 PV_VCONTROL_ODD_DELAY));
356 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
357 } else {
358 CRTC_WRITE(PV_V_CONTROL,
359 PV_VCONTROL_CONTINUOUS |
360 (is_dsi ? PV_VCONTROL_DSI : 0));
361 }
362
363 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
364
365 CRTC_WRITE(PV_CONTROL,
366 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
367 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
368 PV_CONTROL_FIFO_LEVEL) |
369 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
370 PV_CONTROL_CLR_AT_START |
371 PV_CONTROL_TRIGGER_UNDERFLOW |
372 PV_CONTROL_WAIT_HSTART |
373 VC4_SET_FIELD(vc4_encoder->clock_select,
374 PV_CONTROL_CLK_SELECT) |
375 PV_CONTROL_FIFO_CLR |
376 PV_CONTROL_EN);
377}
378
379static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
380{
381 struct drm_device *dev = crtc->dev;
382 struct vc4_dev *vc4 = to_vc4_dev(dev);
383 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
384 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
385 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
386 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
387 bool debug_dump_regs = false;
388
389 if (debug_dump_regs) {
390 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
391 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
392 drm_crtc_index(crtc));
393 drm_print_regset32(&p, &vc4_crtc->regset);
394 }
395
396 if (vc4_crtc->channel == 2) {
397 u32 dispctrl;
398 u32 dsp3_mux;
399
400
401
402
403
404
405
406
407
408
409
410 if (vc4_state->feed_txp)
411 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
412 else
413 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
414
415 dispctrl = HVS_READ(SCALER_DISPCTRL) &
416 ~SCALER_DISPCTRL_DSP3_MUX_MASK;
417 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
418 }
419
420 if (!vc4_state->feed_txp)
421 vc4_crtc_config_pv(crtc);
422
423 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
424 SCALER_DISPBKGND_AUTOHS |
425 SCALER_DISPBKGND_GAMMA |
426 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
427
428
429
430
431 vc4_crtc_lut_load(crtc);
432
433 if (debug_dump_regs) {
434 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
435 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
436 drm_crtc_index(crtc));
437 drm_print_regset32(&p, &vc4_crtc->regset);
438 }
439}
440
441static void require_hvs_enabled(struct drm_device *dev)
442{
443 struct vc4_dev *vc4 = to_vc4_dev(dev);
444
445 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
446 SCALER_DISPCTRL_ENABLE);
447}
448
449static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
450 struct drm_crtc_state *old_state)
451{
452 struct drm_device *dev = crtc->dev;
453 struct vc4_dev *vc4 = to_vc4_dev(dev);
454 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
455 u32 chan = vc4_crtc->channel;
456 int ret;
457 require_hvs_enabled(dev);
458
459
460 drm_crtc_vblank_off(crtc);
461
462 CRTC_WRITE(PV_V_CONTROL,
463 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
464 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
465 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
466
467 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
468 SCALER_DISPCTRLX_ENABLE) {
469 HVS_WRITE(SCALER_DISPCTRLX(chan),
470 SCALER_DISPCTRLX_RESET);
471
472
473
474
475 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
476 }
477
478
479
480 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
481
482 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
483 SCALER_DISPSTATX_MODE) !=
484 SCALER_DISPSTATX_MODE_DISABLED);
485
486 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
487 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
488 SCALER_DISPSTATX_EMPTY);
489
490
491
492
493
494 if (crtc->state->event) {
495 unsigned long flags;
496
497 spin_lock_irqsave(&dev->event_lock, flags);
498 drm_crtc_send_vblank_event(crtc, crtc->state->event);
499 crtc->state->event = NULL;
500 spin_unlock_irqrestore(&dev->event_lock, flags);
501 }
502}
503
504void vc4_crtc_txp_armed(struct drm_crtc_state *state)
505{
506 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
507
508 vc4_state->txp_armed = true;
509}
510
511static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
512{
513 struct drm_device *dev = crtc->dev;
514 struct vc4_dev *vc4 = to_vc4_dev(dev);
515 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
516 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
517
518 if (crtc->state->event) {
519 unsigned long flags;
520
521 crtc->state->event->pipe = drm_crtc_index(crtc);
522
523 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
524
525 spin_lock_irqsave(&dev->event_lock, flags);
526
527 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
528 vc4_crtc->event = crtc->state->event;
529 crtc->state->event = NULL;
530 }
531
532 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
533 vc4_state->mm.start);
534
535 spin_unlock_irqrestore(&dev->event_lock, flags);
536 } else {
537 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
538 vc4_state->mm.start);
539 }
540}
541
542static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
543 struct drm_crtc_state *old_state)
544{
545 struct drm_device *dev = crtc->dev;
546 struct vc4_dev *vc4 = to_vc4_dev(dev);
547 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
548 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
549 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
550
551 require_hvs_enabled(dev);
552
553
554
555
556 drm_crtc_vblank_on(crtc);
557 vc4_crtc_update_dlist(crtc);
558
559
560
561
562
563
564 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
565 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
566 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
567 SCALER_DISPCTRLX_ENABLE |
568 (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
569
570
571
572
573 if (!vc4_state->feed_txp)
574 CRTC_WRITE(PV_V_CONTROL,
575 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
576}
577
578static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
579 const struct drm_display_mode *mode)
580{
581
582 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
583 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
584 crtc->base.id);
585 return MODE_NO_DBLESCAN;
586 }
587
588 return MODE_OK;
589}
590
591void vc4_crtc_get_margins(struct drm_crtc_state *state,
592 unsigned int *left, unsigned int *right,
593 unsigned int *top, unsigned int *bottom)
594{
595 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
596 struct drm_connector_state *conn_state;
597 struct drm_connector *conn;
598 int i;
599
600 *left = vc4_state->margins.left;
601 *right = vc4_state->margins.right;
602 *top = vc4_state->margins.top;
603 *bottom = vc4_state->margins.bottom;
604
605
606
607
608
609
610 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
611 if (conn_state->crtc != state->crtc)
612 continue;
613
614 *left = conn_state->tv.margins.left;
615 *right = conn_state->tv.margins.right;
616 *top = conn_state->tv.margins.top;
617 *bottom = conn_state->tv.margins.bottom;
618 break;
619 }
620}
621
622static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
623 struct drm_crtc_state *state)
624{
625 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
626 struct drm_device *dev = crtc->dev;
627 struct vc4_dev *vc4 = to_vc4_dev(dev);
628 struct drm_plane *plane;
629 unsigned long flags;
630 const struct drm_plane_state *plane_state;
631 struct drm_connector *conn;
632 struct drm_connector_state *conn_state;
633 u32 dlist_count = 0;
634 int ret, i;
635
636
637
638
639 if (hweight32(state->connector_mask) > 1)
640 return -EINVAL;
641
642 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
643 dlist_count += vc4_plane_dlist_size(plane_state);
644
645 dlist_count++;
646
647 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
648 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
649 dlist_count);
650 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
651 if (ret)
652 return ret;
653
654 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
655 if (conn_state->crtc != crtc)
656 continue;
657
658
659
660
661 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
662 state->no_vblank = true;
663 vc4_state->feed_txp = true;
664 } else {
665 state->no_vblank = false;
666 vc4_state->feed_txp = false;
667 }
668
669 vc4_state->margins.left = conn_state->tv.margins.left;
670 vc4_state->margins.right = conn_state->tv.margins.right;
671 vc4_state->margins.top = conn_state->tv.margins.top;
672 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
673 break;
674 }
675
676 return 0;
677}
678
679static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
680 struct drm_crtc_state *old_state)
681{
682 struct drm_device *dev = crtc->dev;
683 struct vc4_dev *vc4 = to_vc4_dev(dev);
684 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
685 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
686 struct drm_plane *plane;
687 struct vc4_plane_state *vc4_plane_state;
688 bool debug_dump_regs = false;
689 bool enable_bg_fill = false;
690 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
691 u32 __iomem *dlist_next = dlist_start;
692
693 if (debug_dump_regs) {
694 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
695 vc4_hvs_dump_state(dev);
696 }
697
698
699 drm_atomic_crtc_for_each_plane(plane, crtc) {
700
701 if (dlist_next == dlist_start) {
702
703
704
705
706
707
708
709
710 vc4_plane_state = to_vc4_plane_state(plane->state);
711 enable_bg_fill = vc4_plane_state->needs_bg_fill;
712 }
713
714 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
715 }
716
717 writel(SCALER_CTL0_END, dlist_next);
718 dlist_next++;
719
720 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
721
722 if (enable_bg_fill)
723
724
725
726 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
727 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
728 SCALER_DISPBKGND_FILL);
729
730
731
732
733
734
735
736
737 if (crtc->state->active && old_state->active)
738 vc4_crtc_update_dlist(crtc);
739
740 if (crtc->state->color_mgmt_changed) {
741 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
742
743 if (crtc->state->gamma_lut) {
744 vc4_crtc_update_gamma_lut(crtc);
745 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
746 } else {
747
748
749
750
751 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
752 }
753 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
754 }
755
756 if (debug_dump_regs) {
757 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
758 vc4_hvs_dump_state(dev);
759 }
760}
761
762static int vc4_enable_vblank(struct drm_crtc *crtc)
763{
764 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
765
766 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
767
768 return 0;
769}
770
771static void vc4_disable_vblank(struct drm_crtc *crtc)
772{
773 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
774
775 CRTC_WRITE(PV_INTEN, 0);
776}
777
778static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
779{
780 struct drm_crtc *crtc = &vc4_crtc->base;
781 struct drm_device *dev = crtc->dev;
782 struct vc4_dev *vc4 = to_vc4_dev(dev);
783 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
784 u32 chan = vc4_crtc->channel;
785 unsigned long flags;
786
787 spin_lock_irqsave(&dev->event_lock, flags);
788 if (vc4_crtc->event &&
789 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
790 vc4_state->feed_txp)) {
791 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
792 vc4_crtc->event = NULL;
793 drm_crtc_vblank_put(crtc);
794
795
796
797
798
799
800
801 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
802 }
803 spin_unlock_irqrestore(&dev->event_lock, flags);
804}
805
806void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
807{
808 crtc->t_vblank = ktime_get();
809 drm_crtc_handle_vblank(&crtc->base);
810 vc4_crtc_handle_page_flip(crtc);
811}
812
813static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
814{
815 struct vc4_crtc *vc4_crtc = data;
816 u32 stat = CRTC_READ(PV_INTSTAT);
817 irqreturn_t ret = IRQ_NONE;
818
819 if (stat & PV_INT_VFP_START) {
820 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
821 vc4_crtc_handle_vblank(vc4_crtc);
822 ret = IRQ_HANDLED;
823 }
824
825 return ret;
826}
827
828struct vc4_async_flip_state {
829 struct drm_crtc *crtc;
830 struct drm_framebuffer *fb;
831 struct drm_framebuffer *old_fb;
832 struct drm_pending_vblank_event *event;
833
834 struct vc4_seqno_cb cb;
835};
836
837
838
839
840static void
841vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
842{
843 struct vc4_async_flip_state *flip_state =
844 container_of(cb, struct vc4_async_flip_state, cb);
845 struct drm_crtc *crtc = flip_state->crtc;
846 struct drm_device *dev = crtc->dev;
847 struct vc4_dev *vc4 = to_vc4_dev(dev);
848 struct drm_plane *plane = crtc->primary;
849
850 vc4_plane_async_set_fb(plane, flip_state->fb);
851 if (flip_state->event) {
852 unsigned long flags;
853
854 spin_lock_irqsave(&dev->event_lock, flags);
855 drm_crtc_send_vblank_event(crtc, flip_state->event);
856 spin_unlock_irqrestore(&dev->event_lock, flags);
857 }
858
859 drm_crtc_vblank_put(crtc);
860 drm_framebuffer_put(flip_state->fb);
861
862
863
864
865
866
867
868 if (flip_state->old_fb) {
869 struct drm_gem_cma_object *cma_bo;
870 struct vc4_bo *bo;
871
872 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
873 bo = to_vc4_bo(&cma_bo->base);
874 vc4_bo_dec_usecnt(bo);
875 drm_framebuffer_put(flip_state->old_fb);
876 }
877
878 kfree(flip_state);
879
880 up(&vc4->async_modeset);
881}
882
883
884
885
886
887
888
889static int vc4_async_page_flip(struct drm_crtc *crtc,
890 struct drm_framebuffer *fb,
891 struct drm_pending_vblank_event *event,
892 uint32_t flags)
893{
894 struct drm_device *dev = crtc->dev;
895 struct vc4_dev *vc4 = to_vc4_dev(dev);
896 struct drm_plane *plane = crtc->primary;
897 int ret = 0;
898 struct vc4_async_flip_state *flip_state;
899 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
900 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
901
902
903
904
905
906
907
908
909 ret = vc4_bo_inc_usecnt(bo);
910 if (ret)
911 return ret;
912
913 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
914 if (!flip_state) {
915 vc4_bo_dec_usecnt(bo);
916 return -ENOMEM;
917 }
918
919 drm_framebuffer_get(fb);
920 flip_state->fb = fb;
921 flip_state->crtc = crtc;
922 flip_state->event = event;
923
924
925 ret = down_interruptible(&vc4->async_modeset);
926 if (ret) {
927 drm_framebuffer_put(fb);
928 vc4_bo_dec_usecnt(bo);
929 kfree(flip_state);
930 return ret;
931 }
932
933
934
935
936
937
938
939
940
941 flip_state->old_fb = plane->state->fb;
942 if (flip_state->old_fb)
943 drm_framebuffer_get(flip_state->old_fb);
944
945 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
946
947
948
949
950
951 drm_atomic_set_fb_for_plane(plane->state, fb);
952
953 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
954 vc4_async_page_flip_complete);
955
956
957 return 0;
958}
959
960static int vc4_page_flip(struct drm_crtc *crtc,
961 struct drm_framebuffer *fb,
962 struct drm_pending_vblank_event *event,
963 uint32_t flags,
964 struct drm_modeset_acquire_ctx *ctx)
965{
966 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
967 return vc4_async_page_flip(crtc, fb, event, flags);
968 else
969 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
970}
971
972static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
973{
974 struct vc4_crtc_state *vc4_state, *old_vc4_state;
975
976 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
977 if (!vc4_state)
978 return NULL;
979
980 old_vc4_state = to_vc4_crtc_state(crtc->state);
981 vc4_state->feed_txp = old_vc4_state->feed_txp;
982 vc4_state->margins = old_vc4_state->margins;
983
984 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
985 return &vc4_state->base;
986}
987
988static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
989 struct drm_crtc_state *state)
990{
991 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
992 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
993
994 if (vc4_state->mm.allocated) {
995 unsigned long flags;
996
997 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
998 drm_mm_remove_node(&vc4_state->mm);
999 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1000
1001 }
1002
1003 drm_atomic_helper_crtc_destroy_state(crtc, state);
1004}
1005
1006static void
1007vc4_crtc_reset(struct drm_crtc *crtc)
1008{
1009 if (crtc->state)
1010 vc4_crtc_destroy_state(crtc, crtc->state);
1011
1012 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1013 if (crtc->state)
1014 crtc->state->crtc = crtc;
1015}
1016
1017static const struct drm_crtc_funcs vc4_crtc_funcs = {
1018 .set_config = drm_atomic_helper_set_config,
1019 .destroy = vc4_crtc_destroy,
1020 .page_flip = vc4_page_flip,
1021 .set_property = NULL,
1022 .cursor_set = NULL,
1023 .cursor_move = NULL,
1024 .reset = vc4_crtc_reset,
1025 .atomic_duplicate_state = vc4_crtc_duplicate_state,
1026 .atomic_destroy_state = vc4_crtc_destroy_state,
1027 .gamma_set = drm_atomic_helper_legacy_gamma_set,
1028 .enable_vblank = vc4_enable_vblank,
1029 .disable_vblank = vc4_disable_vblank,
1030};
1031
1032static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1033 .mode_set_nofb = vc4_crtc_mode_set_nofb,
1034 .mode_valid = vc4_crtc_mode_valid,
1035 .atomic_check = vc4_crtc_atomic_check,
1036 .atomic_flush = vc4_crtc_atomic_flush,
1037 .atomic_enable = vc4_crtc_atomic_enable,
1038 .atomic_disable = vc4_crtc_atomic_disable,
1039};
1040
1041static const struct vc4_crtc_data pv0_data = {
1042 .hvs_channel = 0,
1043 .debugfs_name = "crtc0_regs",
1044 .encoder_types = {
1045 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1046 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1047 },
1048};
1049
1050static const struct vc4_crtc_data pv1_data = {
1051 .hvs_channel = 2,
1052 .debugfs_name = "crtc1_regs",
1053 .encoder_types = {
1054 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1055 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1056 },
1057};
1058
1059static const struct vc4_crtc_data pv2_data = {
1060 .hvs_channel = 1,
1061 .debugfs_name = "crtc2_regs",
1062 .encoder_types = {
1063 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1064 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1065 },
1066};
1067
1068static const struct of_device_id vc4_crtc_dt_match[] = {
1069 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1070 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1071 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1072 {}
1073};
1074
1075static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1076 struct drm_crtc *crtc)
1077{
1078 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1079 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1080 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1081 struct drm_encoder *encoder;
1082
1083 drm_for_each_encoder(encoder, drm) {
1084 struct vc4_encoder *vc4_encoder;
1085 int i;
1086
1087
1088 if (crtc_data->hvs_channel == 2 &&
1089 encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1090 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1091 continue;
1092 }
1093
1094 vc4_encoder = to_vc4_encoder(encoder);
1095 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1096 if (vc4_encoder->type == encoder_types[i]) {
1097 vc4_encoder->clock_select = i;
1098 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1099 break;
1100 }
1101 }
1102 }
1103}
1104
1105static void
1106vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1107{
1108 struct drm_device *drm = vc4_crtc->base.dev;
1109 struct vc4_dev *vc4 = to_vc4_dev(drm);
1110 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1111
1112
1113
1114
1115 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1116 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1117
1118 vc4_crtc->cob_size = top - base + 4;
1119}
1120
1121static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1122{
1123 struct platform_device *pdev = to_platform_device(dev);
1124 struct drm_device *drm = dev_get_drvdata(master);
1125 struct vc4_crtc *vc4_crtc;
1126 struct drm_crtc *crtc;
1127 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1128 const struct of_device_id *match;
1129 int ret, i;
1130
1131 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1132 if (!vc4_crtc)
1133 return -ENOMEM;
1134 crtc = &vc4_crtc->base;
1135
1136 match = of_match_device(vc4_crtc_dt_match, dev);
1137 if (!match)
1138 return -ENODEV;
1139 vc4_crtc->data = match->data;
1140 vc4_crtc->pdev = pdev;
1141
1142 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1143 if (IS_ERR(vc4_crtc->regs))
1144 return PTR_ERR(vc4_crtc->regs);
1145
1146 vc4_crtc->regset.base = vc4_crtc->regs;
1147 vc4_crtc->regset.regs = crtc_regs;
1148 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1149
1150
1151
1152
1153
1154
1155
1156 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1157 if (IS_ERR(primary_plane)) {
1158 dev_err(dev, "failed to construct primary plane\n");
1159 ret = PTR_ERR(primary_plane);
1160 goto err;
1161 }
1162
1163 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1164 &vc4_crtc_funcs, NULL);
1165 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1166 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1167 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1168 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1169
1170
1171
1172
1173 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184 for (i = 0; i < 8; i++) {
1185 struct drm_plane *plane =
1186 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1187
1188 if (IS_ERR(plane))
1189 continue;
1190
1191 plane->possible_crtcs = drm_crtc_mask(crtc);
1192 }
1193
1194
1195
1196
1197
1198 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1199 if (!IS_ERR(cursor_plane)) {
1200 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1201 crtc->cursor = cursor_plane;
1202 }
1203
1204 vc4_crtc_get_cob_allocation(vc4_crtc);
1205
1206 CRTC_WRITE(PV_INTEN, 0);
1207 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1208 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1209 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1210 if (ret)
1211 goto err_destroy_planes;
1212
1213 vc4_set_crtc_possible_masks(drm, crtc);
1214
1215 for (i = 0; i < crtc->gamma_size; i++) {
1216 vc4_crtc->lut_r[i] = i;
1217 vc4_crtc->lut_g[i] = i;
1218 vc4_crtc->lut_b[i] = i;
1219 }
1220
1221 platform_set_drvdata(pdev, vc4_crtc);
1222
1223 vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1224 &vc4_crtc->regset);
1225
1226 return 0;
1227
1228err_destroy_planes:
1229 list_for_each_entry_safe(destroy_plane, temp,
1230 &drm->mode_config.plane_list, head) {
1231 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1232 destroy_plane->funcs->destroy(destroy_plane);
1233 }
1234err:
1235 return ret;
1236}
1237
1238static void vc4_crtc_unbind(struct device *dev, struct device *master,
1239 void *data)
1240{
1241 struct platform_device *pdev = to_platform_device(dev);
1242 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1243
1244 vc4_crtc_destroy(&vc4_crtc->base);
1245
1246 CRTC_WRITE(PV_INTEN, 0);
1247
1248 platform_set_drvdata(pdev, NULL);
1249}
1250
1251static const struct component_ops vc4_crtc_ops = {
1252 .bind = vc4_crtc_bind,
1253 .unbind = vc4_crtc_unbind,
1254};
1255
1256static int vc4_crtc_dev_probe(struct platform_device *pdev)
1257{
1258 return component_add(&pdev->dev, &vc4_crtc_ops);
1259}
1260
1261static int vc4_crtc_dev_remove(struct platform_device *pdev)
1262{
1263 component_del(&pdev->dev, &vc4_crtc_ops);
1264 return 0;
1265}
1266
1267struct platform_driver vc4_crtc_driver = {
1268 .probe = vc4_crtc_dev_probe,
1269 .remove = vc4_crtc_dev_remove,
1270 .driver = {
1271 .name = "vc4_crtc",
1272 .of_match_table = vc4_crtc_dt_match,
1273 },
1274};
1275