1
2
3
4
5
6#include <linux/mm_types.h>
7#include <drm/drmP.h>
8#include <drm/drm_util.h>
9#include <drm/drm_encoder.h>
10#include <drm/drm_gem_cma_helper.h>
11#include <drm/drm_atomic.h>
12#include <drm/drm_syncobj.h>
13
14#include "uapi/drm/vc4_drm.h"
15
16
17
18
19enum vc4_kernel_bo_type {
20
21
22
23 VC4_BO_TYPE_KERNEL,
24 VC4_BO_TYPE_V3D,
25 VC4_BO_TYPE_V3D_SHADER,
26 VC4_BO_TYPE_DUMB,
27 VC4_BO_TYPE_BIN,
28 VC4_BO_TYPE_RCL,
29 VC4_BO_TYPE_BCL,
30 VC4_BO_TYPE_KERNEL_CACHE,
31 VC4_BO_TYPE_COUNT
32};
33
34
35
36
37
38
39
40struct vc4_perfmon {
41
42
43
44 refcount_t refcnt;
45
46
47
48
49 u8 ncounters;
50
51
52 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
53
54
55
56
57
58
59
60
61 u64 counters[0];
62};
63
64struct vc4_dev {
65 struct drm_device *dev;
66
67 struct vc4_hdmi *hdmi;
68 struct vc4_hvs *hvs;
69 struct vc4_v3d *v3d;
70 struct vc4_dpi *dpi;
71 struct vc4_dsi *dsi1;
72 struct vc4_vec *vec;
73 struct vc4_txp *txp;
74
75 struct vc4_hang_state *hang_state;
76
77
78
79
80
81 struct vc4_bo_cache {
82
83
84
85
86 struct list_head *size_list;
87 uint32_t size_list_size;
88
89
90
91
92
93 struct list_head time_list;
94 struct work_struct time_work;
95 struct timer_list time_timer;
96 } bo_cache;
97
98 u32 num_labels;
99 struct vc4_label {
100 const char *name;
101 u32 num_allocated;
102 u32 size_allocated;
103 } *bo_labels;
104
105
106 struct mutex bo_lock;
107
108
109
110
111
112 struct {
113 struct list_head list;
114 unsigned int num;
115 size_t size;
116 unsigned int purged_num;
117 size_t purged_size;
118 struct mutex lock;
119 } purgeable;
120
121 uint64_t dma_fence_context;
122
123
124
125
126 uint64_t emit_seqno;
127
128
129
130
131 uint64_t finished_seqno;
132
133
134
135
136
137 struct list_head bin_job_list;
138
139
140
141
142
143
144 struct list_head render_job_list;
145
146
147
148
149 struct list_head job_done_list;
150
151
152
153 spinlock_t job_lock;
154 wait_queue_head_t job_wait_queue;
155 struct work_struct job_done_work;
156
157
158
159
160 struct vc4_perfmon *active_perfmon;
161
162
163
164
165 struct list_head seqno_cb_list;
166
167
168
169
170
171 struct vc4_bo *bin_bo;
172
173
174 uint32_t bin_alloc_size;
175
176
177
178
179 uint32_t bin_alloc_used;
180
181
182 uint32_t bin_alloc_overflow;
183
184
185
186
187
188
189 atomic_t underrun;
190
191 struct work_struct overflow_mem_work;
192
193 int power_refcount;
194
195
196 bool load_tracker_enabled;
197
198
199 struct mutex power_lock;
200
201 struct {
202 struct timer_list timer;
203 struct work_struct reset_work;
204 } hangcheck;
205
206 struct semaphore async_modeset;
207
208 struct drm_modeset_lock ctm_state_lock;
209 struct drm_private_obj ctm_manager;
210 struct drm_private_obj load_tracker;
211
212
213
214
215 struct list_head debugfs_list;
216
217
218 struct mutex bin_bo_lock;
219
220 struct kref bin_bo_kref;
221};
222
223static inline struct vc4_dev *
224to_vc4_dev(struct drm_device *dev)
225{
226 return (struct vc4_dev *)dev->dev_private;
227}
228
229struct vc4_bo {
230 struct drm_gem_cma_object base;
231
232
233 uint64_t seqno;
234
235
236
237
238
239
240 uint64_t write_seqno;
241
242 bool t_format;
243
244
245
246
247 struct list_head unref_head;
248
249
250 unsigned long free_time;
251
252
253 struct list_head size_head;
254
255
256
257
258 struct vc4_validated_shader_info *validated_shader;
259
260
261
262
263 int label;
264
265
266
267
268
269 refcount_t usecnt;
270
271
272 u32 madv;
273 struct mutex madv_lock;
274};
275
276static inline struct vc4_bo *
277to_vc4_bo(struct drm_gem_object *bo)
278{
279 return (struct vc4_bo *)bo;
280}
281
282struct vc4_fence {
283 struct dma_fence base;
284 struct drm_device *dev;
285
286 uint64_t seqno;
287};
288
289static inline struct vc4_fence *
290to_vc4_fence(struct dma_fence *fence)
291{
292 return (struct vc4_fence *)fence;
293}
294
295struct vc4_seqno_cb {
296 struct work_struct work;
297 uint64_t seqno;
298 void (*func)(struct vc4_seqno_cb *cb);
299};
300
301struct vc4_v3d {
302 struct vc4_dev *vc4;
303 struct platform_device *pdev;
304 void __iomem *regs;
305 struct clk *clk;
306 struct debugfs_regset32 regset;
307};
308
309struct vc4_hvs {
310 struct platform_device *pdev;
311 void __iomem *regs;
312 u32 __iomem *dlist;
313
314
315
316
317 struct drm_mm dlist_mm;
318
319 struct drm_mm lbm_mm;
320 spinlock_t mm_lock;
321
322 struct drm_mm_node mitchell_netravali_filter;
323 struct debugfs_regset32 regset;
324};
325
326struct vc4_plane {
327 struct drm_plane base;
328};
329
330static inline struct vc4_plane *
331to_vc4_plane(struct drm_plane *plane)
332{
333 return (struct vc4_plane *)plane;
334}
335
336enum vc4_scaling_mode {
337 VC4_SCALING_NONE,
338 VC4_SCALING_TPZ,
339 VC4_SCALING_PPF,
340};
341
342struct vc4_plane_state {
343 struct drm_plane_state base;
344
345
346
347 u32 *dlist;
348 u32 dlist_size;
349 u32 dlist_count;
350
351
352
353
354 u32 pos0_offset;
355 u32 pos2_offset;
356 u32 ptr0_offset;
357 u32 lbm_offset;
358
359
360
361
362 u32 __iomem *hw_dlist;
363
364
365 int crtc_x, crtc_y, crtc_w, crtc_h;
366
367 u32 src_x, src_y;
368
369 u32 src_w[2], src_h[2];
370
371
372 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
373 bool is_unity;
374 bool is_yuv;
375
376
377
378
379 u32 offsets[3];
380
381
382 struct drm_mm_node lbm;
383
384
385
386
387
388 bool needs_bg_fill;
389
390
391
392
393 bool dlist_initialized;
394
395
396
397
398 u64 hvs_load;
399
400
401
402
403 u64 membus_load;
404};
405
406static inline struct vc4_plane_state *
407to_vc4_plane_state(struct drm_plane_state *state)
408{
409 return (struct vc4_plane_state *)state;
410}
411
412enum vc4_encoder_type {
413 VC4_ENCODER_TYPE_NONE,
414 VC4_ENCODER_TYPE_HDMI,
415 VC4_ENCODER_TYPE_VEC,
416 VC4_ENCODER_TYPE_DSI0,
417 VC4_ENCODER_TYPE_DSI1,
418 VC4_ENCODER_TYPE_SMI,
419 VC4_ENCODER_TYPE_DPI,
420};
421
422struct vc4_encoder {
423 struct drm_encoder base;
424 enum vc4_encoder_type type;
425 u32 clock_select;
426};
427
428static inline struct vc4_encoder *
429to_vc4_encoder(struct drm_encoder *encoder)
430{
431 return container_of(encoder, struct vc4_encoder, base);
432}
433
434struct vc4_crtc_data {
435
436 int hvs_channel;
437
438 enum vc4_encoder_type encoder_types[4];
439 const char *debugfs_name;
440};
441
442struct vc4_crtc {
443 struct drm_crtc base;
444 struct platform_device *pdev;
445 const struct vc4_crtc_data *data;
446 void __iomem *regs;
447
448
449 ktime_t t_vblank;
450
451
452 int channel;
453
454 u8 lut_r[256];
455 u8 lut_g[256];
456 u8 lut_b[256];
457
458 u32 cob_size;
459
460 struct drm_pending_vblank_event *event;
461
462 struct debugfs_regset32 regset;
463};
464
465static inline struct vc4_crtc *
466to_vc4_crtc(struct drm_crtc *crtc)
467{
468 return (struct vc4_crtc *)crtc;
469}
470
471#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
472#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
473#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
474#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
475
476#define VC4_REG32(reg) { .name = #reg, .offset = reg }
477
478struct vc4_exec_info {
479
480 uint64_t seqno;
481
482
483 uint64_t bin_dep_seqno;
484
485 struct dma_fence *fence;
486
487
488
489
490 uint32_t last_ct0ca, last_ct1ca;
491
492
493 struct drm_vc4_submit_cl *args;
494
495
496
497
498 struct drm_gem_cma_object **bo;
499 uint32_t bo_count;
500
501
502
503
504
505 struct drm_gem_cma_object *rcl_write_bo[4];
506 uint32_t rcl_write_bo_count;
507
508
509 struct list_head head;
510
511
512
513
514 struct list_head unref_list;
515
516
517
518
519 uint32_t bo_index[2];
520
521
522
523
524 struct drm_gem_cma_object *exec_bo;
525
526
527
528
529
530
531
532 struct vc4_shader_state {
533 uint32_t addr;
534
535
536
537 uint32_t max_index;
538 } *shader_state;
539
540
541 uint32_t shader_state_size;
542
543 uint32_t shader_state_count;
544
545 bool found_tile_binning_mode_config_packet;
546 bool found_start_tile_binning_packet;
547 bool found_increment_semaphore_packet;
548 bool found_flush;
549 uint8_t bin_tiles_x, bin_tiles_y;
550
551
552
553 uint32_t tile_alloc_offset;
554
555 uint32_t bin_slots;
556
557
558
559
560
561 uint32_t ct0ca, ct0ea;
562 uint32_t ct1ca, ct1ea;
563
564
565 void *bin_u;
566
567
568
569
570
571
572 void *shader_rec_u;
573 void *shader_rec_v;
574 uint32_t shader_rec_p;
575 uint32_t shader_rec_size;
576
577
578
579
580 void *uniforms_u;
581 void *uniforms_v;
582 uint32_t uniforms_p;
583 uint32_t uniforms_size;
584
585
586
587
588 struct vc4_perfmon *perfmon;
589
590
591
592
593 bool bin_bo_used;
594};
595
596
597
598
599struct vc4_file {
600 struct {
601 struct idr idr;
602 struct mutex lock;
603 } perfmon;
604
605 bool bin_bo_used;
606};
607
608static inline struct vc4_exec_info *
609vc4_first_bin_job(struct vc4_dev *vc4)
610{
611 return list_first_entry_or_null(&vc4->bin_job_list,
612 struct vc4_exec_info, head);
613}
614
615static inline struct vc4_exec_info *
616vc4_first_render_job(struct vc4_dev *vc4)
617{
618 return list_first_entry_or_null(&vc4->render_job_list,
619 struct vc4_exec_info, head);
620}
621
622static inline struct vc4_exec_info *
623vc4_last_render_job(struct vc4_dev *vc4)
624{
625 if (list_empty(&vc4->render_job_list))
626 return NULL;
627 return list_last_entry(&vc4->render_job_list,
628 struct vc4_exec_info, head);
629}
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645struct vc4_texture_sample_info {
646 bool is_direct;
647 uint32_t p_offset[4];
648};
649
650
651
652
653
654
655
656
657
658
659
660struct vc4_validated_shader_info {
661 uint32_t uniforms_size;
662 uint32_t uniforms_src_size;
663 uint32_t num_texture_samples;
664 struct vc4_texture_sample_info *texture_samples;
665
666 uint32_t num_uniform_addr_offsets;
667 uint32_t *uniform_addr_offsets;
668
669 bool is_threaded;
670};
671
672
673
674
675
676
677
678
679
680#define _wait_for(COND, MS, W) ({ \
681 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
682 int ret__ = 0; \
683 while (!(COND)) { \
684 if (time_after(jiffies, timeout__)) { \
685 if (!(COND)) \
686 ret__ = -ETIMEDOUT; \
687 break; \
688 } \
689 if (W && drm_can_sleep()) { \
690 msleep(W); \
691 } else { \
692 cpu_relax(); \
693 } \
694 } \
695 ret__; \
696})
697
698#define wait_for(COND, MS) _wait_for(COND, MS, 1)
699
700
701struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
702void vc4_free_object(struct drm_gem_object *gem_obj);
703struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
704 bool from_cache, enum vc4_kernel_bo_type type);
705int vc4_dumb_create(struct drm_file *file_priv,
706 struct drm_device *dev,
707 struct drm_mode_create_dumb *args);
708struct dma_buf *vc4_prime_export(struct drm_device *dev,
709 struct drm_gem_object *obj, int flags);
710int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
712int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *file_priv);
714int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *file_priv);
716int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
717 struct drm_file *file_priv);
718int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
719 struct drm_file *file_priv);
720int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
721 struct drm_file *file_priv);
722int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *file_priv);
724vm_fault_t vc4_fault(struct vm_fault *vmf);
725int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
726int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
727struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
728 struct dma_buf_attachment *attach,
729 struct sg_table *sgt);
730void *vc4_prime_vmap(struct drm_gem_object *obj);
731int vc4_bo_cache_init(struct drm_device *dev);
732void vc4_bo_cache_destroy(struct drm_device *dev);
733int vc4_bo_inc_usecnt(struct vc4_bo *bo);
734void vc4_bo_dec_usecnt(struct vc4_bo *bo);
735void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
736void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
737
738
739extern struct platform_driver vc4_crtc_driver;
740bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
741 bool in_vblank_irq, int *vpos, int *hpos,
742 ktime_t *stime, ktime_t *etime,
743 const struct drm_display_mode *mode);
744void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
745void vc4_crtc_txp_armed(struct drm_crtc_state *state);
746void vc4_crtc_get_margins(struct drm_crtc_state *state,
747 unsigned int *right, unsigned int *left,
748 unsigned int *top, unsigned int *bottom);
749
750
751int vc4_debugfs_init(struct drm_minor *minor);
752#ifdef CONFIG_DEBUG_FS
753void vc4_debugfs_add_file(struct drm_device *drm,
754 const char *filename,
755 int (*show)(struct seq_file*, void*),
756 void *data);
757void vc4_debugfs_add_regset32(struct drm_device *drm,
758 const char *filename,
759 struct debugfs_regset32 *regset);
760#else
761static inline void vc4_debugfs_add_file(struct drm_device *drm,
762 const char *filename,
763 int (*show)(struct seq_file*, void*),
764 void *data)
765{
766}
767
768static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
769 const char *filename,
770 struct debugfs_regset32 *regset)
771{
772}
773#endif
774
775
776void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
777
778
779extern struct platform_driver vc4_dpi_driver;
780
781
782extern struct platform_driver vc4_dsi_driver;
783
784
785extern const struct dma_fence_ops vc4_fence_ops;
786
787
788void vc4_gem_init(struct drm_device *dev);
789void vc4_gem_destroy(struct drm_device *dev);
790int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
791 struct drm_file *file_priv);
792int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
793 struct drm_file *file_priv);
794int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
795 struct drm_file *file_priv);
796void vc4_submit_next_bin_job(struct drm_device *dev);
797void vc4_submit_next_render_job(struct drm_device *dev);
798void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
799int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
800 uint64_t timeout_ns, bool interruptible);
801void vc4_job_handle_completed(struct vc4_dev *vc4);
802int vc4_queue_seqno_cb(struct drm_device *dev,
803 struct vc4_seqno_cb *cb, uint64_t seqno,
804 void (*func)(struct vc4_seqno_cb *cb));
805int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
806 struct drm_file *file_priv);
807
808
809extern struct platform_driver vc4_hdmi_driver;
810
811
812extern struct platform_driver vc4_vec_driver;
813
814
815extern struct platform_driver vc4_txp_driver;
816
817
818irqreturn_t vc4_irq(int irq, void *arg);
819void vc4_irq_preinstall(struct drm_device *dev);
820int vc4_irq_postinstall(struct drm_device *dev);
821void vc4_irq_uninstall(struct drm_device *dev);
822void vc4_irq_reset(struct drm_device *dev);
823
824
825extern struct platform_driver vc4_hvs_driver;
826void vc4_hvs_dump_state(struct drm_device *dev);
827void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
828void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
829
830
831int vc4_kms_load(struct drm_device *dev);
832
833
834struct drm_plane *vc4_plane_init(struct drm_device *dev,
835 enum drm_plane_type type);
836u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
837u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
838void vc4_plane_async_set_fb(struct drm_plane *plane,
839 struct drm_framebuffer *fb);
840
841
842extern struct platform_driver vc4_v3d_driver;
843extern const struct of_device_id vc4_v3d_dt_match[];
844int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
845int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
846void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
847int vc4_v3d_pm_get(struct vc4_dev *vc4);
848void vc4_v3d_pm_put(struct vc4_dev *vc4);
849
850
851int
852vc4_validate_bin_cl(struct drm_device *dev,
853 void *validated,
854 void *unvalidated,
855 struct vc4_exec_info *exec);
856
857int
858vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
859
860struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
861 uint32_t hindex);
862
863int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
864
865bool vc4_check_tex_size(struct vc4_exec_info *exec,
866 struct drm_gem_cma_object *fbo,
867 uint32_t offset, uint8_t tiling_format,
868 uint32_t width, uint32_t height, uint8_t cpp);
869
870
871struct vc4_validated_shader_info *
872vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
873
874
875void vc4_perfmon_get(struct vc4_perfmon *perfmon);
876void vc4_perfmon_put(struct vc4_perfmon *perfmon);
877void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
878void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
879 bool capture);
880struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
881void vc4_perfmon_open_file(struct vc4_file *vc4file);
882void vc4_perfmon_close_file(struct vc4_file *vc4file);
883int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889