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27#include <linux/module.h>
28#include <linux/console.h>
29#include <linux/dma-mapping.h>
30
31#include <drm/drmP.h>
32#include "vmwgfx_drv.h"
33#include "vmwgfx_binding.h"
34#include "ttm_object.h"
35#include <drm/ttm/ttm_placement.h>
36#include <drm/ttm/ttm_bo_driver.h>
37#include <drm/ttm/ttm_module.h>
38
39#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
40#define VMWGFX_CHIP_SVGAII 0
41#define VMW_FB_RESERVATION 0
42
43#define VMW_MIN_INITIAL_WIDTH 800
44#define VMW_MIN_INITIAL_HEIGHT 600
45
46#ifndef VMWGFX_GIT_VERSION
47#define VMWGFX_GIT_VERSION "Unknown"
48#endif
49
50#define VMWGFX_REPO "In Tree"
51
52#define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
53
54
55
56
57
58
59#define DRM_IOCTL_VMW_GET_PARAM \
60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
61 struct drm_vmw_getparam_arg)
62#define DRM_IOCTL_VMW_ALLOC_DMABUF \
63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
64 union drm_vmw_alloc_dmabuf_arg)
65#define DRM_IOCTL_VMW_UNREF_DMABUF \
66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
67 struct drm_vmw_unref_dmabuf_arg)
68#define DRM_IOCTL_VMW_CURSOR_BYPASS \
69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
70 struct drm_vmw_cursor_bypass_arg)
71
72#define DRM_IOCTL_VMW_CONTROL_STREAM \
73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
74 struct drm_vmw_control_stream_arg)
75#define DRM_IOCTL_VMW_CLAIM_STREAM \
76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
77 struct drm_vmw_stream_arg)
78#define DRM_IOCTL_VMW_UNREF_STREAM \
79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
80 struct drm_vmw_stream_arg)
81
82#define DRM_IOCTL_VMW_CREATE_CONTEXT \
83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
84 struct drm_vmw_context_arg)
85#define DRM_IOCTL_VMW_UNREF_CONTEXT \
86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
87 struct drm_vmw_context_arg)
88#define DRM_IOCTL_VMW_CREATE_SURFACE \
89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
90 union drm_vmw_surface_create_arg)
91#define DRM_IOCTL_VMW_UNREF_SURFACE \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
93 struct drm_vmw_surface_arg)
94#define DRM_IOCTL_VMW_REF_SURFACE \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
96 union drm_vmw_surface_reference_arg)
97#define DRM_IOCTL_VMW_EXECBUF \
98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
99 struct drm_vmw_execbuf_arg)
100#define DRM_IOCTL_VMW_GET_3D_CAP \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
102 struct drm_vmw_get_3d_cap_arg)
103#define DRM_IOCTL_VMW_FENCE_WAIT \
104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
105 struct drm_vmw_fence_wait_arg)
106#define DRM_IOCTL_VMW_FENCE_SIGNALED \
107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
108 struct drm_vmw_fence_signaled_arg)
109#define DRM_IOCTL_VMW_FENCE_UNREF \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
111 struct drm_vmw_fence_arg)
112#define DRM_IOCTL_VMW_FENCE_EVENT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
114 struct drm_vmw_fence_event_arg)
115#define DRM_IOCTL_VMW_PRESENT \
116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
117 struct drm_vmw_present_arg)
118#define DRM_IOCTL_VMW_PRESENT_READBACK \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
120 struct drm_vmw_present_readback_arg)
121#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
123 struct drm_vmw_update_layout_arg)
124#define DRM_IOCTL_VMW_CREATE_SHADER \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
126 struct drm_vmw_shader_create_arg)
127#define DRM_IOCTL_VMW_UNREF_SHADER \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
129 struct drm_vmw_shader_arg)
130#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
132 union drm_vmw_gb_surface_create_arg)
133#define DRM_IOCTL_VMW_GB_SURFACE_REF \
134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
135 union drm_vmw_gb_surface_reference_arg)
136#define DRM_IOCTL_VMW_SYNCCPU \
137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
138 struct drm_vmw_synccpu_arg)
139#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
141 struct drm_vmw_context_arg)
142#define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
144 union drm_vmw_gb_surface_create_ext_arg)
145#define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
147 union drm_vmw_gb_surface_reference_ext_arg)
148
149
150
151
152
153
154#define VMW_IOCTL_DEF(ioctl, func, flags) \
155 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
156
157
158
159
160
161static const struct drm_ioctl_desc vmw_ioctls[] = {
162 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
163 DRM_AUTH | DRM_RENDER_ALLOW),
164 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
165 DRM_AUTH | DRM_RENDER_ALLOW),
166 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
167 DRM_RENDER_ALLOW),
168 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
169 vmw_kms_cursor_bypass_ioctl,
170 DRM_MASTER),
171
172 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
173 DRM_MASTER),
174 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
175 DRM_MASTER),
176 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
177 DRM_MASTER),
178
179 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
180 DRM_AUTH | DRM_RENDER_ALLOW),
181 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
182 DRM_RENDER_ALLOW),
183 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
184 DRM_AUTH | DRM_RENDER_ALLOW),
185 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
186 DRM_RENDER_ALLOW),
187 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
188 DRM_AUTH | DRM_RENDER_ALLOW),
189 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
190 DRM_RENDER_ALLOW),
191 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
192 DRM_RENDER_ALLOW),
193 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
194 vmw_fence_obj_signaled_ioctl,
195 DRM_RENDER_ALLOW),
196 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
197 DRM_RENDER_ALLOW),
198 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
199 DRM_AUTH | DRM_RENDER_ALLOW),
200 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
201 DRM_AUTH | DRM_RENDER_ALLOW),
202
203
204 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
205 DRM_MASTER | DRM_AUTH),
206 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
207 vmw_present_readback_ioctl,
208 DRM_MASTER | DRM_AUTH),
209
210
211
212
213
214 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
215 vmw_kms_update_layout_ioctl,
216 DRM_RENDER_ALLOW),
217 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
218 vmw_shader_define_ioctl,
219 DRM_AUTH | DRM_RENDER_ALLOW),
220 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
221 vmw_shader_destroy_ioctl,
222 DRM_RENDER_ALLOW),
223 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
224 vmw_gb_surface_define_ioctl,
225 DRM_AUTH | DRM_RENDER_ALLOW),
226 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
227 vmw_gb_surface_reference_ioctl,
228 DRM_AUTH | DRM_RENDER_ALLOW),
229 VMW_IOCTL_DEF(VMW_SYNCCPU,
230 vmw_user_bo_synccpu_ioctl,
231 DRM_RENDER_ALLOW),
232 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
233 vmw_extended_context_define_ioctl,
234 DRM_AUTH | DRM_RENDER_ALLOW),
235 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
236 vmw_gb_surface_define_ext_ioctl,
237 DRM_AUTH | DRM_RENDER_ALLOW),
238 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
239 vmw_gb_surface_reference_ext_ioctl,
240 DRM_AUTH | DRM_RENDER_ALLOW),
241};
242
243static const struct pci_device_id vmw_pci_id_list[] = {
244 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
245 {0, 0, 0}
246};
247MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
248
249static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
250static int vmw_force_iommu;
251static int vmw_restrict_iommu;
252static int vmw_force_coherent;
253static int vmw_restrict_dma_mask;
254static int vmw_assume_16bpp;
255
256static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
257static void vmw_master_init(struct vmw_master *);
258static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
259 void *ptr);
260
261MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
262module_param_named(enable_fbdev, enable_fbdev, int, 0600);
263MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
264module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
265MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
266module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
267MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
268module_param_named(force_coherent, vmw_force_coherent, int, 0600);
269MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
270module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
271MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
272module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
273
274
275static void vmw_print_capabilities2(uint32_t capabilities2)
276{
277 DRM_INFO("Capabilities2:\n");
278 if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
279 DRM_INFO(" Grow oTable.\n");
280 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
281 DRM_INFO(" IntraSurface copy.\n");
282}
283
284static void vmw_print_capabilities(uint32_t capabilities)
285{
286 DRM_INFO("Capabilities:\n");
287 if (capabilities & SVGA_CAP_RECT_COPY)
288 DRM_INFO(" Rect copy.\n");
289 if (capabilities & SVGA_CAP_CURSOR)
290 DRM_INFO(" Cursor.\n");
291 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
292 DRM_INFO(" Cursor bypass.\n");
293 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
294 DRM_INFO(" Cursor bypass 2.\n");
295 if (capabilities & SVGA_CAP_8BIT_EMULATION)
296 DRM_INFO(" 8bit emulation.\n");
297 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
298 DRM_INFO(" Alpha cursor.\n");
299 if (capabilities & SVGA_CAP_3D)
300 DRM_INFO(" 3D.\n");
301 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
302 DRM_INFO(" Extended Fifo.\n");
303 if (capabilities & SVGA_CAP_MULTIMON)
304 DRM_INFO(" Multimon.\n");
305 if (capabilities & SVGA_CAP_PITCHLOCK)
306 DRM_INFO(" Pitchlock.\n");
307 if (capabilities & SVGA_CAP_IRQMASK)
308 DRM_INFO(" Irq mask.\n");
309 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
310 DRM_INFO(" Display Topology.\n");
311 if (capabilities & SVGA_CAP_GMR)
312 DRM_INFO(" GMR.\n");
313 if (capabilities & SVGA_CAP_TRACES)
314 DRM_INFO(" Traces.\n");
315 if (capabilities & SVGA_CAP_GMR2)
316 DRM_INFO(" GMR2.\n");
317 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
318 DRM_INFO(" Screen Object 2.\n");
319 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
320 DRM_INFO(" Command Buffers.\n");
321 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
322 DRM_INFO(" Command Buffers 2.\n");
323 if (capabilities & SVGA_CAP_GBOBJECTS)
324 DRM_INFO(" Guest Backed Resources.\n");
325 if (capabilities & SVGA_CAP_DX)
326 DRM_INFO(" DX Features.\n");
327 if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
328 DRM_INFO(" HP Command Queue.\n");
329}
330
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332
333
334
335
336
337
338
339
340
341
342
343
344static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
345{
346 int ret;
347 struct vmw_buffer_object *vbo;
348 struct ttm_bo_kmap_obj map;
349 volatile SVGA3dQueryResult *result;
350 bool dummy;
351
352
353
354
355
356
357 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
358 if (!vbo)
359 return -ENOMEM;
360
361 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
362 &vmw_sys_ne_placement, false,
363 &vmw_bo_bo_free);
364 if (unlikely(ret != 0))
365 return ret;
366
367 ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
368 BUG_ON(ret != 0);
369 vmw_bo_pin_reserved(vbo, true);
370
371 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
372 if (likely(ret == 0)) {
373 result = ttm_kmap_obj_virtual(&map, &dummy);
374 result->totalSize = sizeof(*result);
375 result->state = SVGA3D_QUERYSTATE_PENDING;
376 result->result32 = 0xff;
377 ttm_bo_kunmap(&map);
378 }
379 vmw_bo_pin_reserved(vbo, false);
380 ttm_bo_unreserve(&vbo->base);
381
382 if (unlikely(ret != 0)) {
383 DRM_ERROR("Dummy query buffer map failed.\n");
384 vmw_bo_unreference(&vbo);
385 } else
386 dev_priv->dummy_query_bo = vbo;
387
388 return ret;
389}
390
391
392
393
394
395
396
397
398
399
400
401static int vmw_request_device_late(struct vmw_private *dev_priv)
402{
403 int ret;
404
405 if (dev_priv->has_mob) {
406 ret = vmw_otables_setup(dev_priv);
407 if (unlikely(ret != 0)) {
408 DRM_ERROR("Unable to initialize "
409 "guest Memory OBjects.\n");
410 return ret;
411 }
412 }
413
414 if (dev_priv->cman) {
415 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
416 256*4096, 2*4096);
417 if (ret) {
418 struct vmw_cmdbuf_man *man = dev_priv->cman;
419
420 dev_priv->cman = NULL;
421 vmw_cmdbuf_man_destroy(man);
422 }
423 }
424
425 return 0;
426}
427
428static int vmw_request_device(struct vmw_private *dev_priv)
429{
430 int ret;
431
432 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
433 if (unlikely(ret != 0)) {
434 DRM_ERROR("Unable to initialize FIFO.\n");
435 return ret;
436 }
437 vmw_fence_fifo_up(dev_priv->fman);
438 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
439 if (IS_ERR(dev_priv->cman)) {
440 dev_priv->cman = NULL;
441 dev_priv->has_dx = false;
442 }
443
444 ret = vmw_request_device_late(dev_priv);
445 if (ret)
446 goto out_no_mob;
447
448 ret = vmw_dummy_query_bo_create(dev_priv);
449 if (unlikely(ret != 0))
450 goto out_no_query_bo;
451
452 return 0;
453
454out_no_query_bo:
455 if (dev_priv->cman)
456 vmw_cmdbuf_remove_pool(dev_priv->cman);
457 if (dev_priv->has_mob) {
458 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
459 vmw_otables_takedown(dev_priv);
460 }
461 if (dev_priv->cman)
462 vmw_cmdbuf_man_destroy(dev_priv->cman);
463out_no_mob:
464 vmw_fence_fifo_down(dev_priv->fman);
465 vmw_fifo_release(dev_priv, &dev_priv->fifo);
466 return ret;
467}
468
469
470
471
472
473
474
475
476
477static void vmw_release_device_early(struct vmw_private *dev_priv)
478{
479
480
481
482
483
484 BUG_ON(dev_priv->pinned_bo != NULL);
485
486 vmw_bo_unreference(&dev_priv->dummy_query_bo);
487 if (dev_priv->cman)
488 vmw_cmdbuf_remove_pool(dev_priv->cman);
489
490 if (dev_priv->has_mob) {
491 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
492 vmw_otables_takedown(dev_priv);
493 }
494}
495
496
497
498
499
500
501
502
503
504static void vmw_release_device_late(struct vmw_private *dev_priv)
505{
506 vmw_fence_fifo_down(dev_priv->fman);
507 if (dev_priv->cman)
508 vmw_cmdbuf_man_destroy(dev_priv->cman);
509
510 vmw_fifo_release(dev_priv, &dev_priv->fifo);
511}
512
513
514
515
516
517
518
519
520
521
522static void vmw_get_initial_size(struct vmw_private *dev_priv)
523{
524 uint32_t width;
525 uint32_t height;
526
527 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
528 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
529
530 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
531 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
532
533 if (width > dev_priv->fb_max_width ||
534 height > dev_priv->fb_max_height) {
535
536
537
538
539
540 width = VMW_MIN_INITIAL_WIDTH;
541 height = VMW_MIN_INITIAL_HEIGHT;
542 }
543
544 dev_priv->initial_width = width;
545 dev_priv->initial_height = height;
546}
547
548
549
550
551
552
553
554
555
556
557
558
559
560static int vmw_dma_select_mode(struct vmw_private *dev_priv)
561{
562 static const char *names[vmw_dma_map_max] = {
563 [vmw_dma_phys] = "Using physical TTM page addresses.",
564 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
565 [vmw_dma_map_populate] = "Caching DMA mappings.",
566 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
567
568 if (vmw_force_coherent)
569 dev_priv->map_mode = vmw_dma_alloc_coherent;
570 else if (vmw_restrict_iommu)
571 dev_priv->map_mode = vmw_dma_map_bind;
572 else
573 dev_priv->map_mode = vmw_dma_map_populate;
574
575
576 if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) &&
577 (dev_priv->map_mode == vmw_dma_alloc_coherent))
578 return -EINVAL;
579
580 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
581 return 0;
582}
583
584
585
586
587
588
589
590
591
592static int vmw_dma_masks(struct vmw_private *dev_priv)
593{
594 struct drm_device *dev = dev_priv->dev;
595 int ret = 0;
596
597 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
598 if (dev_priv->map_mode != vmw_dma_phys &&
599 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
600 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
601 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
602 }
603
604 return ret;
605}
606
607static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
608{
609 struct vmw_private *dev_priv;
610 int ret;
611 uint32_t svga_id;
612 enum vmw_res_type i;
613 bool refuse_dma = false;
614 char host_log[100] = {0};
615
616 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
617 if (unlikely(!dev_priv)) {
618 DRM_ERROR("Failed allocating a device private struct.\n");
619 return -ENOMEM;
620 }
621
622 pci_set_master(dev->pdev);
623
624 dev_priv->dev = dev;
625 dev_priv->vmw_chipset = chipset;
626 dev_priv->last_read_seqno = (uint32_t) -100;
627 mutex_init(&dev_priv->cmdbuf_mutex);
628 mutex_init(&dev_priv->release_mutex);
629 mutex_init(&dev_priv->binding_mutex);
630 mutex_init(&dev_priv->global_kms_state_mutex);
631 ttm_lock_init(&dev_priv->reservation_sem);
632 spin_lock_init(&dev_priv->resource_lock);
633 spin_lock_init(&dev_priv->hw_lock);
634 spin_lock_init(&dev_priv->waiter_lock);
635 spin_lock_init(&dev_priv->cap_lock);
636 spin_lock_init(&dev_priv->svga_lock);
637 spin_lock_init(&dev_priv->cursor_lock);
638
639 for (i = vmw_res_context; i < vmw_res_max; ++i) {
640 idr_init(&dev_priv->res_idr[i]);
641 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
642 }
643
644 mutex_init(&dev_priv->init_mutex);
645 init_waitqueue_head(&dev_priv->fence_queue);
646 init_waitqueue_head(&dev_priv->fifo_queue);
647 dev_priv->fence_queue_waiters = 0;
648 dev_priv->fifo_queue_waiters = 0;
649
650 dev_priv->used_memory_size = 0;
651
652 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
653 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
654 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
655
656 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
657
658 dev_priv->enable_fb = enable_fbdev;
659
660 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
661 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
662 if (svga_id != SVGA_ID_2) {
663 ret = -ENOSYS;
664 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
665 goto out_err0;
666 }
667
668 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
669
670 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
671 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
672 }
673
674
675 ret = vmw_dma_select_mode(dev_priv);
676 if (unlikely(ret != 0)) {
677 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
678 refuse_dma = true;
679 }
680
681 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
682 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
683 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
684 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
685
686 vmw_get_initial_size(dev_priv);
687
688 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
689 dev_priv->max_gmr_ids =
690 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
691 dev_priv->max_gmr_pages =
692 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
693 dev_priv->memory_size =
694 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
695 dev_priv->memory_size -= dev_priv->vram_size;
696 } else {
697
698
699
700
701 dev_priv->memory_size = 512*1024*1024;
702 }
703 dev_priv->max_mob_pages = 0;
704 dev_priv->max_mob_size = 0;
705 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
706 uint64_t mem_size =
707 vmw_read(dev_priv,
708 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
709
710
711
712
713
714 if (!(dev_priv->capabilities & SVGA_CAP_3D))
715 mem_size *= 3;
716
717 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
718 dev_priv->prim_bb_mem =
719 vmw_read(dev_priv,
720 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
721 dev_priv->max_mob_size =
722 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
723 dev_priv->stdu_max_width =
724 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
725 dev_priv->stdu_max_height =
726 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
727
728 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
729 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
730 dev_priv->texture_max_width = vmw_read(dev_priv,
731 SVGA_REG_DEV_CAP);
732 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
733 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
734 dev_priv->texture_max_height = vmw_read(dev_priv,
735 SVGA_REG_DEV_CAP);
736 } else {
737 dev_priv->texture_max_width = 8192;
738 dev_priv->texture_max_height = 8192;
739 dev_priv->prim_bb_mem = dev_priv->vram_size;
740 }
741
742 vmw_print_capabilities(dev_priv->capabilities);
743 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
744 vmw_print_capabilities2(dev_priv->capabilities2);
745
746 ret = vmw_dma_masks(dev_priv);
747 if (unlikely(ret != 0))
748 goto out_err0;
749
750 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
751 SCATTERLIST_MAX_SEGMENT));
752
753 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
754 DRM_INFO("Max GMR ids is %u\n",
755 (unsigned)dev_priv->max_gmr_ids);
756 DRM_INFO("Max number of GMR pages is %u\n",
757 (unsigned)dev_priv->max_gmr_pages);
758 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
759 (unsigned)dev_priv->memory_size / 1024);
760 }
761 DRM_INFO("Maximum display memory size is %u kiB\n",
762 dev_priv->prim_bb_mem / 1024);
763 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
764 dev_priv->vram_start, dev_priv->vram_size / 1024);
765 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
766 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
767
768 vmw_master_init(&dev_priv->fbdev_master);
769 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
770 dev_priv->active_master = &dev_priv->fbdev_master;
771
772 dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
773 dev_priv->mmio_size, MEMREMAP_WB);
774
775 if (unlikely(dev_priv->mmio_virt == NULL)) {
776 ret = -ENOMEM;
777 DRM_ERROR("Failed mapping MMIO.\n");
778 goto out_err0;
779 }
780
781
782 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
783 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
784 !vmw_fifo_have_pitchlock(dev_priv)) {
785 ret = -ENOSYS;
786 DRM_ERROR("Hardware has no pitchlock\n");
787 goto out_err4;
788 }
789
790 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
791 &vmw_prime_dmabuf_ops);
792
793 if (unlikely(dev_priv->tdev == NULL)) {
794 DRM_ERROR("Unable to initialize TTM object management.\n");
795 ret = -ENOMEM;
796 goto out_err4;
797 }
798
799 dev->dev_private = dev_priv;
800
801 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
802 dev_priv->stealth = (ret != 0);
803 if (dev_priv->stealth) {
804
805
806
807
808 DRM_INFO("It appears like vesafb is loaded. "
809 "Ignore above error if any.\n");
810 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
811 if (unlikely(ret != 0)) {
812 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
813 goto out_no_device;
814 }
815 }
816
817 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
818 ret = vmw_irq_install(dev, dev->pdev->irq);
819 if (ret != 0) {
820 DRM_ERROR("Failed installing irq: %d\n", ret);
821 goto out_no_irq;
822 }
823 }
824
825 dev_priv->fman = vmw_fence_manager_init(dev_priv);
826 if (unlikely(dev_priv->fman == NULL)) {
827 ret = -ENOMEM;
828 goto out_no_fman;
829 }
830
831 ret = ttm_bo_device_init(&dev_priv->bdev,
832 &vmw_bo_driver,
833 dev->anon_inode->i_mapping,
834 false);
835 if (unlikely(ret != 0)) {
836 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
837 goto out_no_bdev;
838 }
839
840
841
842
843
844 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
845 (dev_priv->vram_size >> PAGE_SHIFT));
846 if (unlikely(ret != 0)) {
847 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
848 goto out_no_vram;
849 }
850 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
851
852 dev_priv->has_gmr = true;
853 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
854 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
855 VMW_PL_GMR) != 0) {
856 DRM_INFO("No GMR memory available. "
857 "Graphics memory resources are very limited.\n");
858 dev_priv->has_gmr = false;
859 }
860
861 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
862 dev_priv->has_mob = true;
863 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
864 VMW_PL_MOB) != 0) {
865 DRM_INFO("No MOB memory available. "
866 "3D will be disabled.\n");
867 dev_priv->has_mob = false;
868 }
869 }
870
871 if (dev_priv->has_mob) {
872 spin_lock(&dev_priv->cap_lock);
873 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
874 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
875 spin_unlock(&dev_priv->cap_lock);
876 }
877
878 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
879 ret = vmw_kms_init(dev_priv);
880 if (unlikely(ret != 0))
881 goto out_no_kms;
882 vmw_overlay_init(dev_priv);
883
884 ret = vmw_request_device(dev_priv);
885 if (ret)
886 goto out_no_fifo;
887
888 if (dev_priv->has_dx) {
889
890
891
892
893 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) {
894 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
895 SVGA3D_DEVCAP_SM41);
896 dev_priv->has_sm4_1 = vmw_read(dev_priv,
897 SVGA_REG_DEV_CAP);
898 }
899 }
900
901 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
902 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
903 ? "yes." : "no.");
904 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no.");
905
906 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
907 VMWGFX_REPO, VMWGFX_GIT_VERSION);
908 vmw_host_log(host_log);
909
910 memset(host_log, 0, sizeof(host_log));
911 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
912 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
913 VMWGFX_DRIVER_PATCHLEVEL);
914 vmw_host_log(host_log);
915
916 if (dev_priv->enable_fb) {
917 vmw_fifo_resource_inc(dev_priv);
918 vmw_svga_enable(dev_priv);
919 vmw_fb_init(dev_priv);
920 }
921
922 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
923 register_pm_notifier(&dev_priv->pm_nb);
924
925 return 0;
926
927out_no_fifo:
928 vmw_overlay_close(dev_priv);
929 vmw_kms_close(dev_priv);
930out_no_kms:
931 if (dev_priv->has_mob)
932 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
933 if (dev_priv->has_gmr)
934 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
935 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
936out_no_vram:
937 (void)ttm_bo_device_release(&dev_priv->bdev);
938out_no_bdev:
939 vmw_fence_manager_takedown(dev_priv->fman);
940out_no_fman:
941 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
942 vmw_irq_uninstall(dev_priv->dev);
943out_no_irq:
944 if (dev_priv->stealth)
945 pci_release_region(dev->pdev, 2);
946 else
947 pci_release_regions(dev->pdev);
948out_no_device:
949 ttm_object_device_release(&dev_priv->tdev);
950out_err4:
951 memunmap(dev_priv->mmio_virt);
952out_err0:
953 for (i = vmw_res_context; i < vmw_res_max; ++i)
954 idr_destroy(&dev_priv->res_idr[i]);
955
956 if (dev_priv->ctx.staged_bindings)
957 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
958 kfree(dev_priv);
959 return ret;
960}
961
962static void vmw_driver_unload(struct drm_device *dev)
963{
964 struct vmw_private *dev_priv = vmw_priv(dev);
965 enum vmw_res_type i;
966
967 unregister_pm_notifier(&dev_priv->pm_nb);
968
969 if (dev_priv->ctx.res_ht_initialized)
970 drm_ht_remove(&dev_priv->ctx.res_ht);
971 vfree(dev_priv->ctx.cmd_bounce);
972 if (dev_priv->enable_fb) {
973 vmw_fb_off(dev_priv);
974 vmw_fb_close(dev_priv);
975 vmw_fifo_resource_dec(dev_priv);
976 vmw_svga_disable(dev_priv);
977 }
978
979 vmw_kms_close(dev_priv);
980 vmw_overlay_close(dev_priv);
981
982 if (dev_priv->has_gmr)
983 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
984 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
985
986 vmw_release_device_early(dev_priv);
987 if (dev_priv->has_mob)
988 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
989 (void) ttm_bo_device_release(&dev_priv->bdev);
990 vmw_release_device_late(dev_priv);
991 vmw_fence_manager_takedown(dev_priv->fman);
992 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
993 vmw_irq_uninstall(dev_priv->dev);
994 if (dev_priv->stealth)
995 pci_release_region(dev->pdev, 2);
996 else
997 pci_release_regions(dev->pdev);
998
999 ttm_object_device_release(&dev_priv->tdev);
1000 memunmap(dev_priv->mmio_virt);
1001 if (dev_priv->ctx.staged_bindings)
1002 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1003
1004 for (i = vmw_res_context; i < vmw_res_max; ++i)
1005 idr_destroy(&dev_priv->res_idr[i]);
1006
1007 kfree(dev_priv);
1008}
1009
1010static void vmw_postclose(struct drm_device *dev,
1011 struct drm_file *file_priv)
1012{
1013 struct vmw_fpriv *vmw_fp;
1014
1015 vmw_fp = vmw_fpriv(file_priv);
1016
1017 if (vmw_fp->locked_master) {
1018 struct vmw_master *vmaster =
1019 vmw_master(vmw_fp->locked_master);
1020
1021 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1022 ttm_vt_unlock(&vmaster->lock);
1023 drm_master_put(&vmw_fp->locked_master);
1024 }
1025
1026 ttm_object_file_release(&vmw_fp->tfile);
1027 kfree(vmw_fp);
1028}
1029
1030static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1031{
1032 struct vmw_private *dev_priv = vmw_priv(dev);
1033 struct vmw_fpriv *vmw_fp;
1034 int ret = -ENOMEM;
1035
1036 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1037 if (unlikely(!vmw_fp))
1038 return ret;
1039
1040 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1041 if (unlikely(vmw_fp->tfile == NULL))
1042 goto out_no_tfile;
1043
1044 file_priv->driver_priv = vmw_fp;
1045
1046 return 0;
1047
1048out_no_tfile:
1049 kfree(vmw_fp);
1050 return ret;
1051}
1052
1053static struct vmw_master *vmw_master_check(struct drm_device *dev,
1054 struct drm_file *file_priv,
1055 unsigned int flags)
1056{
1057 int ret;
1058 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1059 struct vmw_master *vmaster;
1060
1061 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1062 return NULL;
1063
1064 ret = mutex_lock_interruptible(&dev->master_mutex);
1065 if (unlikely(ret != 0))
1066 return ERR_PTR(-ERESTARTSYS);
1067
1068 if (drm_is_current_master(file_priv)) {
1069 mutex_unlock(&dev->master_mutex);
1070 return NULL;
1071 }
1072
1073
1074
1075
1076
1077 if (vmw_fp->locked_master) {
1078 mutex_unlock(&dev->master_mutex);
1079
1080 if (flags & DRM_RENDER_ALLOW)
1081 return NULL;
1082
1083 DRM_ERROR("Dropped master trying to access ioctl that "
1084 "requires authentication.\n");
1085 return ERR_PTR(-EACCES);
1086 }
1087 mutex_unlock(&dev->master_mutex);
1088
1089
1090
1091
1092
1093
1094 vmaster = vmw_master(file_priv->master);
1095 ret = ttm_read_lock(&vmaster->lock, true);
1096 if (unlikely(ret != 0))
1097 vmaster = ERR_PTR(ret);
1098
1099 return vmaster;
1100}
1101
1102static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1103 unsigned long arg,
1104 long (*ioctl_func)(struct file *, unsigned int,
1105 unsigned long))
1106{
1107 struct drm_file *file_priv = filp->private_data;
1108 struct drm_device *dev = file_priv->minor->dev;
1109 unsigned int nr = DRM_IOCTL_NR(cmd);
1110 struct vmw_master *vmaster;
1111 unsigned int flags;
1112 long ret;
1113
1114
1115
1116
1117
1118 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1119 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1120 const struct drm_ioctl_desc *ioctl =
1121 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1122
1123 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1124 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1125 if (unlikely(ret != 0))
1126 return ret;
1127
1128 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1129 goto out_io_encoding;
1130
1131 return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1132 _IOC_SIZE(cmd));
1133 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1134 if (!drm_is_current_master(file_priv) &&
1135 !capable(CAP_SYS_ADMIN))
1136 return -EACCES;
1137 }
1138
1139 if (unlikely(ioctl->cmd != cmd))
1140 goto out_io_encoding;
1141
1142 flags = ioctl->flags;
1143 } else if (!drm_ioctl_flags(nr, &flags))
1144 return -EINVAL;
1145
1146 vmaster = vmw_master_check(dev, file_priv, flags);
1147 if (IS_ERR(vmaster)) {
1148 ret = PTR_ERR(vmaster);
1149
1150 if (ret != -ERESTARTSYS)
1151 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1152 nr, ret);
1153 return ret;
1154 }
1155
1156 ret = ioctl_func(filp, cmd, arg);
1157 if (vmaster)
1158 ttm_read_unlock(&vmaster->lock);
1159
1160 return ret;
1161
1162out_io_encoding:
1163 DRM_ERROR("Invalid command format, ioctl %d\n",
1164 nr - DRM_COMMAND_BASE);
1165
1166 return -EINVAL;
1167}
1168
1169static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1170 unsigned long arg)
1171{
1172 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1173}
1174
1175#ifdef CONFIG_COMPAT
1176static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1177 unsigned long arg)
1178{
1179 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1180}
1181#endif
1182
1183static void vmw_lastclose(struct drm_device *dev)
1184{
1185}
1186
1187static void vmw_master_init(struct vmw_master *vmaster)
1188{
1189 ttm_lock_init(&vmaster->lock);
1190}
1191
1192static int vmw_master_create(struct drm_device *dev,
1193 struct drm_master *master)
1194{
1195 struct vmw_master *vmaster;
1196
1197 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1198 if (unlikely(!vmaster))
1199 return -ENOMEM;
1200
1201 vmw_master_init(vmaster);
1202 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1203 master->driver_priv = vmaster;
1204
1205 return 0;
1206}
1207
1208static void vmw_master_destroy(struct drm_device *dev,
1209 struct drm_master *master)
1210{
1211 struct vmw_master *vmaster = vmw_master(master);
1212
1213 master->driver_priv = NULL;
1214 kfree(vmaster);
1215}
1216
1217static int vmw_master_set(struct drm_device *dev,
1218 struct drm_file *file_priv,
1219 bool from_open)
1220{
1221 struct vmw_private *dev_priv = vmw_priv(dev);
1222 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1223 struct vmw_master *active = dev_priv->active_master;
1224 struct vmw_master *vmaster = vmw_master(file_priv->master);
1225 int ret = 0;
1226
1227 if (active) {
1228 BUG_ON(active != &dev_priv->fbdev_master);
1229 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1230 if (unlikely(ret != 0))
1231 return ret;
1232
1233 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1234 dev_priv->active_master = NULL;
1235 }
1236
1237 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1238 if (!from_open) {
1239 ttm_vt_unlock(&vmaster->lock);
1240 BUG_ON(vmw_fp->locked_master != file_priv->master);
1241 drm_master_put(&vmw_fp->locked_master);
1242 }
1243
1244 dev_priv->active_master = vmaster;
1245
1246
1247
1248
1249
1250 if (!from_open)
1251 drm_sysfs_hotplug_event(dev);
1252
1253 return 0;
1254}
1255
1256static void vmw_master_drop(struct drm_device *dev,
1257 struct drm_file *file_priv)
1258{
1259 struct vmw_private *dev_priv = vmw_priv(dev);
1260 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1261 struct vmw_master *vmaster = vmw_master(file_priv->master);
1262 int ret;
1263
1264
1265
1266
1267
1268
1269 vmw_fp->locked_master = drm_master_get(file_priv->master);
1270 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1271 vmw_kms_legacy_hotspot_clear(dev_priv);
1272 if (unlikely((ret != 0))) {
1273 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1274 drm_master_put(&vmw_fp->locked_master);
1275 }
1276
1277 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1278
1279 if (!dev_priv->enable_fb)
1280 vmw_svga_disable(dev_priv);
1281
1282 dev_priv->active_master = &dev_priv->fbdev_master;
1283 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1284 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1285}
1286
1287
1288
1289
1290
1291
1292
1293static void __vmw_svga_enable(struct vmw_private *dev_priv)
1294{
1295 spin_lock(&dev_priv->svga_lock);
1296 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1297 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1298 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1299 }
1300 spin_unlock(&dev_priv->svga_lock);
1301}
1302
1303
1304
1305
1306
1307
1308void vmw_svga_enable(struct vmw_private *dev_priv)
1309{
1310 (void) ttm_read_lock(&dev_priv->reservation_sem, false);
1311 __vmw_svga_enable(dev_priv);
1312 ttm_read_unlock(&dev_priv->reservation_sem);
1313}
1314
1315
1316
1317
1318
1319
1320
1321
1322static void __vmw_svga_disable(struct vmw_private *dev_priv)
1323{
1324 spin_lock(&dev_priv->svga_lock);
1325 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1326 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1327 vmw_write(dev_priv, SVGA_REG_ENABLE,
1328 SVGA_REG_ENABLE_HIDE |
1329 SVGA_REG_ENABLE_ENABLE);
1330 }
1331 spin_unlock(&dev_priv->svga_lock);
1332}
1333
1334
1335
1336
1337
1338
1339
1340
1341void vmw_svga_disable(struct vmw_private *dev_priv)
1342{
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355 vmw_kms_lost_device(dev_priv->dev);
1356 ttm_write_lock(&dev_priv->reservation_sem, false);
1357 spin_lock(&dev_priv->svga_lock);
1358 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1359 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1360 spin_unlock(&dev_priv->svga_lock);
1361 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1362 DRM_ERROR("Failed evicting VRAM buffers.\n");
1363 vmw_write(dev_priv, SVGA_REG_ENABLE,
1364 SVGA_REG_ENABLE_HIDE |
1365 SVGA_REG_ENABLE_ENABLE);
1366 } else
1367 spin_unlock(&dev_priv->svga_lock);
1368 ttm_write_unlock(&dev_priv->reservation_sem);
1369}
1370
1371static void vmw_remove(struct pci_dev *pdev)
1372{
1373 struct drm_device *dev = pci_get_drvdata(pdev);
1374
1375 pci_disable_device(pdev);
1376 drm_put_dev(dev);
1377}
1378
1379static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1380 void *ptr)
1381{
1382 struct vmw_private *dev_priv =
1383 container_of(nb, struct vmw_private, pm_nb);
1384
1385 switch (val) {
1386 case PM_HIBERNATION_PREPARE:
1387
1388
1389
1390
1391
1392
1393
1394
1395 ttm_suspend_lock(&dev_priv->reservation_sem);
1396 dev_priv->suspend_locked = true;
1397 break;
1398 case PM_POST_HIBERNATION:
1399 case PM_POST_RESTORE:
1400 if (READ_ONCE(dev_priv->suspend_locked)) {
1401 dev_priv->suspend_locked = false;
1402 ttm_suspend_unlock(&dev_priv->reservation_sem);
1403 }
1404 break;
1405 default:
1406 break;
1407 }
1408 return 0;
1409}
1410
1411static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1412{
1413 struct drm_device *dev = pci_get_drvdata(pdev);
1414 struct vmw_private *dev_priv = vmw_priv(dev);
1415
1416 if (dev_priv->refuse_hibernation)
1417 return -EBUSY;
1418
1419 pci_save_state(pdev);
1420 pci_disable_device(pdev);
1421 pci_set_power_state(pdev, PCI_D3hot);
1422 return 0;
1423}
1424
1425static int vmw_pci_resume(struct pci_dev *pdev)
1426{
1427 pci_set_power_state(pdev, PCI_D0);
1428 pci_restore_state(pdev);
1429 return pci_enable_device(pdev);
1430}
1431
1432static int vmw_pm_suspend(struct device *kdev)
1433{
1434 struct pci_dev *pdev = to_pci_dev(kdev);
1435 struct pm_message dummy;
1436
1437 dummy.event = 0;
1438
1439 return vmw_pci_suspend(pdev, dummy);
1440}
1441
1442static int vmw_pm_resume(struct device *kdev)
1443{
1444 struct pci_dev *pdev = to_pci_dev(kdev);
1445
1446 return vmw_pci_resume(pdev);
1447}
1448
1449static int vmw_pm_freeze(struct device *kdev)
1450{
1451 struct pci_dev *pdev = to_pci_dev(kdev);
1452 struct drm_device *dev = pci_get_drvdata(pdev);
1453 struct vmw_private *dev_priv = vmw_priv(dev);
1454 int ret;
1455
1456
1457
1458
1459
1460 ttm_suspend_unlock(&dev_priv->reservation_sem);
1461 ret = vmw_kms_suspend(dev_priv->dev);
1462 if (ret) {
1463 ttm_suspend_lock(&dev_priv->reservation_sem);
1464 DRM_ERROR("Failed to freeze modesetting.\n");
1465 return ret;
1466 }
1467 if (dev_priv->enable_fb)
1468 vmw_fb_off(dev_priv);
1469
1470 ttm_suspend_lock(&dev_priv->reservation_sem);
1471 vmw_execbuf_release_pinned_bo(dev_priv);
1472 vmw_resource_evict_all(dev_priv);
1473 vmw_release_device_early(dev_priv);
1474 ttm_bo_swapout_all(&dev_priv->bdev);
1475 if (dev_priv->enable_fb)
1476 vmw_fifo_resource_dec(dev_priv);
1477 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1478 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1479 if (dev_priv->enable_fb)
1480 vmw_fifo_resource_inc(dev_priv);
1481 WARN_ON(vmw_request_device_late(dev_priv));
1482 dev_priv->suspend_locked = false;
1483 ttm_suspend_unlock(&dev_priv->reservation_sem);
1484 if (dev_priv->suspend_state)
1485 vmw_kms_resume(dev);
1486 if (dev_priv->enable_fb)
1487 vmw_fb_on(dev_priv);
1488 return -EBUSY;
1489 }
1490
1491 vmw_fence_fifo_down(dev_priv->fman);
1492 __vmw_svga_disable(dev_priv);
1493
1494 vmw_release_device_late(dev_priv);
1495 return 0;
1496}
1497
1498static int vmw_pm_restore(struct device *kdev)
1499{
1500 struct pci_dev *pdev = to_pci_dev(kdev);
1501 struct drm_device *dev = pci_get_drvdata(pdev);
1502 struct vmw_private *dev_priv = vmw_priv(dev);
1503 int ret;
1504
1505 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1506 (void) vmw_read(dev_priv, SVGA_REG_ID);
1507
1508 if (dev_priv->enable_fb)
1509 vmw_fifo_resource_inc(dev_priv);
1510
1511 ret = vmw_request_device(dev_priv);
1512 if (ret)
1513 return ret;
1514
1515 if (dev_priv->enable_fb)
1516 __vmw_svga_enable(dev_priv);
1517
1518 vmw_fence_fifo_up(dev_priv->fman);
1519 dev_priv->suspend_locked = false;
1520 ttm_suspend_unlock(&dev_priv->reservation_sem);
1521 if (dev_priv->suspend_state)
1522 vmw_kms_resume(dev_priv->dev);
1523
1524 if (dev_priv->enable_fb)
1525 vmw_fb_on(dev_priv);
1526
1527 return 0;
1528}
1529
1530static const struct dev_pm_ops vmw_pm_ops = {
1531 .freeze = vmw_pm_freeze,
1532 .thaw = vmw_pm_restore,
1533 .restore = vmw_pm_restore,
1534 .suspend = vmw_pm_suspend,
1535 .resume = vmw_pm_resume,
1536};
1537
1538static const struct file_operations vmwgfx_driver_fops = {
1539 .owner = THIS_MODULE,
1540 .open = drm_open,
1541 .release = drm_release,
1542 .unlocked_ioctl = vmw_unlocked_ioctl,
1543 .mmap = vmw_mmap,
1544 .poll = vmw_fops_poll,
1545 .read = vmw_fops_read,
1546#if defined(CONFIG_COMPAT)
1547 .compat_ioctl = vmw_compat_ioctl,
1548#endif
1549 .llseek = noop_llseek,
1550};
1551
1552static struct drm_driver driver = {
1553 .driver_features =
1554 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
1555 .load = vmw_driver_load,
1556 .unload = vmw_driver_unload,
1557 .lastclose = vmw_lastclose,
1558 .get_vblank_counter = vmw_get_vblank_counter,
1559 .enable_vblank = vmw_enable_vblank,
1560 .disable_vblank = vmw_disable_vblank,
1561 .ioctls = vmw_ioctls,
1562 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1563 .master_create = vmw_master_create,
1564 .master_destroy = vmw_master_destroy,
1565 .master_set = vmw_master_set,
1566 .master_drop = vmw_master_drop,
1567 .open = vmw_driver_open,
1568 .postclose = vmw_postclose,
1569
1570 .dumb_create = vmw_dumb_create,
1571 .dumb_map_offset = vmw_dumb_map_offset,
1572 .dumb_destroy = vmw_dumb_destroy,
1573
1574 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1575 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1576
1577 .fops = &vmwgfx_driver_fops,
1578 .name = VMWGFX_DRIVER_NAME,
1579 .desc = VMWGFX_DRIVER_DESC,
1580 .date = VMWGFX_DRIVER_DATE,
1581 .major = VMWGFX_DRIVER_MAJOR,
1582 .minor = VMWGFX_DRIVER_MINOR,
1583 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1584};
1585
1586static struct pci_driver vmw_pci_driver = {
1587 .name = VMWGFX_DRIVER_NAME,
1588 .id_table = vmw_pci_id_list,
1589 .probe = vmw_probe,
1590 .remove = vmw_remove,
1591 .driver = {
1592 .pm = &vmw_pm_ops
1593 }
1594};
1595
1596static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1597{
1598 return drm_get_pci_dev(pdev, ent, &driver);
1599}
1600
1601static int __init vmwgfx_init(void)
1602{
1603 int ret;
1604
1605 if (vgacon_text_force())
1606 return -EINVAL;
1607
1608 ret = pci_register_driver(&vmw_pci_driver);
1609 if (ret)
1610 DRM_ERROR("Failed initializing DRM.\n");
1611 return ret;
1612}
1613
1614static void __exit vmwgfx_exit(void)
1615{
1616 pci_unregister_driver(&vmw_pci_driver);
1617}
1618
1619module_init(vmwgfx_init);
1620module_exit(vmwgfx_exit);
1621
1622MODULE_AUTHOR("VMware Inc. and others");
1623MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1624MODULE_LICENSE("GPL and additional rights");
1625MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1626 __stringify(VMWGFX_DRIVER_MINOR) "."
1627 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1628 "0");
1629
