LXR linux/drivers/gpu/ipu-v3/ipu-dc.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   5 */
   6
   7#include <linux/export.h>
   8#include <linux/module.h>
   9#include <linux/types.h>
  10#include <linux/errno.h>
  11#include <linux/delay.h>
  12#include <linux/interrupt.h>
  13#include <linux/io.h>
  14
  15#include <video/imx-ipu-v3.h>
  16#include "ipu-prv.h"
  17
  18#define DC_MAP_CONF_PTR(n)      (0x108 + ((n) & ~0x1) * 2)
  19#define DC_MAP_CONF_VAL(n)      (0x144 + ((n) & ~0x1) * 2)
  20
  21#define DC_EVT_NF               0
  22#define DC_EVT_NL               1
  23#define DC_EVT_EOF              2
  24#define DC_EVT_NFIELD           3
  25#define DC_EVT_EOL              4
  26#define DC_EVT_EOFIELD          5
  27#define DC_EVT_NEW_ADDR         6
  28#define DC_EVT_NEW_CHAN         7
  29#define DC_EVT_NEW_DATA         8
  30
  31#define DC_EVT_NEW_ADDR_W_0     0
  32#define DC_EVT_NEW_ADDR_W_1     1
  33#define DC_EVT_NEW_CHAN_W_0     2
  34#define DC_EVT_NEW_CHAN_W_1     3
  35#define DC_EVT_NEW_DATA_W_0     4
  36#define DC_EVT_NEW_DATA_W_1     5
  37#define DC_EVT_NEW_ADDR_R_0     6
  38#define DC_EVT_NEW_ADDR_R_1     7
  39#define DC_EVT_NEW_CHAN_R_0     8
  40#define DC_EVT_NEW_CHAN_R_1     9
  41#define DC_EVT_NEW_DATA_R_0     10
  42#define DC_EVT_NEW_DATA_R_1     11
  43
  44#define DC_WR_CH_CONF           0x0
  45#define DC_WR_CH_ADDR           0x4
  46#define DC_RL_CH(evt)           (8 + ((evt) & ~0x1) * 2)
  47
  48#define DC_GEN                  0xd4
  49#define DC_DISP_CONF1(disp)     (0xd8 + (disp) * 4)
  50#define DC_DISP_CONF2(disp)     (0xe8 + (disp) * 4)
  51#define DC_STAT                 0x1c8
  52
  53#define WROD(lf)                (0x18 | ((lf) << 1))
  54#define WRG                     0x01
  55#define WCLK                    0xc9
  56
  57#define SYNC_WAVE 0
  58#define NULL_WAVE (-1)
  59
  60#define DC_GEN_SYNC_1_6_SYNC    (2 << 1)
  61#define DC_GEN_SYNC_PRIORITY_1  (1 << 7)
  62
  63#define DC_WR_CH_CONF_WORD_SIZE_8               (0 << 0)
  64#define DC_WR_CH_CONF_WORD_SIZE_16              (1 << 0)
  65#define DC_WR_CH_CONF_WORD_SIZE_24              (2 << 0)
  66#define DC_WR_CH_CONF_WORD_SIZE_32              (3 << 0)
  67#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)       (((i) & 0x1) << 3)
  68#define DC_WR_CH_CONF_DISP_ID_SERIAL            (2 << 3)
  69#define DC_WR_CH_CONF_DISP_ID_ASYNC             (3 << 4)
  70#define DC_WR_CH_CONF_FIELD_MODE                (1 << 9)
  71#define DC_WR_CH_CONF_PROG_TYPE_NORMAL          (4 << 5)
  72#define DC_WR_CH_CONF_PROG_TYPE_MASK            (7 << 5)
  73#define DC_WR_CH_CONF_PROG_DI_ID                (1 << 2)
  74#define DC_WR_CH_CONF_PROG_DISP_ID(i)           (((i) & 0x1) << 3)
  75
  76#define IPU_DC_NUM_CHANNELS     10
  77
  78struct ipu_dc_priv;
  79
  80enum ipu_dc_map {
  81        IPU_DC_MAP_RGB24,
  82        IPU_DC_MAP_RGB565,
  83        IPU_DC_MAP_GBR24, /* TVEv2 */
  84        IPU_DC_MAP_BGR666,
  85        IPU_DC_MAP_LVDS666,
  86        IPU_DC_MAP_BGR24,
  87};
  88
  89struct ipu_dc {
  90        /* The display interface number assigned to this dc channel */
  91        unsigned int            di;
  92        void __iomem            *base;
  93        struct ipu_dc_priv      *priv;
  94        int                     chno;
  95        bool                    in_use;
  96};
  97
  98struct ipu_dc_priv {
  99        void __iomem            *dc_reg;
 100        void __iomem            *dc_tmpl_reg;
 101        struct ipu_soc          *ipu;
 102        struct device           *dev;
 103        struct ipu_dc           channels[IPU_DC_NUM_CHANNELS];
 104        struct mutex            mutex;
 105        struct completion       comp;
 106        int                     use_count;
 107};
 108
 109static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 110{
 111        u32 reg;
 112
 113        reg = readl(dc->base + DC_RL_CH(event));
 114        reg &= ~(0xffff << (16 * (event & 0x1)));
 115        reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 116        writel(reg, dc->base + DC_RL_CH(event));
 117}
 118
 119static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 120                int map, int wave, int glue, int sync, int stop)
 121{
 122        struct ipu_dc_priv *priv = dc->priv;
 123        u32 reg1, reg2;
 124
 125        if (opcode == WCLK) {
 126                reg1 = (operand << 20) & 0xfff00000;
 127                reg2 = operand >> 12 | opcode << 1 | stop << 9;
 128        } else if (opcode == WRG) {
 129                reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
 130                reg2 = operand >> 17 | opcode << 7 | stop << 9;
 131        } else {
 132                reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
 133                reg2 = operand >> 12 | opcode << 4 | stop << 9;
 134        }
 135        writel(reg1, priv->dc_tmpl_reg + word * 8);
 136        writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 137}
 138
 139static int ipu_bus_format_to_map(u32 fmt)
 140{
 141        switch (fmt) {
 142        default:
 143                WARN_ON(1);
 144                /* fall-through */
 145        case MEDIA_BUS_FMT_RGB888_1X24:
 146                return IPU_DC_MAP_RGB24;
 147        case MEDIA_BUS_FMT_RGB565_1X16:
 148                return IPU_DC_MAP_RGB565;
 149        case MEDIA_BUS_FMT_GBR888_1X24:
 150                return IPU_DC_MAP_GBR24;
 151        case MEDIA_BUS_FMT_RGB666_1X18:
 152                return IPU_DC_MAP_BGR666;
 153        case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
 154                return IPU_DC_MAP_LVDS666;
 155        case MEDIA_BUS_FMT_BGR888_1X24:
 156                return IPU_DC_MAP_BGR24;
 157        }
 158}
 159
 160int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 161                u32 bus_format, u32 width)
 162{
 163        struct ipu_dc_priv *priv = dc->priv;
 164        int addr, sync;
 165        u32 reg = 0;
 166        int map;
 167
 168        dc->di = ipu_di_get_num(di);
 169
 170        map = ipu_bus_format_to_map(bus_format);
 171
 172        /*
 173         * In interlaced mode we need more counters to create the asymmetric
 174         * per-field VSYNC signals. The pixel active signal synchronising DC
 175         * to DI moves to signal generator #6 (see ipu-di.c). In progressive
 176         * mode counter #5 is used.
 177         */
 178        sync = interlaced ? 6 : 5;
 179
 180        /* Reserve 5 microcode template words for each DI */
 181        if (dc->di)
 182                addr = 5;
 183        else
 184                addr = 0;
 185
 186        if (interlaced) {
 187                dc_link_event(dc, DC_EVT_NL, addr, 3);
 188                dc_link_event(dc, DC_EVT_EOL, addr, 2);
 189                dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
 190
 191                /* Init template microcode */
 192                dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
 193        } else {
 194                dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
 195                dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
 196                dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
 197
 198                /* Init template microcode */
 199                dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
 200                dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
 201                dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 202                dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
 203        }
 204
 205        dc_link_event(dc, DC_EVT_NF, 0, 0);
 206        dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
 207        dc_link_event(dc, DC_EVT_EOF, 0, 0);
 208        dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
 209        dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
 210        dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
 211
 212        reg = readl(dc->base + DC_WR_CH_CONF);
 213        if (interlaced)
 214                reg |= DC_WR_CH_CONF_FIELD_MODE;
 215        else
 216                reg &= ~DC_WR_CH_CONF_FIELD_MODE;
 217        writel(reg, dc->base + DC_WR_CH_CONF);
 218
 219        writel(0x0, dc->base + DC_WR_CH_ADDR);
 220        writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
 221
 222        return 0;
 223}
 224EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 225
 226void ipu_dc_enable(struct ipu_soc *ipu)
 227{
 228        struct ipu_dc_priv *priv = ipu->dc_priv;
 229
 230        mutex_lock(&priv->mutex);
 231
 232        if (!priv->use_count)
 233                ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 234
 235        priv->use_count++;
 236
 237        mutex_unlock(&priv->mutex);
 238}
 239EXPORT_SYMBOL_GPL(ipu_dc_enable);
 240
 241void ipu_dc_enable_channel(struct ipu_dc *dc)
 242{
 243        u32 reg;
 244
 245        reg = readl(dc->base + DC_WR_CH_CONF);
 246        reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
 247        writel(reg, dc->base + DC_WR_CH_CONF);
 248}
 249EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
 250
 251void ipu_dc_disable_channel(struct ipu_dc *dc)
 252{
 253        u32 val;
 254
 255        val = readl(dc->base + DC_WR_CH_CONF);
 256        val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 257        writel(val, dc->base + DC_WR_CH_CONF);
 258}
 259EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 260
 261void ipu_dc_disable(struct ipu_soc *ipu)
 262{
 263        struct ipu_dc_priv *priv = ipu->dc_priv;
 264
 265        mutex_lock(&priv->mutex);
 266
 267        priv->use_count--;
 268        if (!priv->use_count)
 269                ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
 270
 271        if (priv->use_count < 0)
 272                priv->use_count = 0;
 273
 274        mutex_unlock(&priv->mutex);
 275}
 276EXPORT_SYMBOL_GPL(ipu_dc_disable);
 277
 278static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
 279                int byte_num, int offset, int mask)
 280{
 281        int ptr = map * 3 + byte_num;
 282        u32 reg;
 283
 284        reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 285        reg &= ~(0xffff << (16 * (ptr & 0x1)));
 286        reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 287        writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 288
 289        reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 290        reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
 291        reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 292        writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
 293}
 294
 295static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
 296{
 297        u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 298
 299        writel(reg & ~(0xffff << (16 * (map & 0x1))),
 300                     priv->dc_reg + DC_MAP_CONF_PTR(map));
 301}
 302
 303struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
 304{
 305        struct ipu_dc_priv *priv = ipu->dc_priv;
 306        struct ipu_dc *dc;
 307
 308        if (channel >= IPU_DC_NUM_CHANNELS)
 309                return ERR_PTR(-ENODEV);
 310
 311        dc = &priv->channels[channel];
 312
 313        mutex_lock(&priv->mutex);
 314
 315        if (dc->in_use) {
 316                mutex_unlock(&priv->mutex);
 317                return ERR_PTR(-EBUSY);
 318        }
 319
 320        dc->in_use = true;
 321
 322        mutex_unlock(&priv->mutex);
 323
 324        return dc;
 325}
 326EXPORT_SYMBOL_GPL(ipu_dc_get);
 327
 328void ipu_dc_put(struct ipu_dc *dc)
 329{
 330        struct ipu_dc_priv *priv = dc->priv;
 331
 332        mutex_lock(&priv->mutex);
 333        dc->in_use = false;
 334        mutex_unlock(&priv->mutex);
 335}
 336EXPORT_SYMBOL_GPL(ipu_dc_put);
 337
 338int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 339                unsigned long base, unsigned long template_base)
 340{
 341        struct ipu_dc_priv *priv;
 342        static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
 343                0x78, 0, 0x94, 0xb4};
 344        int i;
 345
 346        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 347        if (!priv)
 348                return -ENOMEM;
 349
 350        mutex_init(&priv->mutex);
 351
 352        priv->dev = dev;
 353        priv->ipu = ipu;
 354        priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
 355        priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
 356        if (!priv->dc_reg || !priv->dc_tmpl_reg)
 357                return -ENOMEM;
 358
 359        for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
 360                priv->channels[i].chno = i;
 361                priv->channels[i].priv = priv;
 362                priv->channels[i].base = priv->dc_reg + channel_offsets[i];
 363        }
 364
 365        writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
 366                        DC_WR_CH_CONF_PROG_DI_ID,
 367                        priv->channels[1].base + DC_WR_CH_CONF);
 368        writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
 369                        priv->channels[5].base + DC_WR_CH_CONF);
 370
 371        writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
 372                priv->dc_reg + DC_GEN);
 373
 374        ipu->dc_priv = priv;
 375
 376        dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 377                        base, template_base);
 378
 379        /* rgb24 */
 380        ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
 381        ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
 382        ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
 383        ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
 384
 385        /* rgb565 */
 386        ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
 387        ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
 388        ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
 389        ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
 390
 391        /* gbr24 */
 392        ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
 393        ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
 394        ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
 395        ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
 396
 397        /* bgr666 */
 398        ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
 399        ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
 400        ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
 401        ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
 402
 403        /* lvds666 */
 404        ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
 405        ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
 406        ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
 407        ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
 408
 409        /* bgr24 */
 410        ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
 411        ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
 412        ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
 413        ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
 414
 415        return 0;
 416}
 417
 418void ipu_dc_exit(struct ipu_soc *ipu)
 419{
 420}
 421