linux/drivers/hwmon/nct6775.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * nct6775 - Driver for the hardware monitoring functionality of
   4 *             Nuvoton NCT677x Super-I/O chips
   5 *
   6 * Copyright (C) 2012  Guenter Roeck <linux@roeck-us.net>
   7 *
   8 * Derived from w83627ehf driver
   9 * Copyright (C) 2005-2012  Jean Delvare <jdelvare@suse.de>
  10 * Copyright (C) 2006  Yuan Mu (Winbond),
  11 *                     Rudolf Marek <r.marek@assembler.cz>
  12 *                     David Hubbard <david.c.hubbard@gmail.com>
  13 *                     Daniel J Blueman <daniel.blueman@gmail.com>
  14 * Copyright (C) 2010  Sheng-Yuan Huang (Nuvoton) (PS00)
  15 *
  16 * Shamelessly ripped from the w83627hf driver
  17 * Copyright (C) 2003  Mark Studebaker
  18 *
  19 * Supports the following chips:
  20 *
  21 * Chip        #vin    #fan    #pwm    #temp  chip IDs       man ID
  22 * nct6106d     9      3       3       6+3    0xc450 0xc1    0x5ca3
  23 * nct6775f     9      4       3       6+3    0xb470 0xc1    0x5ca3
  24 * nct6776f     9      5       3       6+3    0xc330 0xc1    0x5ca3
  25 * nct6779d    15      5       5       2+6    0xc560 0xc1    0x5ca3
  26 * nct6791d    15      6       6       2+6    0xc800 0xc1    0x5ca3
  27 * nct6792d    15      6       6       2+6    0xc910 0xc1    0x5ca3
  28 * nct6793d    15      6       6       2+6    0xd120 0xc1    0x5ca3
  29 * nct6795d    14      6       6       2+6    0xd350 0xc1    0x5ca3
  30 * nct6796d    14      7       7       2+6    0xd420 0xc1    0x5ca3
  31 * nct6797d    14      7       7       2+6    0xd450 0xc1    0x5ca3
  32 *                                           (0xd451)
  33 * nct6798d    14      7       7       2+6    0xd428 0xc1    0x5ca3
  34 *                                           (0xd429)
  35 *
  36 * #temp lists the number of monitored temperature sources (first value) plus
  37 * the number of directly connectable temperature sensors (second value).
  38 */
  39
  40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  41
  42#include <linux/module.h>
  43#include <linux/init.h>
  44#include <linux/slab.h>
  45#include <linux/jiffies.h>
  46#include <linux/platform_device.h>
  47#include <linux/hwmon.h>
  48#include <linux/hwmon-sysfs.h>
  49#include <linux/hwmon-vid.h>
  50#include <linux/err.h>
  51#include <linux/mutex.h>
  52#include <linux/acpi.h>
  53#include <linux/bitops.h>
  54#include <linux/dmi.h>
  55#include <linux/io.h>
  56#include <linux/nospec.h>
  57#include "lm75.h"
  58
  59#define USE_ALTERNATE
  60
  61enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
  62             nct6795, nct6796, nct6797, nct6798 };
  63
  64/* used to set data->name = nct6775_device_names[data->sio_kind] */
  65static const char * const nct6775_device_names[] = {
  66        "nct6106",
  67        "nct6775",
  68        "nct6776",
  69        "nct6779",
  70        "nct6791",
  71        "nct6792",
  72        "nct6793",
  73        "nct6795",
  74        "nct6796",
  75        "nct6797",
  76        "nct6798",
  77};
  78
  79static const char * const nct6775_sio_names[] __initconst = {
  80        "NCT6106D",
  81        "NCT6775F",
  82        "NCT6776D/F",
  83        "NCT6779D",
  84        "NCT6791D",
  85        "NCT6792D",
  86        "NCT6793D",
  87        "NCT6795D",
  88        "NCT6796D",
  89        "NCT6797D",
  90        "NCT6798D",
  91};
  92
  93static unsigned short force_id;
  94module_param(force_id, ushort, 0);
  95MODULE_PARM_DESC(force_id, "Override the detected device ID");
  96
  97static unsigned short fan_debounce;
  98module_param(fan_debounce, ushort, 0);
  99MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
 100
 101#define DRVNAME "nct6775"
 102
 103/*
 104 * Super-I/O constants and functions
 105 */
 106
 107#define NCT6775_LD_ACPI         0x0a
 108#define NCT6775_LD_HWM          0x0b
 109#define NCT6775_LD_VID          0x0d
 110#define NCT6775_LD_12           0x12
 111
 112#define SIO_REG_LDSEL           0x07    /* Logical device select */
 113#define SIO_REG_DEVID           0x20    /* Device ID (2 bytes) */
 114#define SIO_REG_ENABLE          0x30    /* Logical device enable */
 115#define SIO_REG_ADDR            0x60    /* Logical device address (2 bytes) */
 116
 117#define SIO_NCT6106_ID          0xc450
 118#define SIO_NCT6775_ID          0xb470
 119#define SIO_NCT6776_ID          0xc330
 120#define SIO_NCT6779_ID          0xc560
 121#define SIO_NCT6791_ID          0xc800
 122#define SIO_NCT6792_ID          0xc910
 123#define SIO_NCT6793_ID          0xd120
 124#define SIO_NCT6795_ID          0xd350
 125#define SIO_NCT6796_ID          0xd420
 126#define SIO_NCT6797_ID          0xd450
 127#define SIO_NCT6798_ID          0xd428
 128#define SIO_ID_MASK             0xFFF8
 129
 130enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
 131
 132static inline void
 133superio_outb(int ioreg, int reg, int val)
 134{
 135        outb(reg, ioreg);
 136        outb(val, ioreg + 1);
 137}
 138
 139static inline int
 140superio_inb(int ioreg, int reg)
 141{
 142        outb(reg, ioreg);
 143        return inb(ioreg + 1);
 144}
 145
 146static inline void
 147superio_select(int ioreg, int ld)
 148{
 149        outb(SIO_REG_LDSEL, ioreg);
 150        outb(ld, ioreg + 1);
 151}
 152
 153static inline int
 154superio_enter(int ioreg)
 155{
 156        /*
 157         * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
 158         */
 159        if (!request_muxed_region(ioreg, 2, DRVNAME))
 160                return -EBUSY;
 161
 162        outb(0x87, ioreg);
 163        outb(0x87, ioreg);
 164
 165        return 0;
 166}
 167
 168static inline void
 169superio_exit(int ioreg)
 170{
 171        outb(0xaa, ioreg);
 172        outb(0x02, ioreg);
 173        outb(0x02, ioreg + 1);
 174        release_region(ioreg, 2);
 175}
 176
 177/*
 178 * ISA constants
 179 */
 180
 181#define IOREGION_ALIGNMENT      (~7)
 182#define IOREGION_OFFSET         5
 183#define IOREGION_LENGTH         2
 184#define ADDR_REG_OFFSET         0
 185#define DATA_REG_OFFSET         1
 186
 187#define NCT6775_REG_BANK        0x4E
 188#define NCT6775_REG_CONFIG      0x40
 189
 190/*
 191 * Not currently used:
 192 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
 193 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
 194 * REG_MAN_ID is at port 0x4f
 195 * REG_CHIP_ID is at port 0x58
 196 */
 197
 198#define NUM_TEMP        10      /* Max number of temp attribute sets w/ limits*/
 199#define NUM_TEMP_FIXED  6       /* Max number of fixed temp attribute sets */
 200
 201#define NUM_REG_ALARM   7       /* Max number of alarm registers */
 202#define NUM_REG_BEEP    5       /* Max number of beep registers */
 203
 204#define NUM_FAN         7
 205
 206/* Common and NCT6775 specific data */
 207
 208/* Voltage min/max registers for nr=7..14 are in bank 5 */
 209
 210static const u16 NCT6775_REG_IN_MAX[] = {
 211        0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
 212        0x55c, 0x55e, 0x560, 0x562 };
 213static const u16 NCT6775_REG_IN_MIN[] = {
 214        0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
 215        0x55d, 0x55f, 0x561, 0x563 };
 216static const u16 NCT6775_REG_IN[] = {
 217        0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
 218};
 219
 220#define NCT6775_REG_VBAT                0x5D
 221#define NCT6775_REG_DIODE               0x5E
 222#define NCT6775_DIODE_MASK              0x02
 223
 224#define NCT6775_REG_FANDIV1             0x506
 225#define NCT6775_REG_FANDIV2             0x507
 226
 227#define NCT6775_REG_CR_FAN_DEBOUNCE     0xf0
 228
 229static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
 230
 231/* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
 232
 233static const s8 NCT6775_ALARM_BITS[] = {
 234        0, 1, 2, 3, 8, 21, 20, 16,      /* in0.. in7 */
 235        17, -1, -1, -1, -1, -1, -1,     /* in8..in14 */
 236        -1,                             /* unused */
 237        6, 7, 11, -1, -1,               /* fan1..fan5 */
 238        -1, -1, -1,                     /* unused */
 239        4, 5, 13, -1, -1, -1,           /* temp1..temp6 */
 240        12, -1 };                       /* intrusion0, intrusion1 */
 241
 242#define FAN_ALARM_BASE          16
 243#define TEMP_ALARM_BASE         24
 244#define INTRUSION_ALARM_BASE    30
 245
 246static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
 247
 248/*
 249 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
 250 * 30..31 intrusion
 251 */
 252static const s8 NCT6775_BEEP_BITS[] = {
 253        0, 1, 2, 3, 8, 9, 10, 16,       /* in0.. in7 */
 254        17, -1, -1, -1, -1, -1, -1,     /* in8..in14 */
 255        21,                             /* global beep enable */
 256        6, 7, 11, 28, -1,               /* fan1..fan5 */
 257        -1, -1, -1,                     /* unused */
 258        4, 5, 13, -1, -1, -1,           /* temp1..temp6 */
 259        12, -1 };                       /* intrusion0, intrusion1 */
 260
 261#define BEEP_ENABLE_BASE                15
 262
 263static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
 264static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
 265
 266/* DC or PWM output fan configuration */
 267static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
 268static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
 269
 270/* Advanced Fan control, some values are common for all fans */
 271
 272static const u16 NCT6775_REG_TARGET[] = {
 273        0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
 274static const u16 NCT6775_REG_FAN_MODE[] = {
 275        0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
 276static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
 277        0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
 278static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
 279        0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
 280static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
 281        0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
 282static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
 283        0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
 284static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
 285static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
 286
 287static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
 288        0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
 289static const u16 NCT6775_REG_PWM[] = {
 290        0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
 291static const u16 NCT6775_REG_PWM_READ[] = {
 292        0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
 293
 294static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
 295static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
 296static const u16 NCT6775_REG_FAN_PULSES[NUM_FAN] = {
 297        0x641, 0x642, 0x643, 0x644 };
 298static const u16 NCT6775_FAN_PULSE_SHIFT[NUM_FAN] = { };
 299
 300static const u16 NCT6775_REG_TEMP[] = {
 301        0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
 302
 303static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
 304
 305static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
 306        0, 0x152, 0x252, 0x628, 0x629, 0x62A };
 307static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
 308        0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
 309static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
 310        0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
 311
 312static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
 313        0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
 314
 315static const u16 NCT6775_REG_TEMP_SEL[] = {
 316        0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
 317
 318static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
 319        0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
 320static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
 321        0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
 322static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
 323        0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
 324static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
 325        0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
 326static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
 327        0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
 328
 329static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
 330
 331static const u16 NCT6775_REG_AUTO_TEMP[] = {
 332        0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
 333static const u16 NCT6775_REG_AUTO_PWM[] = {
 334        0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
 335
 336#define NCT6775_AUTO_TEMP(data, nr, p)  ((data)->REG_AUTO_TEMP[nr] + (p))
 337#define NCT6775_AUTO_PWM(data, nr, p)   ((data)->REG_AUTO_PWM[nr] + (p))
 338
 339static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
 340
 341static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
 342        0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
 343static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
 344        0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
 345
 346static const char *const nct6775_temp_label[] = {
 347        "",
 348        "SYSTIN",
 349        "CPUTIN",
 350        "AUXTIN",
 351        "AMD SB-TSI",
 352        "PECI Agent 0",
 353        "PECI Agent 1",
 354        "PECI Agent 2",
 355        "PECI Agent 3",
 356        "PECI Agent 4",
 357        "PECI Agent 5",
 358        "PECI Agent 6",
 359        "PECI Agent 7",
 360        "PCH_CHIP_CPU_MAX_TEMP",
 361        "PCH_CHIP_TEMP",
 362        "PCH_CPU_TEMP",
 363        "PCH_MCH_TEMP",
 364        "PCH_DIM0_TEMP",
 365        "PCH_DIM1_TEMP",
 366        "PCH_DIM2_TEMP",
 367        "PCH_DIM3_TEMP"
 368};
 369
 370#define NCT6775_TEMP_MASK       0x001ffffe
 371#define NCT6775_VIRT_TEMP_MASK  0x00000000
 372
 373static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
 374        [13] = 0x661,
 375        [14] = 0x662,
 376        [15] = 0x664,
 377};
 378
 379static const u16 NCT6775_REG_TEMP_CRIT[32] = {
 380        [4] = 0xa00,
 381        [5] = 0xa01,
 382        [6] = 0xa02,
 383        [7] = 0xa03,
 384        [8] = 0xa04,
 385        [9] = 0xa05,
 386        [10] = 0xa06,
 387        [11] = 0xa07
 388};
 389
 390/* NCT6776 specific data */
 391
 392/* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
 393#define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
 394#define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
 395
 396static const s8 NCT6776_ALARM_BITS[] = {
 397        0, 1, 2, 3, 8, 21, 20, 16,      /* in0.. in7 */
 398        17, -1, -1, -1, -1, -1, -1,     /* in8..in14 */
 399        -1,                             /* unused */
 400        6, 7, 11, 10, 23,               /* fan1..fan5 */
 401        -1, -1, -1,                     /* unused */
 402        4, 5, 13, -1, -1, -1,           /* temp1..temp6 */
 403        12, 9 };                        /* intrusion0, intrusion1 */
 404
 405static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
 406
 407static const s8 NCT6776_BEEP_BITS[] = {
 408        0, 1, 2, 3, 4, 5, 6, 7,         /* in0.. in7 */
 409        8, -1, -1, -1, -1, -1, -1,      /* in8..in14 */
 410        24,                             /* global beep enable */
 411        25, 26, 27, 28, 29,             /* fan1..fan5 */
 412        -1, -1, -1,                     /* unused */
 413        16, 17, 18, 19, 20, 21,         /* temp1..temp6 */
 414        30, 31 };                       /* intrusion0, intrusion1 */
 415
 416static const u16 NCT6776_REG_TOLERANCE_H[] = {
 417        0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
 418
 419static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
 420static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
 421
 422static const u16 NCT6776_REG_FAN_MIN[] = {
 423        0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
 424static const u16 NCT6776_REG_FAN_PULSES[NUM_FAN] = {
 425        0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
 426
 427static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
 428        0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
 429
 430static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
 431        0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
 432
 433static const char *const nct6776_temp_label[] = {
 434        "",
 435        "SYSTIN",
 436        "CPUTIN",
 437        "AUXTIN",
 438        "SMBUSMASTER 0",
 439        "SMBUSMASTER 1",
 440        "SMBUSMASTER 2",
 441        "SMBUSMASTER 3",
 442        "SMBUSMASTER 4",
 443        "SMBUSMASTER 5",
 444        "SMBUSMASTER 6",
 445        "SMBUSMASTER 7",
 446        "PECI Agent 0",
 447        "PECI Agent 1",
 448        "PCH_CHIP_CPU_MAX_TEMP",
 449        "PCH_CHIP_TEMP",
 450        "PCH_CPU_TEMP",
 451        "PCH_MCH_TEMP",
 452        "PCH_DIM0_TEMP",
 453        "PCH_DIM1_TEMP",
 454        "PCH_DIM2_TEMP",
 455        "PCH_DIM3_TEMP",
 456        "BYTE_TEMP"
 457};
 458
 459#define NCT6776_TEMP_MASK       0x007ffffe
 460#define NCT6776_VIRT_TEMP_MASK  0x00000000
 461
 462static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
 463        [14] = 0x401,
 464        [15] = 0x402,
 465        [16] = 0x404,
 466};
 467
 468static const u16 NCT6776_REG_TEMP_CRIT[32] = {
 469        [11] = 0x709,
 470        [12] = 0x70a,
 471};
 472
 473/* NCT6779 specific data */
 474
 475static const u16 NCT6779_REG_IN[] = {
 476        0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
 477        0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
 478
 479static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
 480        0x459, 0x45A, 0x45B, 0x568 };
 481
 482static const s8 NCT6779_ALARM_BITS[] = {
 483        0, 1, 2, 3, 8, 21, 20, 16,      /* in0.. in7 */
 484        17, 24, 25, 26, 27, 28, 29,     /* in8..in14 */
 485        -1,                             /* unused */
 486        6, 7, 11, 10, 23,               /* fan1..fan5 */
 487        -1, -1, -1,                     /* unused */
 488        4, 5, 13, -1, -1, -1,           /* temp1..temp6 */
 489        12, 9 };                        /* intrusion0, intrusion1 */
 490
 491static const s8 NCT6779_BEEP_BITS[] = {
 492        0, 1, 2, 3, 4, 5, 6, 7,         /* in0.. in7 */
 493        8, 9, 10, 11, 12, 13, 14,       /* in8..in14 */
 494        24,                             /* global beep enable */
 495        25, 26, 27, 28, 29,             /* fan1..fan5 */
 496        -1, -1, -1,                     /* unused */
 497        16, 17, -1, -1, -1, -1,         /* temp1..temp6 */
 498        30, 31 };                       /* intrusion0, intrusion1 */
 499
 500static const u16 NCT6779_REG_FAN[] = {
 501        0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
 502static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
 503        0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0x64f };
 504
 505static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
 506        0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
 507#define NCT6779_CRITICAL_PWM_ENABLE_MASK        0x01
 508static const u16 NCT6779_REG_CRITICAL_PWM[] = {
 509        0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
 510
 511static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
 512static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
 513static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
 514        0x18, 0x152 };
 515static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
 516        0x3a, 0x153 };
 517static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
 518        0x39, 0x155 };
 519
 520static const u16 NCT6779_REG_TEMP_OFFSET[] = {
 521        0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
 522
 523static const char *const nct6779_temp_label[] = {
 524        "",
 525        "SYSTIN",
 526        "CPUTIN",
 527        "AUXTIN0",
 528        "AUXTIN1",
 529        "AUXTIN2",
 530        "AUXTIN3",
 531        "",
 532        "SMBUSMASTER 0",
 533        "SMBUSMASTER 1",
 534        "SMBUSMASTER 2",
 535        "SMBUSMASTER 3",
 536        "SMBUSMASTER 4",
 537        "SMBUSMASTER 5",
 538        "SMBUSMASTER 6",
 539        "SMBUSMASTER 7",
 540        "PECI Agent 0",
 541        "PECI Agent 1",
 542        "PCH_CHIP_CPU_MAX_TEMP",
 543        "PCH_CHIP_TEMP",
 544        "PCH_CPU_TEMP",
 545        "PCH_MCH_TEMP",
 546        "PCH_DIM0_TEMP",
 547        "PCH_DIM1_TEMP",
 548        "PCH_DIM2_TEMP",
 549        "PCH_DIM3_TEMP",
 550        "BYTE_TEMP",
 551        "",
 552        "",
 553        "",
 554        "",
 555        "Virtual_TEMP"
 556};
 557
 558#define NCT6779_TEMP_MASK       0x07ffff7e
 559#define NCT6779_VIRT_TEMP_MASK  0x00000000
 560#define NCT6791_TEMP_MASK       0x87ffff7e
 561#define NCT6791_VIRT_TEMP_MASK  0x80000000
 562
 563static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
 564        = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
 565            0, 0, 0, 0, 0, 0, 0, 0,
 566            0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
 567            0x408, 0 };
 568
 569static const u16 NCT6779_REG_TEMP_CRIT[32] = {
 570        [15] = 0x709,
 571        [16] = 0x70a,
 572};
 573
 574/* NCT6791 specific data */
 575
 576#define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE     0x28
 577
 578static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
 579static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
 580static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
 581static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
 582static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
 583static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
 584
 585static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
 586        0x459, 0x45A, 0x45B, 0x568, 0x45D };
 587
 588static const s8 NCT6791_ALARM_BITS[] = {
 589        0, 1, 2, 3, 8, 21, 20, 16,      /* in0.. in7 */
 590        17, 24, 25, 26, 27, 28, 29,     /* in8..in14 */
 591        -1,                             /* unused */
 592        6, 7, 11, 10, 23, 33,           /* fan1..fan6 */
 593        -1, -1,                         /* unused */
 594        4, 5, 13, -1, -1, -1,           /* temp1..temp6 */
 595        12, 9 };                        /* intrusion0, intrusion1 */
 596
 597/* NCT6792/NCT6793 specific data */
 598
 599static const u16 NCT6792_REG_TEMP_MON[] = {
 600        0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
 601static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
 602        0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
 603
 604static const char *const nct6792_temp_label[] = {
 605        "",
 606        "SYSTIN",
 607        "CPUTIN",
 608        "AUXTIN0",
 609        "AUXTIN1",
 610        "AUXTIN2",
 611        "AUXTIN3",
 612        "",
 613        "SMBUSMASTER 0",
 614        "SMBUSMASTER 1",
 615        "SMBUSMASTER 2",
 616        "SMBUSMASTER 3",
 617        "SMBUSMASTER 4",
 618        "SMBUSMASTER 5",
 619        "SMBUSMASTER 6",
 620        "SMBUSMASTER 7",
 621        "PECI Agent 0",
 622        "PECI Agent 1",
 623        "PCH_CHIP_CPU_MAX_TEMP",
 624        "PCH_CHIP_TEMP",
 625        "PCH_CPU_TEMP",
 626        "PCH_MCH_TEMP",
 627        "PCH_DIM0_TEMP",
 628        "PCH_DIM1_TEMP",
 629        "PCH_DIM2_TEMP",
 630        "PCH_DIM3_TEMP",
 631        "BYTE_TEMP",
 632        "PECI Agent 0 Calibration",
 633        "PECI Agent 1 Calibration",
 634        "",
 635        "",
 636        "Virtual_TEMP"
 637};
 638
 639#define NCT6792_TEMP_MASK       0x9fffff7e
 640#define NCT6792_VIRT_TEMP_MASK  0x80000000
 641
 642static const char *const nct6793_temp_label[] = {
 643        "",
 644        "SYSTIN",
 645        "CPUTIN",
 646        "AUXTIN0",
 647        "AUXTIN1",
 648        "AUXTIN2",
 649        "AUXTIN3",
 650        "",
 651        "SMBUSMASTER 0",
 652        "SMBUSMASTER 1",
 653        "",
 654        "",
 655        "",
 656        "",
 657        "",
 658        "",
 659        "PECI Agent 0",
 660        "PECI Agent 1",
 661        "PCH_CHIP_CPU_MAX_TEMP",
 662        "PCH_CHIP_TEMP",
 663        "PCH_CPU_TEMP",
 664        "PCH_MCH_TEMP",
 665        "Agent0 Dimm0 ",
 666        "Agent0 Dimm1",
 667        "Agent1 Dimm0",
 668        "Agent1 Dimm1",
 669        "BYTE_TEMP0",
 670        "BYTE_TEMP1",
 671        "PECI Agent 0 Calibration",
 672        "PECI Agent 1 Calibration",
 673        "",
 674        "Virtual_TEMP"
 675};
 676
 677#define NCT6793_TEMP_MASK       0xbfff037e
 678#define NCT6793_VIRT_TEMP_MASK  0x80000000
 679
 680static const char *const nct6795_temp_label[] = {
 681        "",
 682        "SYSTIN",
 683        "CPUTIN",
 684        "AUXTIN0",
 685        "AUXTIN1",
 686        "AUXTIN2",
 687        "AUXTIN3",
 688        "",
 689        "SMBUSMASTER 0",
 690        "SMBUSMASTER 1",
 691        "SMBUSMASTER 2",
 692        "SMBUSMASTER 3",
 693        "SMBUSMASTER 4",
 694        "SMBUSMASTER 5",
 695        "SMBUSMASTER 6",
 696        "SMBUSMASTER 7",
 697        "PECI Agent 0",
 698        "PECI Agent 1",
 699        "PCH_CHIP_CPU_MAX_TEMP",
 700        "PCH_CHIP_TEMP",
 701        "PCH_CPU_TEMP",
 702        "PCH_MCH_TEMP",
 703        "Agent0 Dimm0",
 704        "Agent0 Dimm1",
 705        "Agent1 Dimm0",
 706        "Agent1 Dimm1",
 707        "BYTE_TEMP0",
 708        "BYTE_TEMP1",
 709        "PECI Agent 0 Calibration",
 710        "PECI Agent 1 Calibration",
 711        "",
 712        "Virtual_TEMP"
 713};
 714
 715#define NCT6795_TEMP_MASK       0xbfffff7e
 716#define NCT6795_VIRT_TEMP_MASK  0x80000000
 717
 718static const char *const nct6796_temp_label[] = {
 719        "",
 720        "SYSTIN",
 721        "CPUTIN",
 722        "AUXTIN0",
 723        "AUXTIN1",
 724        "AUXTIN2",
 725        "AUXTIN3",
 726        "AUXTIN4",
 727        "SMBUSMASTER 0",
 728        "SMBUSMASTER 1",
 729        "Virtual_TEMP",
 730        "Virtual_TEMP",
 731        "",
 732        "",
 733        "",
 734        "",
 735        "PECI Agent 0",
 736        "PECI Agent 1",
 737        "PCH_CHIP_CPU_MAX_TEMP",
 738        "PCH_CHIP_TEMP",
 739        "PCH_CPU_TEMP",
 740        "PCH_MCH_TEMP",
 741        "Agent0 Dimm0",
 742        "Agent0 Dimm1",
 743        "Agent1 Dimm0",
 744        "Agent1 Dimm1",
 745        "BYTE_TEMP0",
 746        "BYTE_TEMP1",
 747        "PECI Agent 0 Calibration",
 748        "PECI Agent 1 Calibration",
 749        "",
 750        "Virtual_TEMP"
 751};
 752
 753#define NCT6796_TEMP_MASK       0xbfff0ffe
 754#define NCT6796_VIRT_TEMP_MASK  0x80000c00
 755
 756static const char *const nct6798_temp_label[] = {
 757        "",
 758        "SYSTIN",
 759        "CPUTIN",
 760        "AUXTIN0",
 761        "AUXTIN1",
 762        "AUXTIN2",
 763        "AUXTIN3",
 764        "AUXTIN4",
 765        "SMBUSMASTER 0",
 766        "SMBUSMASTER 1",
 767        "Virtual_TEMP",
 768        "Virtual_TEMP",
 769        "",
 770        "",
 771        "",
 772        "",
 773        "PECI Agent 0",
 774        "PECI Agent 1",
 775        "PCH_CHIP_CPU_MAX_TEMP",
 776        "PCH_CHIP_TEMP",
 777        "PCH_CPU_TEMP",
 778        "PCH_MCH_TEMP",
 779        "Agent0 Dimm0",
 780        "Agent0 Dimm1",
 781        "Agent1 Dimm0",
 782        "Agent1 Dimm1",
 783        "BYTE_TEMP0",
 784        "BYTE_TEMP1",
 785        "",
 786        "",
 787        "",
 788        "Virtual_TEMP"
 789};
 790
 791#define NCT6798_TEMP_MASK       0x8fff0ffe
 792#define NCT6798_VIRT_TEMP_MASK  0x80000c00
 793
 794/* NCT6102D/NCT6106D specific data */
 795
 796#define NCT6106_REG_VBAT        0x318
 797#define NCT6106_REG_DIODE       0x319
 798#define NCT6106_DIODE_MASK      0x01
 799
 800static const u16 NCT6106_REG_IN_MAX[] = {
 801        0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
 802static const u16 NCT6106_REG_IN_MIN[] = {
 803        0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
 804static const u16 NCT6106_REG_IN[] = {
 805        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
 806
 807static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
 808static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
 809static const u16 NCT6106_REG_TEMP_HYST[] = {
 810        0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
 811static const u16 NCT6106_REG_TEMP_OVER[] = {
 812        0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
 813static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
 814        0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
 815static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
 816        0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
 817static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
 818static const u16 NCT6106_REG_TEMP_CONFIG[] = {
 819        0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
 820
 821static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
 822static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
 823static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };
 824static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };
 825
 826static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
 827static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
 828static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
 829static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
 830static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
 831static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
 832static const u16 NCT6106_REG_TEMP_SOURCE[] = {
 833        0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
 834
 835static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
 836static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
 837        0x11b, 0x12b, 0x13b };
 838
 839static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
 840#define NCT6106_CRITICAL_PWM_ENABLE_MASK        0x10
 841static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
 842
 843static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
 844static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
 845static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
 846static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
 847static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
 848static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
 849
 850static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
 851
 852static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
 853static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
 854static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
 855static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x18b };
 856static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
 857static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
 858
 859static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
 860static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
 861
 862static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
 863        0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
 864
 865static const s8 NCT6106_ALARM_BITS[] = {
 866        0, 1, 2, 3, 4, 5, 7, 8,         /* in0.. in7 */
 867        9, -1, -1, -1, -1, -1, -1,      /* in8..in14 */
 868        -1,                             /* unused */
 869        32, 33, 34, -1, -1,             /* fan1..fan5 */
 870        -1, -1, -1,                     /* unused */
 871        16, 17, 18, 19, 20, 21,         /* temp1..temp6 */
 872        48, -1                          /* intrusion0, intrusion1 */
 873};
 874
 875static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
 876        0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
 877
 878static const s8 NCT6106_BEEP_BITS[] = {
 879        0, 1, 2, 3, 4, 5, 7, 8,         /* in0.. in7 */
 880        9, 10, 11, 12, -1, -1, -1,      /* in8..in14 */
 881        32,                             /* global beep enable */
 882        24, 25, 26, 27, 28,             /* fan1..fan5 */
 883        -1, -1, -1,                     /* unused */
 884        16, 17, 18, 19, 20, 21,         /* temp1..temp6 */
 885        34, -1                          /* intrusion0, intrusion1 */
 886};
 887
 888static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
 889        [14] = 0x51,
 890        [15] = 0x52,
 891        [16] = 0x54,
 892};
 893
 894static const u16 NCT6106_REG_TEMP_CRIT[32] = {
 895        [11] = 0x204,
 896        [12] = 0x205,
 897};
 898
 899static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
 900{
 901        if (mode == 0 && pwm == 255)
 902                return off;
 903        return mode + 1;
 904}
 905
 906static int pwm_enable_to_reg(enum pwm_enable mode)
 907{
 908        if (mode == off)
 909                return 0;
 910        return mode - 1;
 911}
 912
 913/*
 914 * Conversions
 915 */
 916
 917/* 1 is DC mode, output in ms */
 918static unsigned int step_time_from_reg(u8 reg, u8 mode)
 919{
 920        return mode ? 400 * reg : 100 * reg;
 921}
 922
 923static u8 step_time_to_reg(unsigned int msec, u8 mode)
 924{
 925        return clamp_val((mode ? (msec + 200) / 400 :
 926                                        (msec + 50) / 100), 1, 255);
 927}
 928
 929static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
 930{
 931        if (reg == 0 || reg == 255)
 932                return 0;
 933        return 1350000U / (reg << divreg);
 934}
 935
 936static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
 937{
 938        if ((reg & 0xff1f) == 0xff1f)
 939                return 0;
 940
 941        reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
 942
 943        if (reg == 0)
 944                return 0;
 945
 946        return 1350000U / reg;
 947}
 948
 949static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
 950{
 951        if (reg == 0 || reg == 0xffff)
 952                return 0;
 953
 954        /*
 955         * Even though the registers are 16 bit wide, the fan divisor
 956         * still applies.
 957         */
 958        return 1350000U / (reg << divreg);
 959}
 960
 961static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg)
 962{
 963        return reg;
 964}
 965
 966static u16 fan_to_reg(u32 fan, unsigned int divreg)
 967{
 968        if (!fan)
 969                return 0;
 970
 971        return (1350000U / fan) >> divreg;
 972}
 973
 974static inline unsigned int
 975div_from_reg(u8 reg)
 976{
 977        return BIT(reg);
 978}
 979
 980/*
 981 * Some of the voltage inputs have internal scaling, the tables below
 982 * contain 8 (the ADC LSB in mV) * scaling factor * 100
 983 */
 984static const u16 scale_in[15] = {
 985        800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
 986        800, 800
 987};
 988
 989static inline long in_from_reg(u8 reg, u8 nr)
 990{
 991        return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
 992}
 993
 994static inline u8 in_to_reg(u32 val, u8 nr)
 995{
 996        return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
 997}
 998
 999/*
1000 * Data structures and manipulation thereof
1001 */
1002
1003struct nct6775_data {
1004        int addr;       /* IO base of hw monitor block */
1005        int sioreg;     /* SIO register address */
1006        enum kinds kind;
1007        const char *name;
1008
1009        const struct attribute_group *groups[6];
1010
1011        u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1012                                    * 3=temp_crit, 4=temp_lcrit
1013                                    */
1014        u8 temp_src[NUM_TEMP];
1015        u16 reg_temp_config[NUM_TEMP];
1016        const char * const *temp_label;
1017        u32 temp_mask;
1018        u32 virt_temp_mask;
1019
1020        u16 REG_CONFIG;
1021        u16 REG_VBAT;
1022        u16 REG_DIODE;
1023        u8 DIODE_MASK;
1024
1025        const s8 *ALARM_BITS;
1026        const s8 *BEEP_BITS;
1027
1028        const u16 *REG_VIN;
1029        const u16 *REG_IN_MINMAX[2];
1030
1031        const u16 *REG_TARGET;
1032        const u16 *REG_FAN;
1033        const u16 *REG_FAN_MODE;
1034        const u16 *REG_FAN_MIN;
1035        const u16 *REG_FAN_PULSES;
1036        const u16 *FAN_PULSE_SHIFT;
1037        const u16 *REG_FAN_TIME[3];
1038
1039        const u16 *REG_TOLERANCE_H;
1040
1041        const u8 *REG_PWM_MODE;
1042        const u8 *PWM_MODE_MASK;
1043
1044        const u16 *REG_PWM[7];  /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1045                                 * [3]=pwm_max, [4]=pwm_step,
1046                                 * [5]=weight_duty_step, [6]=weight_duty_base
1047                                 */
1048        const u16 *REG_PWM_READ;
1049
1050        const u16 *REG_CRITICAL_PWM_ENABLE;
1051        u8 CRITICAL_PWM_ENABLE_MASK;
1052        const u16 *REG_CRITICAL_PWM;
1053
1054        const u16 *REG_AUTO_TEMP;
1055        const u16 *REG_AUTO_PWM;
1056
1057        const u16 *REG_CRITICAL_TEMP;
1058        const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1059
1060        const u16 *REG_TEMP_SOURCE;     /* temp register sources */
1061        const u16 *REG_TEMP_SEL;
1062        const u16 *REG_WEIGHT_TEMP_SEL;
1063        const u16 *REG_WEIGHT_TEMP[3];  /* 0=base, 1=tolerance, 2=step */
1064
1065        const u16 *REG_TEMP_OFFSET;
1066
1067        const u16 *REG_ALARM;
1068        const u16 *REG_BEEP;
1069
1070        unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1071        unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1072
1073        struct mutex update_lock;
1074        bool valid;             /* true if following fields are valid */
1075        unsigned long last_updated;     /* In jiffies */
1076
1077        /* Register values */
1078        u8 bank;                /* current register bank */
1079        u8 in_num;              /* number of in inputs we have */
1080        u8 in[15][3];           /* [0]=in, [1]=in_max, [2]=in_min */
1081        unsigned int rpm[NUM_FAN];
1082        u16 fan_min[NUM_FAN];
1083        u8 fan_pulses[NUM_FAN];
1084        u8 fan_div[NUM_FAN];
1085        u8 has_pwm;
1086        u8 has_fan;             /* some fan inputs can be disabled */
1087        u8 has_fan_min;         /* some fans don't have min register */
1088        bool has_fan_div;
1089
1090        u8 num_temp_alarms;     /* 2, 3, or 6 */
1091        u8 num_temp_beeps;      /* 2, 3, or 6 */
1092        u8 temp_fixed_num;      /* 3 or 6 */
1093        u8 temp_type[NUM_TEMP_FIXED];
1094        s8 temp_offset[NUM_TEMP_FIXED];
1095        s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1096                                * 3=temp_crit, 4=temp_lcrit */
1097        u64 alarms;
1098        u64 beeps;
1099
1100        u8 pwm_num;     /* number of pwm */
1101        u8 pwm_mode[NUM_FAN];   /* 0->DC variable voltage,
1102                                 * 1->PWM variable duty cycle
1103                                 */
1104        enum pwm_enable pwm_enable[NUM_FAN];
1105                        /* 0->off
1106                         * 1->manual
1107                         * 2->thermal cruise mode (also called SmartFan I)
1108                         * 3->fan speed cruise mode
1109                         * 4->SmartFan III
1110                         * 5->enhanced variable thermal cruise (SmartFan IV)
1111                         */
1112        u8 pwm[7][NUM_FAN];     /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1113                                 * [3]=pwm_max, [4]=pwm_step,
1114                                 * [5]=weight_duty_step, [6]=weight_duty_base
1115                                 */
1116
1117        u8 target_temp[NUM_FAN];
1118        u8 target_temp_mask;
1119        u32 target_speed[NUM_FAN];
1120        u32 target_speed_tolerance[NUM_FAN];
1121        u8 speed_tolerance_limit;
1122
1123        u8 temp_tolerance[2][NUM_FAN];
1124        u8 tolerance_mask;
1125
1126        u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1127
1128        /* Automatic fan speed control registers */
1129        int auto_pwm_num;
1130        u8 auto_pwm[NUM_FAN][7];
1131        u8 auto_temp[NUM_FAN][7];
1132        u8 pwm_temp_sel[NUM_FAN];
1133        u8 pwm_weight_temp_sel[NUM_FAN];
1134        u8 weight_temp[3][NUM_FAN];     /* 0->temp_step, 1->temp_step_tol,
1135                                         * 2->temp_base
1136                                         */
1137
1138        u8 vid;
1139        u8 vrm;
1140
1141        bool have_vid;
1142
1143        u16 have_temp;
1144        u16 have_temp_fixed;
1145        u16 have_in;
1146
1147        /* Remember extra register values over suspend/resume */
1148        u8 vbat;
1149        u8 fandiv1;
1150        u8 fandiv2;
1151        u8 sio_reg_enable;
1152};
1153
1154struct nct6775_sio_data {
1155        int sioreg;
1156        enum kinds kind;
1157};
1158
1159struct sensor_device_template {
1160        struct device_attribute dev_attr;
1161        union {
1162                struct {
1163                        u8 nr;
1164                        u8 index;
1165                } s;
1166                int index;
1167        } u;
1168        bool s2;        /* true if both index and nr are used */
1169};
1170
1171struct sensor_device_attr_u {
1172        union {
1173                struct sensor_device_attribute a1;
1174                struct sensor_device_attribute_2 a2;
1175        } u;
1176        char name[32];
1177};
1178
1179#define __TEMPLATE_ATTR(_template, _mode, _show, _store) {      \
1180        .attr = {.name = _template, .mode = _mode },            \
1181        .show   = _show,                                        \
1182        .store  = _store,                                       \
1183}
1184
1185#define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1186        { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1187          .u.index = _index,                                            \
1188          .s2 = false }
1189
1190#define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store,       \
1191                                 _nr, _index)                           \
1192        { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1193          .u.s.index = _index,                                          \
1194          .u.s.nr = _nr,                                                \
1195          .s2 = true }
1196
1197#define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1198static struct sensor_device_template sensor_dev_template_##_name        \
1199        = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store,       \
1200                                 _index)
1201
1202#define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store,       \
1203                          _nr, _index)                                  \
1204static struct sensor_device_template sensor_dev_template_##_name        \
1205        = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store,     \
1206                                 _nr, _index)
1207
1208struct sensor_template_group {
1209        struct sensor_device_template **templates;
1210        umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1211        int base;
1212};
1213
1214static struct attribute_group *
1215nct6775_create_attr_group(struct device *dev,
1216                          const struct sensor_template_group *tg,
1217                          int repeat)
1218{
1219        struct attribute_group *group;
1220        struct sensor_device_attr_u *su;
1221        struct sensor_device_attribute *a;
1222        struct sensor_device_attribute_2 *a2;
1223        struct attribute **attrs;
1224        struct sensor_device_template **t;
1225        int i, count;
1226
1227        if (repeat <= 0)
1228                return ERR_PTR(-EINVAL);
1229
1230        t = tg->templates;
1231        for (count = 0; *t; t++, count++)
1232                ;
1233
1234        if (count == 0)
1235                return ERR_PTR(-EINVAL);
1236
1237        group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1238        if (group == NULL)
1239                return ERR_PTR(-ENOMEM);
1240
1241        attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1242                             GFP_KERNEL);
1243        if (attrs == NULL)
1244                return ERR_PTR(-ENOMEM);
1245
1246        su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1247                               GFP_KERNEL);
1248        if (su == NULL)
1249                return ERR_PTR(-ENOMEM);
1250
1251        group->attrs = attrs;
1252        group->is_visible = tg->is_visible;
1253
1254        for (i = 0; i < repeat; i++) {
1255                t = tg->templates;
1256                while (*t != NULL) {
1257                        snprintf(su->name, sizeof(su->name),
1258                                 (*t)->dev_attr.attr.name, tg->base + i);
1259                        if ((*t)->s2) {
1260                                a2 = &su->u.a2;
1261                                sysfs_attr_init(&a2->dev_attr.attr);
1262                                a2->dev_attr.attr.name = su->name;
1263                                a2->nr = (*t)->u.s.nr + i;
1264                                a2->index = (*t)->u.s.index;
1265                                a2->dev_attr.attr.mode =
1266                                  (*t)->dev_attr.attr.mode;
1267                                a2->dev_attr.show = (*t)->dev_attr.show;
1268                                a2->dev_attr.store = (*t)->dev_attr.store;
1269                                *attrs = &a2->dev_attr.attr;
1270                        } else {
1271                                a = &su->u.a1;
1272                                sysfs_attr_init(&a->dev_attr.attr);
1273                                a->dev_attr.attr.name = su->name;
1274                                a->index = (*t)->u.index + i;
1275                                a->dev_attr.attr.mode =
1276                                  (*t)->dev_attr.attr.mode;
1277                                a->dev_attr.show = (*t)->dev_attr.show;
1278                                a->dev_attr.store = (*t)->dev_attr.store;
1279                                *attrs = &a->dev_attr.attr;
1280                        }
1281                        attrs++;
1282                        su++;
1283                        t++;
1284                }
1285        }
1286
1287        return group;
1288}
1289
1290static bool is_word_sized(struct nct6775_data *data, u16 reg)
1291{
1292        switch (data->kind) {
1293        case nct6106:
1294                return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1295                  reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1296                  reg == 0x111 || reg == 0x121 || reg == 0x131;
1297        case nct6775:
1298                return (((reg & 0xff00) == 0x100 ||
1299                    (reg & 0xff00) == 0x200) &&
1300                   ((reg & 0x00ff) == 0x50 ||
1301                    (reg & 0x00ff) == 0x53 ||
1302                    (reg & 0x00ff) == 0x55)) ||
1303                  (reg & 0xfff0) == 0x630 ||
1304                  reg == 0x640 || reg == 0x642 ||
1305                  reg == 0x662 ||
1306                  ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1307                  reg == 0x73 || reg == 0x75 || reg == 0x77;
1308        case nct6776:
1309                return (((reg & 0xff00) == 0x100 ||
1310                    (reg & 0xff00) == 0x200) &&
1311                   ((reg & 0x00ff) == 0x50 ||
1312                    (reg & 0x00ff) == 0x53 ||
1313                    (reg & 0x00ff) == 0x55)) ||
1314                  (reg & 0xfff0) == 0x630 ||
1315                  reg == 0x402 ||
1316                  reg == 0x640 || reg == 0x642 ||
1317                  ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1318                  reg == 0x73 || reg == 0x75 || reg == 0x77;
1319        case nct6779:
1320        case nct6791:
1321        case nct6792:
1322        case nct6793:
1323        case nct6795:
1324        case nct6796:
1325        case nct6797:
1326        case nct6798:
1327                return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1328                  (reg & 0xfff0) == 0x4c0 ||
1329                  reg == 0x402 ||
1330                  reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1331                  reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1332                  reg == 0x64c ||
1333                  reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1334                  reg == 0x7b || reg == 0x7d;
1335        }
1336        return false;
1337}
1338
1339/*
1340 * On older chips, only registers 0x50-0x5f are banked.
1341 * On more recent chips, all registers are banked.
1342 * Assume that is the case and set the bank number for each access.
1343 * Cache the bank number so it only needs to be set if it changes.
1344 */
1345static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1346{
1347        u8 bank = reg >> 8;
1348
1349        if (data->bank != bank) {
1350                outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1351                outb_p(bank, data->addr + DATA_REG_OFFSET);
1352                data->bank = bank;
1353        }
1354}
1355
1356static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1357{
1358        int res, word_sized = is_word_sized(data, reg);
1359
1360        nct6775_set_bank(data, reg);
1361        outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1362        res = inb_p(data->addr + DATA_REG_OFFSET);
1363        if (word_sized) {
1364                outb_p((reg & 0xff) + 1,
1365                       data->addr + ADDR_REG_OFFSET);
1366                res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1367        }
1368        return res;
1369}
1370
1371static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1372{
1373        int word_sized = is_word_sized(data, reg);
1374
1375        nct6775_set_bank(data, reg);
1376        outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1377        if (word_sized) {
1378                outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1379                outb_p((reg & 0xff) + 1,
1380                       data->addr + ADDR_REG_OFFSET);
1381        }
1382        outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1383        return 0;
1384}
1385
1386/* We left-align 8-bit temperature values to make the code simpler */
1387static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1388{
1389        u16 res;
1390
1391        res = nct6775_read_value(data, reg);
1392        if (!is_word_sized(data, reg))
1393                res <<= 8;
1394
1395        return res;
1396}
1397
1398static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1399{
1400        if (!is_word_sized(data, reg))
1401                value >>= 8;
1402        return nct6775_write_value(data, reg, value);
1403}
1404
1405/* This function assumes that the caller holds data->update_lock */
1406static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1407{
1408        u8 reg;
1409
1410        switch (nr) {
1411        case 0:
1412                reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1413                    | (data->fan_div[0] & 0x7);
1414                nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1415                break;
1416        case 1:
1417                reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1418                    | ((data->fan_div[1] << 4) & 0x70);
1419                nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1420                break;
1421        case 2:
1422                reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1423                    | (data->fan_div[2] & 0x7);
1424                nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1425                break;
1426        case 3:
1427                reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1428                    | ((data->fan_div[3] << 4) & 0x70);
1429                nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1430                break;
1431        }
1432}
1433
1434static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1435{
1436        if (data->kind == nct6775)
1437                nct6775_write_fan_div(data, nr);
1438}
1439
1440static void nct6775_update_fan_div(struct nct6775_data *data)
1441{
1442        u8 i;
1443
1444        i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1445        data->fan_div[0] = i & 0x7;
1446        data->fan_div[1] = (i & 0x70) >> 4;
1447        i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1448        data->fan_div[2] = i & 0x7;
1449        if (data->has_fan & BIT(3))
1450                data->fan_div[3] = (i & 0x70) >> 4;
1451}
1452
1453static void nct6775_update_fan_div_common(struct nct6775_data *data)
1454{
1455        if (data->kind == nct6775)
1456                nct6775_update_fan_div(data);
1457}
1458
1459static void nct6775_init_fan_div(struct nct6775_data *data)
1460{
1461        int i;
1462
1463        nct6775_update_fan_div_common(data);
1464        /*
1465         * For all fans, start with highest divider value if the divider
1466         * register is not initialized. This ensures that we get a
1467         * reading from the fan count register, even if it is not optimal.
1468         * We'll compute a better divider later on.
1469         */
1470        for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1471                if (!(data->has_fan & BIT(i)))
1472                        continue;
1473                if (data->fan_div[i] == 0) {
1474                        data->fan_div[i] = 7;
1475                        nct6775_write_fan_div_common(data, i);
1476                }
1477        }
1478}
1479
1480static void nct6775_init_fan_common(struct device *dev,
1481                                    struct nct6775_data *data)
1482{
1483        int i;
1484        u8 reg;
1485
1486        if (data->has_fan_div)
1487                nct6775_init_fan_div(data);
1488
1489        /*
1490         * If fan_min is not set (0), set it to 0xff to disable it. This
1491         * prevents the unnecessary warning when fanX_min is reported as 0.
1492         */
1493        for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1494                if (data->has_fan_min & BIT(i)) {
1495                        reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1496                        if (!reg)
1497                                nct6775_write_value(data, data->REG_FAN_MIN[i],
1498                                                    data->has_fan_div ? 0xff
1499                                                                      : 0xff1f);
1500                }
1501        }
1502}
1503
1504static void nct6775_select_fan_div(struct device *dev,
1505                                   struct nct6775_data *data, int nr, u16 reg)
1506{
1507        u8 fan_div = data->fan_div[nr];
1508        u16 fan_min;
1509
1510        if (!data->has_fan_div)
1511                return;
1512
1513        /*
1514         * If we failed to measure the fan speed, or the reported value is not
1515         * in the optimal range, and the clock divider can be modified,
1516         * let's try that for next time.
1517         */
1518        if (reg == 0x00 && fan_div < 0x07)
1519                fan_div++;
1520        else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1521                fan_div--;
1522
1523        if (fan_div != data->fan_div[nr]) {
1524                dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1525                        nr + 1, div_from_reg(data->fan_div[nr]),
1526                        div_from_reg(fan_div));
1527
1528                /* Preserve min limit if possible */
1529                if (data->has_fan_min & BIT(nr)) {
1530                        fan_min = data->fan_min[nr];
1531                        if (fan_div > data->fan_div[nr]) {
1532                                if (fan_min != 255 && fan_min > 1)
1533                                        fan_min >>= 1;
1534                        } else {
1535                                if (fan_min != 255) {
1536                                        fan_min <<= 1;
1537                                        if (fan_min > 254)
1538                                                fan_min = 254;
1539                                }
1540                        }
1541                        if (fan_min != data->fan_min[nr]) {
1542                                data->fan_min[nr] = fan_min;
1543                                nct6775_write_value(data, data->REG_FAN_MIN[nr],
1544                                                    fan_min);
1545                        }
1546                }
1547                data->fan_div[nr] = fan_div;
1548                nct6775_write_fan_div_common(data, nr);
1549        }
1550}
1551
1552static void nct6775_update_pwm(struct device *dev)
1553{
1554        struct nct6775_data *data = dev_get_drvdata(dev);
1555        int i, j;
1556        int fanmodecfg, reg;
1557        bool duty_is_dc;
1558
1559        for (i = 0; i < data->pwm_num; i++) {
1560                if (!(data->has_pwm & BIT(i)))
1561                        continue;
1562
1563                duty_is_dc = data->REG_PWM_MODE[i] &&
1564                  (nct6775_read_value(data, data->REG_PWM_MODE[i])
1565                   & data->PWM_MODE_MASK[i]);
1566                data->pwm_mode[i] = !duty_is_dc;
1567
1568                fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1569                for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1570                        if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1571                                data->pwm[j][i]
1572                                  = nct6775_read_value(data,
1573                                                       data->REG_PWM[j][i]);
1574                        }
1575                }
1576
1577                data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1578                                                        (fanmodecfg >> 4) & 7);
1579
1580                if (!data->temp_tolerance[0][i] ||
1581                    data->pwm_enable[i] != speed_cruise)
1582                        data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1583                if (!data->target_speed_tolerance[i] ||
1584                    data->pwm_enable[i] == speed_cruise) {
1585                        u8 t = fanmodecfg & 0x0f;
1586
1587                        if (data->REG_TOLERANCE_H) {
1588                                t |= (nct6775_read_value(data,
1589                                      data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1590                        }
1591                        data->target_speed_tolerance[i] = t;
1592                }
1593
1594                data->temp_tolerance[1][i] =
1595                        nct6775_read_value(data,
1596                                        data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1597
1598                reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1599                data->pwm_temp_sel[i] = reg & 0x1f;
1600                /* If fan can stop, report floor as 0 */
1601                if (reg & 0x80)
1602                        data->pwm[2][i] = 0;
1603
1604                if (!data->REG_WEIGHT_TEMP_SEL[i])
1605                        continue;
1606
1607                reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1608                data->pwm_weight_temp_sel[i] = reg & 0x1f;
1609                /* If weight is disabled, report weight source as 0 */
1610                if (!(reg & 0x80))
1611                        data->pwm_weight_temp_sel[i] = 0;
1612
1613                /* Weight temp data */
1614                for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1615                        data->weight_temp[j][i]
1616                          = nct6775_read_value(data,
1617                                               data->REG_WEIGHT_TEMP[j][i]);
1618                }
1619        }
1620}
1621
1622static void nct6775_update_pwm_limits(struct device *dev)
1623{
1624        struct nct6775_data *data = dev_get_drvdata(dev);
1625        int i, j;
1626        u8 reg;
1627        u16 reg_t;
1628
1629        for (i = 0; i < data->pwm_num; i++) {
1630                if (!(data->has_pwm & BIT(i)))
1631                        continue;
1632
1633                for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1634                        data->fan_time[j][i] =
1635                          nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1636                }
1637
1638                reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1639                /* Update only in matching mode or if never updated */
1640                if (!data->target_temp[i] ||
1641                    data->pwm_enable[i] == thermal_cruise)
1642                        data->target_temp[i] = reg_t & data->target_temp_mask;
1643                if (!data->target_speed[i] ||
1644                    data->pwm_enable[i] == speed_cruise) {
1645                        if (data->REG_TOLERANCE_H) {
1646                                reg_t |= (nct6775_read_value(data,
1647                                        data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1648                        }
1649                        data->target_speed[i] = reg_t;
1650                }
1651
1652                for (j = 0; j < data->auto_pwm_num; j++) {
1653                        data->auto_pwm[i][j] =
1654                          nct6775_read_value(data,
1655                                             NCT6775_AUTO_PWM(data, i, j));
1656                        data->auto_temp[i][j] =
1657                          nct6775_read_value(data,
1658                                             NCT6775_AUTO_TEMP(data, i, j));
1659                }
1660
1661                /* critical auto_pwm temperature data */
1662                data->auto_temp[i][data->auto_pwm_num] =
1663                        nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1664
1665                switch (data->kind) {
1666                case nct6775:
1667                        reg = nct6775_read_value(data,
1668                                                 NCT6775_REG_CRITICAL_ENAB[i]);
1669                        data->auto_pwm[i][data->auto_pwm_num] =
1670                                                (reg & 0x02) ? 0xff : 0x00;
1671                        break;
1672                case nct6776:
1673                        data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1674                        break;
1675                case nct6106:
1676                case nct6779:
1677                case nct6791:
1678                case nct6792:
1679                case nct6793:
1680                case nct6795:
1681                case nct6796:
1682                case nct6797:
1683                case nct6798:
1684                        reg = nct6775_read_value(data,
1685                                        data->REG_CRITICAL_PWM_ENABLE[i]);
1686                        if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1687                                reg = nct6775_read_value(data,
1688                                        data->REG_CRITICAL_PWM[i]);
1689                        else
1690                                reg = 0xff;
1691                        data->auto_pwm[i][data->auto_pwm_num] = reg;
1692                        break;
1693                }
1694        }
1695}
1696
1697static struct nct6775_data *nct6775_update_device(struct device *dev)
1698{
1699        struct nct6775_data *data = dev_get_drvdata(dev);
1700        int i, j;
1701
1702        mutex_lock(&data->update_lock);
1703
1704        if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1705            || !data->valid) {
1706                /* Fan clock dividers */
1707                nct6775_update_fan_div_common(data);
1708
1709                /* Measured voltages and limits */
1710                for (i = 0; i < data->in_num; i++) {
1711                        if (!(data->have_in & BIT(i)))
1712                                continue;
1713
1714                        data->in[i][0] = nct6775_read_value(data,
1715                                                            data->REG_VIN[i]);
1716                        data->in[i][1] = nct6775_read_value(data,
1717                                          data->REG_IN_MINMAX[0][i]);
1718                        data->in[i][2] = nct6775_read_value(data,
1719                                          data->REG_IN_MINMAX[1][i]);
1720                }
1721
1722                /* Measured fan speeds and limits */
1723                for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1724                        u16 reg;
1725
1726                        if (!(data->has_fan & BIT(i)))
1727                                continue;
1728
1729                        reg = nct6775_read_value(data, data->REG_FAN[i]);
1730                        data->rpm[i] = data->fan_from_reg(reg,
1731                                                          data->fan_div[i]);
1732
1733                        if (data->has_fan_min & BIT(i))
1734                                data->fan_min[i] = nct6775_read_value(data,
1735                                           data->REG_FAN_MIN[i]);
1736
1737                        if (data->REG_FAN_PULSES[i]) {
1738                                data->fan_pulses[i] =
1739                                  (nct6775_read_value(data,
1740                                                      data->REG_FAN_PULSES[i])
1741                                   >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1742                        }
1743
1744                        nct6775_select_fan_div(dev, data, i, reg);
1745                }
1746
1747                nct6775_update_pwm(dev);
1748                nct6775_update_pwm_limits(dev);
1749
1750                /* Measured temperatures and limits */
1751                for (i = 0; i < NUM_TEMP; i++) {
1752                        if (!(data->have_temp & BIT(i)))
1753                                continue;
1754                        for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1755                                if (data->reg_temp[j][i])
1756                                        data->temp[j][i]
1757                                          = nct6775_read_temp(data,
1758                                                data->reg_temp[j][i]);
1759                        }
1760                        if (i >= NUM_TEMP_FIXED ||
1761                            !(data->have_temp_fixed & BIT(i)))
1762                                continue;
1763                        data->temp_offset[i]
1764                          = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1765                }
1766
1767                data->alarms = 0;
1768                for (i = 0; i < NUM_REG_ALARM; i++) {
1769                        u8 alarm;
1770
1771                        if (!data->REG_ALARM[i])
1772                                continue;
1773                        alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1774                        data->alarms |= ((u64)alarm) << (i << 3);
1775                }
1776
1777                data->beeps = 0;
1778                for (i = 0; i < NUM_REG_BEEP; i++) {
1779                        u8 beep;
1780
1781                        if (!data->REG_BEEP[i])
1782                                continue;
1783                        beep = nct6775_read_value(data, data->REG_BEEP[i]);
1784                        data->beeps |= ((u64)beep) << (i << 3);
1785                }
1786
1787                data->last_updated = jiffies;
1788                data->valid = true;
1789        }
1790
1791        mutex_unlock(&data->update_lock);
1792        return data;
1793}
1794
1795/*
1796 * Sysfs callback functions
1797 */
1798static ssize_t
1799show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1800{
1801        struct nct6775_data *data = nct6775_update_device(dev);
1802        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1803        int index = sattr->index;
1804        int nr = sattr->nr;
1805
1806        return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1807}
1808
1809static ssize_t
1810store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1811             size_t count)
1812{
1813        struct nct6775_data *data = dev_get_drvdata(dev);
1814        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1815        int index = sattr->index;
1816        int nr = sattr->nr;
1817        unsigned long val;
1818        int err;
1819
1820        err = kstrtoul(buf, 10, &val);
1821        if (err < 0)
1822                return err;
1823        mutex_lock(&data->update_lock);
1824        data->in[nr][index] = in_to_reg(val, nr);
1825        nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1826                            data->in[nr][index]);
1827        mutex_unlock(&data->update_lock);
1828        return count;
1829}
1830
1831static ssize_t
1832show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1833{
1834        struct nct6775_data *data = nct6775_update_device(dev);
1835        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1836        int nr = data->ALARM_BITS[sattr->index];
1837
1838        return sprintf(buf, "%u\n",
1839                       (unsigned int)((data->alarms >> nr) & 0x01));
1840}
1841
1842static int find_temp_source(struct nct6775_data *data, int index, int count)
1843{
1844        int source = data->temp_src[index];
1845        int nr;
1846
1847        for (nr = 0; nr < count; nr++) {
1848                int src;
1849
1850                src = nct6775_read_value(data,
1851                                         data->REG_TEMP_SOURCE[nr]) & 0x1f;
1852                if (src == source)
1853                        return nr;
1854        }
1855        return -ENODEV;
1856}
1857
1858static ssize_t
1859show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1860{
1861        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1862        struct nct6775_data *data = nct6775_update_device(dev);
1863        unsigned int alarm = 0;
1864        int nr;
1865
1866        /*
1867         * For temperatures, there is no fixed mapping from registers to alarm
1868         * bits. Alarm bits are determined by the temperature source mapping.
1869         */
1870        nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1871        if (nr >= 0) {
1872                int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1873
1874                alarm = (data->alarms >> bit) & 0x01;
1875        }
1876        return sprintf(buf, "%u\n", alarm);
1877}
1878
1879static ssize_t
1880show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1881{
1882        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1883        struct nct6775_data *data = nct6775_update_device(dev);
1884        int nr = data->BEEP_BITS[sattr->index];
1885
1886        return sprintf(buf, "%u\n",
1887                       (unsigned int)((data->beeps >> nr) & 0x01));
1888}
1889
1890static ssize_t
1891store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1892           size_t count)
1893{
1894        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1895        struct nct6775_data *data = dev_get_drvdata(dev);
1896        int nr = data->BEEP_BITS[sattr->index];
1897        int regindex = nr >> 3;
1898        unsigned long val;
1899        int err;
1900
1901        err = kstrtoul(buf, 10, &val);
1902        if (err < 0)
1903                return err;
1904        if (val > 1)
1905                return -EINVAL;
1906
1907        mutex_lock(&data->update_lock);
1908        if (val)
1909                data->beeps |= (1ULL << nr);
1910        else
1911                data->beeps &= ~(1ULL << nr);
1912        nct6775_write_value(data, data->REG_BEEP[regindex],
1913                            (data->beeps >> (regindex << 3)) & 0xff);
1914        mutex_unlock(&data->update_lock);
1915        return count;
1916}
1917
1918static ssize_t
1919show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1920{
1921        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1922        struct nct6775_data *data = nct6775_update_device(dev);
1923        unsigned int beep = 0;
1924        int nr;
1925
1926        /*
1927         * For temperatures, there is no fixed mapping from registers to beep
1928         * enable bits. Beep enable bits are determined by the temperature
1929         * source mapping.
1930         */
1931        nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1932        if (nr >= 0) {
1933                int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1934
1935                beep = (data->beeps >> bit) & 0x01;
1936        }
1937        return sprintf(buf, "%u\n", beep);
1938}
1939
1940static ssize_t
1941store_temp_beep(struct device *dev, struct device_attribute *attr,
1942                const char *buf, size_t count)
1943{
1944        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1945        struct nct6775_data *data = dev_get_drvdata(dev);
1946        int nr, bit, regindex;
1947        unsigned long val;
1948        int err;
1949
1950        err = kstrtoul(buf, 10, &val);
1951        if (err < 0)
1952                return err;
1953        if (val > 1)
1954                return -EINVAL;
1955
1956        nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1957        if (nr < 0)
1958                return nr;
1959
1960        bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1961        regindex = bit >> 3;
1962
1963        mutex_lock(&data->update_lock);
1964        if (val)
1965                data->beeps |= (1ULL << bit);
1966        else
1967                data->beeps &= ~(1ULL << bit);
1968        nct6775_write_value(data, data->REG_BEEP[regindex],
1969                            (data->beeps >> (regindex << 3)) & 0xff);
1970        mutex_unlock(&data->update_lock);
1971
1972        return count;
1973}
1974
1975static umode_t nct6775_in_is_visible(struct kobject *kobj,
1976                                     struct attribute *attr, int index)
1977{
1978        struct device *dev = container_of(kobj, struct device, kobj);
1979        struct nct6775_data *data = dev_get_drvdata(dev);
1980        int in = index / 5;     /* voltage index */
1981
1982        if (!(data->have_in & BIT(in)))
1983                return 0;
1984
1985        return attr->mode;
1986}
1987
1988SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1989SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1990SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1991                0);
1992SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1993                  store_in_reg, 0, 1);
1994SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1995                  store_in_reg, 0, 2);
1996
1997/*
1998 * nct6775_in_is_visible uses the index into the following array
1999 * to determine if attributes should be created or not.
2000 * Any change in order or content must be matched.
2001 */
2002static struct sensor_device_template *nct6775_attributes_in_template[] = {
2003        &sensor_dev_template_in_input,
2004        &sensor_dev_template_in_alarm,
2005        &sensor_dev_template_in_beep,
2006        &sensor_dev_template_in_min,
2007        &sensor_dev_template_in_max,
2008        NULL
2009};
2010
2011static const struct sensor_template_group nct6775_in_template_group = {
2012        .templates = nct6775_attributes_in_template,
2013        .is_visible = nct6775_in_is_visible,
2014};
2015
2016static ssize_t
2017show_fan(struct device *dev, struct device_attribute *attr, char *buf)
2018{
2019        struct nct6775_data *data = nct6775_update_device(dev);
2020        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2021        int nr = sattr->index;
2022
2023        return sprintf(buf, "%d\n", data->rpm[nr]);
2024}
2025
2026static ssize_t
2027show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
2028{
2029        struct nct6775_data *data = nct6775_update_device(dev);
2030        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2031        int nr = sattr->index;
2032
2033        return sprintf(buf, "%d\n",
2034                       data->fan_from_reg_min(data->fan_min[nr],
2035                                              data->fan_div[nr]));
2036}
2037
2038static ssize_t
2039show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2040{
2041        struct nct6775_data *data = nct6775_update_device(dev);
2042        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2043        int nr = sattr->index;
2044
2045        return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2046}
2047
2048static ssize_t
2049store_fan_min(struct device *dev, struct device_attribute *attr,
2050              const char *buf, size_t count)
2051{
2052        struct nct6775_data *data = dev_get_drvdata(dev);
2053        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2054        int nr = sattr->index;
2055        unsigned long val;
2056        unsigned int reg;
2057        u8 new_div;
2058        int err;
2059
2060        err = kstrtoul(buf, 10, &val);
2061        if (err < 0)
2062                return err;
2063
2064        mutex_lock(&data->update_lock);
2065        if (!data->has_fan_div) {
2066                /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2067                if (!val) {
2068                        val = 0xff1f;
2069                } else {
2070                        if (val > 1350000U)
2071                                val = 135000U;
2072                        val = 1350000U / val;
2073                        val = (val & 0x1f) | ((val << 3) & 0xff00);
2074                }
2075                data->fan_min[nr] = val;
2076                goto write_min; /* Leave fan divider alone */
2077        }
2078        if (!val) {
2079                /* No min limit, alarm disabled */
2080                data->fan_min[nr] = 255;
2081                new_div = data->fan_div[nr]; /* No change */
2082                dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2083                goto write_div;
2084        }
2085        reg = 1350000U / val;
2086        if (reg >= 128 * 255) {
2087                /*
2088                 * Speed below this value cannot possibly be represented,
2089                 * even with the highest divider (128)
2090                 */
2091                data->fan_min[nr] = 254;
2092                new_div = 7; /* 128 == BIT(7) */
2093                dev_warn(dev,
2094                         "fan%u low limit %lu below minimum %u, set to minimum\n",
2095                         nr + 1, val, data->fan_from_reg_min(254, 7));
2096        } else if (!reg) {
2097                /*
2098                 * Speed above this value cannot possibly be represented,
2099                 * even with the lowest divider (1)
2100                 */
2101                data->fan_min[nr] = 1;
2102                new_div = 0; /* 1 == BIT(0) */
2103                dev_warn(dev,
2104                         "fan%u low limit %lu above maximum %u, set to maximum\n",
2105                         nr + 1, val, data->fan_from_reg_min(1, 0));
2106        } else {
2107                /*
2108                 * Automatically pick the best divider, i.e. the one such
2109                 * that the min limit will correspond to a register value
2110                 * in the 96..192 range
2111                 */
2112                new_div = 0;
2113                while (reg > 192 && new_div < 7) {
2114                        reg >>= 1;
2115                        new_div++;
2116                }
2117                data->fan_min[nr] = reg;
2118        }
2119
2120write_div:
2121        /*
2122         * Write both the fan clock divider (if it changed) and the new
2123         * fan min (unconditionally)
2124         */
2125        if (new_div != data->fan_div[nr]) {
2126                dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2127                        nr + 1, div_from_reg(data->fan_div[nr]),
2128                        div_from_reg(new_div));
2129                data->fan_div[nr] = new_div;
2130                nct6775_write_fan_div_common(data, nr);
2131                /* Give the chip time to sample a new speed value */
2132                data->last_updated = jiffies;
2133        }
2134
2135write_min:
2136        nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2137        mutex_unlock(&data->update_lock);
2138
2139        return count;
2140}
2141
2142static ssize_t
2143show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2144{
2145        struct nct6775_data *data = nct6775_update_device(dev);
2146        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2147        int p = data->fan_pulses[sattr->index];
2148
2149        return sprintf(buf, "%d\n", p ? : 4);
2150}
2151
2152static ssize_t
2153store_fan_pulses(struct device *dev, struct device_attribute *attr,
2154                 const char *buf, size_t count)
2155{
2156        struct nct6775_data *data = dev_get_drvdata(dev);
2157        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2158        int nr = sattr->index;
2159        unsigned long val;
2160        int err;
2161        u8 reg;
2162
2163        err = kstrtoul(buf, 10, &val);
2164        if (err < 0)
2165                return err;
2166
2167        if (val > 4)
2168                return -EINVAL;
2169
2170        mutex_lock(&data->update_lock);
2171        data->fan_pulses[nr] = val & 3;
2172        reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2173        reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2174        reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2175        nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2176        mutex_unlock(&data->update_lock);
2177
2178        return count;
2179}
2180
2181static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2182                                      struct attribute *attr, int index)
2183{
2184        struct device *dev = container_of(kobj, struct device, kobj);
2185        struct nct6775_data *data = dev_get_drvdata(dev);
2186        int fan = index / 6;    /* fan index */
2187        int nr = index % 6;     /* attribute index */
2188
2189        if (!(data->has_fan & BIT(fan)))
2190                return 0;
2191
2192        if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2193                return 0;
2194        if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2195                return 0;
2196        if (nr == 3 && !data->REG_FAN_PULSES[fan])
2197                return 0;
2198        if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2199                return 0;
2200        if (nr == 5 && data->kind != nct6775)
2201                return 0;
2202
2203        return attr->mode;
2204}
2205
2206SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2207SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2208                FAN_ALARM_BASE);
2209SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2210                store_beep, FAN_ALARM_BASE);
2211SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2212                store_fan_pulses, 0);
2213SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2214                store_fan_min, 0);
2215SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2216
2217/*
2218 * nct6775_fan_is_visible uses the index into the following array
2219 * to determine if attributes should be created or not.
2220 * Any change in order or content must be matched.
2221 */
2222static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2223        &sensor_dev_template_fan_input,
2224        &sensor_dev_template_fan_alarm, /* 1 */
2225        &sensor_dev_template_fan_beep,  /* 2 */
2226        &sensor_dev_template_fan_pulses,
2227        &sensor_dev_template_fan_min,   /* 4 */
2228        &sensor_dev_template_fan_div,   /* 5 */
2229        NULL
2230};
2231
2232static const struct sensor_template_group nct6775_fan_template_group = {
2233        .templates = nct6775_attributes_fan_template,
2234        .is_visible = nct6775_fan_is_visible,
2235        .base = 1,
2236};
2237
2238static ssize_t
2239show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2240{
2241        struct nct6775_data *data = nct6775_update_device(dev);
2242        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2243        int nr = sattr->index;
2244
2245        return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2246}
2247
2248static ssize_t
2249show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2250{
2251        struct nct6775_data *data = nct6775_update_device(dev);
2252        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2253        int nr = sattr->nr;
2254        int index = sattr->index;
2255
2256        return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2257}
2258
2259static ssize_t
2260store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2261           size_t count)
2262{
2263        struct nct6775_data *data = dev_get_drvdata(dev);
2264        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2265        int nr = sattr->nr;
2266        int index = sattr->index;
2267        int err;
2268        long val;
2269
2270        err = kstrtol(buf, 10, &val);
2271        if (err < 0)
2272                return err;
2273
2274        mutex_lock(&data->update_lock);
2275        data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2276        nct6775_write_temp(data, data->reg_temp[index][nr],
2277                           data->temp[index][nr]);
2278        mutex_unlock(&data->update_lock);
2279        return count;
2280}
2281
2282static ssize_t
2283show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2284{
2285        struct nct6775_data *data = nct6775_update_device(dev);
2286        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2287
2288        return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2289}
2290
2291static ssize_t
2292store_temp_offset(struct device *dev, struct device_attribute *attr,
2293                  const char *buf, size_t count)
2294{
2295        struct nct6775_data *data = dev_get_drvdata(dev);
2296        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2297        int nr = sattr->index;
2298        long val;
2299        int err;
2300
2301        err = kstrtol(buf, 10, &val);
2302        if (err < 0)
2303                return err;
2304
2305        val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2306
2307        mutex_lock(&data->update_lock);
2308        data->temp_offset[nr] = val;
2309        nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2310        mutex_unlock(&data->update_lock);
2311
2312        return count;
2313}
2314
2315static ssize_t
2316show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2317{
2318        struct nct6775_data *data = nct6775_update_device(dev);
2319        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2320        int nr = sattr->index;
2321
2322        return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2323}
2324
2325static ssize_t
2326store_temp_type(struct device *dev, struct device_attribute *attr,
2327                const char *buf, size_t count)
2328{
2329        struct nct6775_data *data = nct6775_update_device(dev);
2330        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2331        int nr = sattr->index;
2332        unsigned long val;
2333        int err;
2334        u8 vbat, diode, vbit, dbit;
2335
2336        err = kstrtoul(buf, 10, &val);
2337        if (err < 0)
2338                return err;
2339
2340        if (val != 1 && val != 3 && val != 4)
2341                return -EINVAL;
2342
2343        mutex_lock(&data->update_lock);
2344
2345        data->temp_type[nr] = val;
2346        vbit = 0x02 << nr;
2347        dbit = data->DIODE_MASK << nr;
2348        vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2349        diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2350        switch (val) {
2351        case 1: /* CPU diode (diode, current mode) */
2352                vbat |= vbit;
2353                diode |= dbit;
2354                break;
2355        case 3: /* diode, voltage mode */
2356                vbat |= dbit;
2357                break;
2358        case 4: /* thermistor */
2359                break;
2360        }
2361        nct6775_write_value(data, data->REG_VBAT, vbat);
2362        nct6775_write_value(data, data->REG_DIODE, diode);
2363
2364        mutex_unlock(&data->update_lock);
2365        return count;
2366}
2367
2368static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2369                                       struct attribute *attr, int index)
2370{
2371        struct device *dev = container_of(kobj, struct device, kobj);
2372        struct nct6775_data *data = dev_get_drvdata(dev);
2373        int temp = index / 10;  /* temp index */
2374        int nr = index % 10;    /* attribute index */
2375
2376        if (!(data->have_temp & BIT(temp)))
2377                return 0;
2378
2379        if (nr == 1 && !data->temp_label)
2380                return 0;
2381
2382        if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2383                return 0;                               /* alarm */
2384
2385        if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2386                return 0;                               /* beep */
2387
2388        if (nr == 4 && !data->reg_temp[1][temp])        /* max */
2389                return 0;
2390
2391        if (nr == 5 && !data->reg_temp[2][temp])        /* max_hyst */
2392                return 0;
2393
2394        if (nr == 6 && !data->reg_temp[3][temp])        /* crit */
2395                return 0;
2396
2397        if (nr == 7 && !data->reg_temp[4][temp])        /* lcrit */
2398                return 0;
2399
2400        /* offset and type only apply to fixed sensors */
2401        if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2402                return 0;
2403
2404        return attr->mode;
2405}
2406
2407SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2408SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2409SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2410                  store_temp, 0, 1);
2411SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2412                  show_temp, store_temp, 0, 2);
2413SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2414                  store_temp, 0, 3);
2415SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2416                  store_temp, 0, 4);
2417SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2418                show_temp_offset, store_temp_offset, 0);
2419SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2420                store_temp_type, 0);
2421SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2422SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2423                store_temp_beep, 0);
2424
2425/*
2426 * nct6775_temp_is_visible uses the index into the following array
2427 * to determine if attributes should be created or not.
2428 * Any change in order or content must be matched.
2429 */
2430static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2431        &sensor_dev_template_temp_input,
2432        &sensor_dev_template_temp_label,
2433        &sensor_dev_template_temp_alarm,        /* 2 */
2434        &sensor_dev_template_temp_beep,         /* 3 */
2435        &sensor_dev_template_temp_max,          /* 4 */
2436        &sensor_dev_template_temp_max_hyst,     /* 5 */
2437        &sensor_dev_template_temp_crit,         /* 6 */
2438        &sensor_dev_template_temp_lcrit,        /* 7 */
2439        &sensor_dev_template_temp_offset,       /* 8 */
2440        &sensor_dev_template_temp_type,         /* 9 */
2441        NULL
2442};
2443
2444static const struct sensor_template_group nct6775_temp_template_group = {
2445        .templates = nct6775_attributes_temp_template,
2446        .is_visible = nct6775_temp_is_visible,
2447        .base = 1,
2448};
2449
2450static ssize_t
2451show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2452{
2453        struct nct6775_data *data = nct6775_update_device(dev);
2454        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2455
2456        return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2457}
2458
2459static ssize_t
2460store_pwm_mode(struct device *dev, struct device_attribute *attr,
2461               const char *buf, size_t count)
2462{
2463        struct nct6775_data *data = dev_get_drvdata(dev);
2464        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2465        int nr = sattr->index;
2466        unsigned long val;
2467        int err;
2468        u8 reg;
2469
2470        err = kstrtoul(buf, 10, &val);
2471        if (err < 0)
2472                return err;
2473
2474        if (val > 1)
2475                return -EINVAL;
2476
2477        /* Setting DC mode (0) is not supported for all chips/channels */
2478        if (data->REG_PWM_MODE[nr] == 0) {
2479                if (!val)
2480                        return -EINVAL;
2481                return count;
2482        }
2483
2484        mutex_lock(&data->update_lock);
2485        data->pwm_mode[nr] = val;
2486        reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2487        reg &= ~data->PWM_MODE_MASK[nr];
2488        if (!val)
2489                reg |= data->PWM_MODE_MASK[nr];
2490        nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2491        mutex_unlock(&data->update_lock);
2492        return count;
2493}
2494
2495static ssize_t
2496show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2497{
2498        struct nct6775_data *data = nct6775_update_device(dev);
2499        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2500        int nr = sattr->nr;
2501        int index = sattr->index;
2502        int pwm;
2503
2504        /*
2505         * For automatic fan control modes, show current pwm readings.
2506         * Otherwise, show the configured value.
2507         */
2508        if (index == 0 && data->pwm_enable[nr] > manual)
2509                pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2510        else
2511                pwm = data->pwm[index][nr];
2512
2513        return sprintf(buf, "%d\n", pwm);
2514}
2515
2516static ssize_t
2517store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2518          size_t count)
2519{
2520        struct nct6775_data *data = dev_get_drvdata(dev);
2521        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2522        int nr = sattr->nr;
2523        int index = sattr->index;
2524        unsigned long val;
2525        int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2526        int maxval[7]
2527          = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2528        int err;
2529        u8 reg;
2530
2531        err = kstrtoul(buf, 10, &val);
2532        if (err < 0)
2533                return err;
2534        val = clamp_val(val, minval[index], maxval[index]);
2535
2536        mutex_lock(&data->update_lock);
2537        data->pwm[index][nr] = val;
2538        nct6775_write_value(data, data->REG_PWM[index][nr], val);
2539        if (index == 2) { /* floor: disable if val == 0 */
2540                reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2541                reg &= 0x7f;
2542                if (val)
2543                        reg |= 0x80;
2544                nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2545        }
2546        mutex_unlock(&data->update_lock);
2547        return count;
2548}
2549
2550/* Returns 0 if OK, -EINVAL otherwise */
2551static int check_trip_points(struct nct6775_data *data, int nr)
2552{
2553        int i;
2554
2555        for (i = 0; i < data->auto_pwm_num - 1; i++) {
2556                if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2557                        return -EINVAL;
2558        }
2559        for (i = 0; i < data->auto_pwm_num - 1; i++) {
2560                if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2561                        return -EINVAL;
2562        }
2563        /* validate critical temperature and pwm if enabled (pwm > 0) */
2564        if (data->auto_pwm[nr][data->auto_pwm_num]) {
2565                if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2566                                data->auto_temp[nr][data->auto_pwm_num] ||
2567                    data->auto_pwm[nr][data->auto_pwm_num - 1] >
2568                                data->auto_pwm[nr][data->auto_pwm_num])
2569                        return -EINVAL;
2570        }
2571        return 0;
2572}
2573
2574static void pwm_update_registers(struct nct6775_data *data, int nr)
2575{
2576        u8 reg;
2577
2578        switch (data->pwm_enable[nr]) {
2579        case off:
2580        case manual:
2581                break;
2582        case speed_cruise:
2583                reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2584                reg = (reg & ~data->tolerance_mask) |
2585                  (data->target_speed_tolerance[nr] & data->tolerance_mask);
2586                nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2587                nct6775_write_value(data, data->REG_TARGET[nr],
2588                                    data->target_speed[nr] & 0xff);
2589                if (data->REG_TOLERANCE_H) {
2590                        reg = (data->target_speed[nr] >> 8) & 0x0f;
2591                        reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2592                        nct6775_write_value(data,
2593                                            data->REG_TOLERANCE_H[nr],
2594                                            reg);
2595                }
2596                break;
2597        case thermal_cruise:
2598                nct6775_write_value(data, data->REG_TARGET[nr],
2599                                    data->target_temp[nr]);
2600                /* fall through  */
2601        default:
2602                reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2603                reg = (reg & ~data->tolerance_mask) |
2604                  data->temp_tolerance[0][nr];
2605                nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2606                break;
2607        }
2608}
2609
2610static ssize_t
2611show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2612{
2613        struct nct6775_data *data = nct6775_update_device(dev);
2614        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2615
2616        return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2617}
2618
2619static ssize_t
2620store_pwm_enable(struct device *dev, struct device_attribute *attr,
2621                 const char *buf, size_t count)
2622{
2623        struct nct6775_data *data = dev_get_drvdata(dev);
2624        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2625        int nr = sattr->index;
2626        unsigned long val;
2627        int err;
2628        u16 reg;
2629
2630        err = kstrtoul(buf, 10, &val);
2631        if (err < 0)
2632                return err;
2633
2634        if (val > sf4)
2635                return -EINVAL;
2636
2637        if (val == sf3 && data->kind != nct6775)
2638                return -EINVAL;
2639
2640        if (val == sf4 && check_trip_points(data, nr)) {
2641                dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2642                dev_err(dev, "Adjust trip points and try again\n");
2643                return -EINVAL;
2644        }
2645
2646        mutex_lock(&data->update_lock);
2647        data->pwm_enable[nr] = val;
2648        if (val == off) {
2649                /*
2650                 * turn off pwm control: select manual mode, set pwm to maximum
2651                 */
2652                data->pwm[0][nr] = 255;
2653                nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2654        }
2655        pwm_update_registers(data, nr);
2656        reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2657        reg &= 0x0f;
2658        reg |= pwm_enable_to_reg(val) << 4;
2659        nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2660        mutex_unlock(&data->update_lock);
2661        return count;
2662}
2663
2664static ssize_t
2665show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2666{
2667        int i, sel = 0;
2668
2669        for (i = 0; i < NUM_TEMP; i++) {
2670                if (!(data->have_temp & BIT(i)))
2671                        continue;
2672                if (src == data->temp_src[i]) {
2673                        sel = i + 1;
2674                        break;
2675                }
2676        }
2677
2678        return sprintf(buf, "%d\n", sel);
2679}
2680
2681static ssize_t
2682show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2683{
2684        struct nct6775_data *data = nct6775_update_device(dev);
2685        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2686        int index = sattr->index;
2687
2688        return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2689}
2690
2691static ssize_t
2692store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2693                   const char *buf, size_t count)
2694{
2695        struct nct6775_data *data = nct6775_update_device(dev);
2696        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2697        int nr = sattr->index;
2698        unsigned long val;
2699        int err, reg, src;
2700
2701        err = kstrtoul(buf, 10, &val);
2702        if (err < 0)
2703                return err;
2704        if (val == 0 || val > NUM_TEMP)
2705                return -EINVAL;
2706        if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2707                return -EINVAL;
2708
2709        mutex_lock(&data->update_lock);
2710        src = data->temp_src[val - 1];
2711        data->pwm_temp_sel[nr] = src;
2712        reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2713        reg &= 0xe0;
2714        reg |= src;
2715        nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2716        mutex_unlock(&data->update_lock);
2717
2718        return count;
2719}
2720
2721static ssize_t
2722show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2723                         char *buf)
2724{
2725        struct nct6775_data *data = nct6775_update_device(dev);
2726        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2727        int index = sattr->index;
2728
2729        return show_pwm_temp_sel_common(data, buf,
2730                                        data->pwm_weight_temp_sel[index]);
2731}
2732
2733static ssize_t
2734store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2735                          const char *buf, size_t count)
2736{
2737        struct nct6775_data *data = nct6775_update_device(dev);
2738        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2739        int nr = sattr->index;
2740        unsigned long val;
2741        int err, reg, src;
2742
2743        err = kstrtoul(buf, 10, &val);
2744        if (err < 0)
2745                return err;
2746        if (val > NUM_TEMP)
2747                return -EINVAL;
2748        val = array_index_nospec(val, NUM_TEMP + 1);
2749        if (val && (!(data->have_temp & BIT(val - 1)) ||
2750                    !data->temp_src[val - 1]))
2751                return -EINVAL;
2752
2753        mutex_lock(&data->update_lock);
2754        if (val) {
2755                src = data->temp_src[val - 1];
2756                data->pwm_weight_temp_sel[nr] = src;
2757                reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2758                reg &= 0xe0;
2759                reg |= (src | 0x80);
2760                nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2761        } else {
2762                data->pwm_weight_temp_sel[nr] = 0;
2763                reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2764                reg &= 0x7f;
2765                nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2766        }
2767        mutex_unlock(&data->update_lock);
2768
2769        return count;
2770}
2771
2772static ssize_t
2773show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2774{
2775        struct nct6775_data *data = nct6775_update_device(dev);
2776        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2777
2778        return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2779}
2780
2781static ssize_t
2782store_target_temp(struct device *dev, struct device_attribute *attr,
2783                  const char *buf, size_t count)
2784{
2785        struct nct6775_data *data = dev_get_drvdata(dev);
2786        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2787        int nr = sattr->index;
2788        unsigned long val;
2789        int err;
2790
2791        err = kstrtoul(buf, 10, &val);
2792        if (err < 0)
2793                return err;
2794
2795        val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2796                        data->target_temp_mask);
2797
2798        mutex_lock(&data->update_lock);
2799        data->target_temp[nr] = val;
2800        pwm_update_registers(data, nr);
2801        mutex_unlock(&data->update_lock);
2802        return count;
2803}
2804
2805static ssize_t
2806show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2807{
2808        struct nct6775_data *data = nct6775_update_device(dev);
2809        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2810        int nr = sattr->index;
2811
2812        return sprintf(buf, "%d\n",
2813                       fan_from_reg16(data->target_speed[nr],
2814                                      data->fan_div[nr]));
2815}
2816
2817static ssize_t
2818store_target_speed(struct device *dev, struct device_attribute *attr,
2819                   const char *buf, size_t count)
2820{
2821        struct nct6775_data *data = dev_get_drvdata(dev);
2822        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2823        int nr = sattr->index;
2824        unsigned long val;
2825        int err;
2826        u16 speed;
2827
2828        err = kstrtoul(buf, 10, &val);
2829        if (err < 0)
2830                return err;
2831
2832        val = clamp_val(val, 0, 1350000U);
2833        speed = fan_to_reg(val, data->fan_div[nr]);
2834
2835        mutex_lock(&data->update_lock);
2836        data->target_speed[nr] = speed;
2837        pwm_update_registers(data, nr);
2838        mutex_unlock(&data->update_lock);
2839        return count;
2840}
2841
2842static ssize_t
2843show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2844                    char *buf)
2845{
2846        struct nct6775_data *data = nct6775_update_device(dev);
2847        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2848        int nr = sattr->nr;
2849        int index = sattr->index;
2850
2851        return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2852}
2853
2854static ssize_t
2855store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2856                     const char *buf, size_t count)
2857{
2858        struct nct6775_data *data = dev_get_drvdata(dev);
2859        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2860        int nr = sattr->nr;
2861        int index = sattr->index;
2862        unsigned long val;
2863        int err;
2864
2865        err = kstrtoul(buf, 10, &val);
2866        if (err < 0)
2867                return err;
2868
2869        /* Limit tolerance as needed */
2870        val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2871
2872        mutex_lock(&data->update_lock);
2873        data->temp_tolerance[index][nr] = val;
2874        if (index)
2875                pwm_update_registers(data, nr);
2876        else
2877                nct6775_write_value(data,
2878                                    data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2879                                    val);
2880        mutex_unlock(&data->update_lock);
2881        return count;
2882}
2883
2884/*
2885 * Fan speed tolerance is a tricky beast, since the associated register is
2886 * a tick counter, but the value is reported and configured as rpm.
2887 * Compute resulting low and high rpm values and report the difference.
2888 * A fan speed tolerance only makes sense if a fan target speed has been
2889 * configured, so only display values other than 0 if that is the case.
2890 */
2891static ssize_t
2892show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2893                     char *buf)
2894{
2895        struct nct6775_data *data = nct6775_update_device(dev);
2896        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2897        int nr = sattr->index;
2898        int target = data->target_speed[nr];
2899        int tolerance = 0;
2900
2901        if (target) {
2902                int low = target - data->target_speed_tolerance[nr];
2903                int high = target + data->target_speed_tolerance[nr];
2904
2905                if (low <= 0)
2906                        low = 1;
2907                if (high > 0xffff)
2908                        high = 0xffff;
2909                if (high < low)
2910                        high = low;
2911
2912                tolerance = (fan_from_reg16(low, data->fan_div[nr])
2913                             - fan_from_reg16(high, data->fan_div[nr])) / 2;
2914        }
2915
2916        return sprintf(buf, "%d\n", tolerance);
2917}
2918
2919static ssize_t
2920store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2921                      const char *buf, size_t count)
2922{
2923        struct nct6775_data *data = dev_get_drvdata(dev);
2924        struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2925        int nr = sattr->index;
2926        unsigned long val;
2927        int err;
2928        int low, high;
2929
2930        err = kstrtoul(buf, 10, &val);
2931        if (err < 0)
2932                return err;
2933
2934        high = fan_from_reg16(data->target_speed[nr],
2935                              data->fan_div[nr]) + val;
2936        low = fan_from_reg16(data->target_speed[nr],
2937                             data->fan_div[nr]) - val;
2938        if (low <= 0)
2939                low = 1;
2940        if (high < low)
2941                high = low;
2942
2943        val = (fan_to_reg(low, data->fan_div[nr]) -
2944               fan_to_reg(high, data->fan_div[nr])) / 2;
2945
2946        /* Limit tolerance as needed */
2947        val = clamp_val(val, 0, data->speed_tolerance_limit);
2948
2949        mutex_lock(&data->update_lock);
2950        data->target_speed_tolerance[nr] = val;
2951        pwm_update_registers(data, nr);
2952        mutex_unlock(&data->update_lock);
2953        return count;
2954}
2955
2956SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2957SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2958                store_pwm_mode, 0);
2959SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2960                store_pwm_enable, 0);
2961SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2962                show_pwm_temp_sel, store_pwm_temp_sel, 0);
2963SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2964                show_target_temp, store_target_temp, 0);
2965SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2966                show_target_speed, store_target_speed, 0);
2967SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2968                show_speed_tolerance, store_speed_tolerance, 0);
2969
2970/* Smart Fan registers */
2971
2972static ssize_t
2973show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2974{
2975        struct nct6775_data *data = nct6775_update_device(dev);
2976        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2977        int nr = sattr->nr;
2978        int index = sattr->index;
2979
2980        return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2981}
2982
2983static ssize_t
2984store_weight_temp(struct device *dev, struct device_attribute *attr,
2985                  const char *buf, size_t count)
2986{
2987        struct nct6775_data *data = dev_get_drvdata(dev);
2988        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2989        int nr = sattr->nr;
2990        int index = sattr->index;
2991        unsigned long val;
2992        int err;
2993
2994        err = kstrtoul(buf, 10, &val);
2995        if (err < 0)
2996                return err;
2997
2998        val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2999
3000        mutex_lock(&data->update_lock);
3001        data->weight_temp[index][nr] = val;
3002        nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
3003        mutex_unlock(&data->update_lock);
3004        return count;
3005}
3006
3007SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
3008                  show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
3009SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
3010                  S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
3011SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
3012                  S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
3013SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
3014                  S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
3015SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
3016                  S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
3017SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
3018                  S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
3019
3020static ssize_t
3021show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
3022{
3023        struct nct6775_data *data = nct6775_update_device(dev);
3024        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3025        int nr = sattr->nr;
3026        int index = sattr->index;
3027
3028        return sprintf(buf, "%d\n",
3029                       step_time_from_reg(data->fan_time[index][nr],
3030                                          data->pwm_mode[nr]));
3031}
3032
3033static ssize_t
3034store_fan_time(struct device *dev, struct device_attribute *attr,
3035               const char *buf, size_t count)
3036{
3037        struct nct6775_data *data = dev_get_drvdata(dev);
3038        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3039        int nr = sattr->nr;
3040        int index = sattr->index;
3041        unsigned long val;
3042        int err;
3043
3044        err = kstrtoul(buf, 10, &val);
3045        if (err < 0)
3046                return err;
3047
3048        val = step_time_to_reg(val, data->pwm_mode[nr]);
3049        mutex_lock(&data->update_lock);
3050        data->fan_time[index][nr] = val;
3051        nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
3052        mutex_unlock(&data->update_lock);
3053        return count;
3054}
3055
3056static ssize_t
3057show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
3058{
3059        struct nct6775_data *data = nct6775_update_device(dev);
3060        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3061
3062        return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3063}
3064
3065static ssize_t
3066store_auto_pwm(struct device *dev, struct device_attribute *attr,
3067               const char *buf, size_t count)
3068{
3069        struct nct6775_data *data = dev_get_drvdata(dev);
3070        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3071        int nr = sattr->nr;
3072        int point = sattr->index;
3073        unsigned long val;
3074        int err;
3075        u8 reg;
3076
3077        err = kstrtoul(buf, 10, &val);
3078        if (err < 0)
3079                return err;
3080        if (val > 255)
3081                return -EINVAL;
3082
3083        if (point == data->auto_pwm_num) {
3084                if (data->kind != nct6775 && !val)
3085                        return -EINVAL;
3086                if (data->kind != nct6779 && val)
3087                        val = 0xff;
3088        }
3089
3090        mutex_lock(&data->update_lock);
3091        data->auto_pwm[nr][point] = val;
3092        if (point < data->auto_pwm_num) {
3093                nct6775_write_value(data,
3094                                    NCT6775_AUTO_PWM(data, nr, point),
3095                                    data->auto_pwm[nr][point]);
3096        } else {
3097                switch (data->kind) {
3098                case nct6775:
3099                        /* disable if needed (pwm == 0) */
3100                        reg = nct6775_read_value(data,
3101                                                 NCT6775_REG_CRITICAL_ENAB[nr]);
3102                        if (val)
3103                                reg |= 0x02;
3104                        else
3105                                reg &= ~0x02;
3106                        nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3107                                            reg);
3108                        break;
3109                case nct6776:
3110                        break; /* always enabled, nothing to do */
3111                case nct6106:
3112                case nct6779:
3113                case nct6791:
3114                case nct6792:
3115                case nct6793:
3116                case nct6795:
3117                case nct6796:
3118                case nct6797:
3119                case nct6798:
3120                        nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3121                                            val);
3122                        reg = nct6775_read_value(data,
3123                                        data->REG_CRITICAL_PWM_ENABLE[nr]);
3124                        if (val == 255)
3125                                reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3126                        else
3127                                reg |= data->CRITICAL_PWM_ENABLE_MASK;
3128                        nct6775_write_value(data,
3129                                            data->REG_CRITICAL_PWM_ENABLE[nr],
3130                                            reg);
3131                        break;
3132                }
3133        }
3134        mutex_unlock(&data->update_lock);
3135        return count;
3136}
3137
3138static ssize_t
3139show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3140{
3141        struct nct6775_data *data = nct6775_update_device(dev);
3142        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3143        int nr = sattr->nr;
3144        int point = sattr->index;
3145
3146        /*
3147         * We don't know for sure if the temperature is signed or unsigned.
3148         * Assume it is unsigned.
3149         */
3150        return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3151}
3152
3153static ssize_t
3154store_auto_temp(struct device *dev, struct device_attribute *attr,
3155                const char *buf, size_t count)
3156{
3157        struct nct6775_data *data = dev_get_drvdata(dev);
3158        struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3159        int nr = sattr->nr;
3160        int point = sattr->index;
3161        unsigned long val;
3162        int err;
3163
3164        err = kstrtoul(buf, 10, &val);
3165        if (err)
3166                return err;
3167        if (val > 255000)
3168                return -EINVAL;
3169
3170        mutex_lock(&data->update_lock);
3171        data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3172        if (point < data->auto_pwm_num) {
3173                nct6775_write_value(data,
3174                                    NCT6775_AUTO_TEMP(data, nr, point),
3175                                    data->auto_temp[nr][point]);
3176        } else {
3177                nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3178                                    data->auto_temp[nr][point]);
3179        }
3180        mutex_unlock(&data->update_lock);
3181        return count;
3182}
3183
3184static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3185                                      struct attribute *attr, int index)
3186{
3187        struct device *dev = container_of(kobj, struct device, kobj);
3188        struct nct6775_data *data = dev_get_drvdata(dev);
3189        int pwm = index / 36;   /* pwm index */
3190        int nr = index % 36;    /* attribute index */
3191
3192        if (!(data->has_pwm & BIT(pwm)))
3193                return 0;
3194
3195        if ((nr >= 14 && nr <= 18) || nr == 21)   /* weight */
3196                if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3197                        return 0;
3198        if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3199                return 0;
3200        if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3201                return 0;
3202        if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3203                return 0;
3204
3205        if (nr >= 22 && nr <= 35) {             /* auto point */
3206                int api = (nr - 22) / 2;        /* auto point index */
3207
3208                if (api > data->auto_pwm_num)
3209                        return 0;
3210        }
3211        return attr->mode;
3212}
3213
3214SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3215                  show_fan_time, store_fan_time, 0, 0);
3216SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3217                  show_fan_time, store_fan_time, 0, 1);
3218SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3219                  show_fan_time, store_fan_time, 0, 2);
3220SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3221                  store_pwm, 0, 1);
3222SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3223                  store_pwm, 0, 2);
3224SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3225                  show_temp_tolerance, store_temp_tolerance, 0, 0);
3226SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3227                  S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3228                  0, 1);
3229
3230SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3231                  0, 3);
3232
3233SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3234                  store_pwm, 0, 4);
3235
3236SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3237                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3238SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3239                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3240
3241SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3242                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3243SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3244                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3245
3246SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3247                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3248SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3249                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3250
3251SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3252                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3253SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3254                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3255
3256SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3257                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3258SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3259                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3260
3261SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3262                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3263SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3264                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3265
3266SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3267                  S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3268SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3269                  S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3270
3271/*
3272 * nct6775_pwm_is_visible uses the index into the following array
3273 * to determine if attributes should be created or not.
3274 * Any change in order or content must be matched.
3275 */
3276static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3277        &sensor_dev_template_pwm,
3278        &sensor_dev_template_pwm_mode,
3279        &sensor_dev_template_pwm_enable,
3280        &sensor_dev_template_pwm_temp_sel,
3281        &sensor_dev_template_pwm_temp_tolerance,
3282        &sensor_dev_template_pwm_crit_temp_tolerance,
3283        &sensor_dev_template_pwm_target_temp,
3284        &sensor_dev_template_fan_target,
3285        &sensor_dev_template_fan_tolerance,
3286        &sensor_dev_template_pwm_stop_time,
3287        &sensor_dev_template_pwm_step_up_time,
3288        &sensor_dev_template_pwm_step_down_time,
3289        &sensor_dev_template_pwm_start,
3290        &sensor_dev_template_pwm_floor,
3291        &sensor_dev_template_pwm_weight_temp_sel,       /* 14 */
3292        &sensor_dev_template_pwm_weight_temp_step,
3293        &sensor_dev_template_pwm_weight_temp_step_tol,
3294        &sensor_dev_template_pwm_weight_temp_step_base,
3295        &sensor_dev_template_pwm_weight_duty_step,      /* 18 */
3296        &sensor_dev_template_pwm_max,                   /* 19 */
3297        &sensor_dev_template_pwm_step,                  /* 20 */
3298        &sensor_dev_template_pwm_weight_duty_base,      /* 21 */
3299        &sensor_dev_template_pwm_auto_point1_pwm,       /* 22 */
3300        &sensor_dev_template_pwm_auto_point1_temp,
3301        &sensor_dev_template_pwm_auto_point2_pwm,
3302        &sensor_dev_template_pwm_auto_point2_temp,
3303        &sensor_dev_template_pwm_auto_point3_pwm,
3304        &sensor_dev_template_pwm_auto_point3_temp,
3305        &sensor_dev_template_pwm_auto_point4_pwm,
3306        &sensor_dev_template_pwm_auto_point4_temp,
3307        &sensor_dev_template_pwm_auto_point5_pwm,
3308        &sensor_dev_template_pwm_auto_point5_temp,
3309        &sensor_dev_template_pwm_auto_point6_pwm,
3310        &sensor_dev_template_pwm_auto_point6_temp,
3311        &sensor_dev_template_pwm_auto_point7_pwm,
3312        &sensor_dev_template_pwm_auto_point7_temp,      /* 35 */
3313
3314        NULL
3315};
3316
3317static const struct sensor_template_group nct6775_pwm_template_group = {
3318        .templates = nct6775_attributes_pwm_template,
3319        .is_visible = nct6775_pwm_is_visible,
3320        .base = 1,
3321};
3322
3323static ssize_t
3324cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3325{
3326        struct nct6775_data *data = dev_get_drvdata(dev);
3327
3328        return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3329}
3330
3331static DEVICE_ATTR_RO(cpu0_vid);
3332
3333/* Case open detection */
3334
3335static ssize_t
3336clear_caseopen(struct device *dev, struct device_attribute *attr,
3337               const char *buf, size_t count)
3338{
3339        struct nct6775_data *data = dev_get_drvdata(dev);
3340        int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3341        unsigned long val;
3342        u8 reg;
3343        int ret;
3344
3345        if (kstrtoul(buf, 10, &val) || val != 0)
3346                return -EINVAL;
3347
3348        mutex_lock(&data->update_lock);
3349
3350        /*
3351         * Use CR registers to clear caseopen status.
3352         * The CR registers are the same for all chips, and not all chips
3353         * support clearing the caseopen status through "regular" registers.
3354         */
3355        ret = superio_enter(data->sioreg);
3356        if (ret) {
3357                count = ret;
3358                goto error;
3359        }
3360
3361        superio_select(data->sioreg, NCT6775_LD_ACPI);
3362        reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3363        reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3364        superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3365        reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3366        superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3367        superio_exit(data->sioreg);
3368
3369        data->valid = false;    /* Force cache refresh */
3370error:
3371        mutex_unlock(&data->update_lock);
3372        return count;
3373}
3374
3375static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3376                          clear_caseopen, INTRUSION_ALARM_BASE);
3377static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3378                          clear_caseopen, INTRUSION_ALARM_BASE + 1);
3379static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3380                          store_beep, INTRUSION_ALARM_BASE);
3381static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3382                          store_beep, INTRUSION_ALARM_BASE + 1);
3383static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3384                          store_beep, BEEP_ENABLE_BASE);
3385
3386static umode_t nct6775_other_is_visible(struct kobject *kobj,
3387                                        struct attribute *attr, int index)
3388{
3389        struct device *dev = container_of(kobj, struct device, kobj);
3390        struct nct6775_data *data = dev_get_drvdata(dev);
3391
3392        if (index == 0 && !data->have_vid)
3393                return 0;
3394
3395        if (index == 1 || index == 2) {
3396                if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3397                        return 0;
3398        }
3399
3400        if (index == 3 || index == 4) {
3401                if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3402                        return 0;
3403        }
3404
3405        return attr->mode;
3406}
3407
3408/*
3409 * nct6775_other_is_visible uses the index into the following array
3410 * to determine if attributes should be created or not.
3411 * Any change in order or content must be matched.
3412 */
3413static struct attribute *nct6775_attributes_other[] = {
3414        &dev_attr_cpu0_vid.attr,                                /* 0 */
3415        &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,        /* 1 */
3416        &sensor_dev_attr_intrusion1_alarm.dev_attr.attr,        /* 2 */
3417        &sensor_dev_attr_intrusion0_beep.dev_attr.attr,         /* 3 */
3418        &sensor_dev_attr_intrusion1_beep.dev_attr.attr,         /* 4 */
3419        &sensor_dev_attr_beep_enable.dev_attr.attr,             /* 5 */
3420
3421        NULL
3422};
3423
3424static const struct attribute_group nct6775_group_other = {
3425        .attrs = nct6775_attributes_other,
3426        .is_visible = nct6775_other_is_visible,
3427};
3428
3429static inline void nct6775_init_device(struct nct6775_data *data)
3430{
3431        int i;
3432        u8 tmp, diode;
3433
3434        /* Start monitoring if needed */
3435        if (data->REG_CONFIG) {
3436                tmp = nct6775_read_value(data, data->REG_CONFIG);
3437                if (!(tmp & 0x01))
3438                        nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3439        }
3440
3441        /* Enable temperature sensors if needed */
3442        for (i = 0; i < NUM_TEMP; i++) {
3443                if (!(data->have_temp & BIT(i)))
3444                        continue;
3445                if (!data->reg_temp_config[i])
3446                        continue;
3447                tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3448                if (tmp & 0x01)
3449                        nct6775_write_value(data, data->reg_temp_config[i],
3450                                            tmp & 0xfe);
3451        }
3452
3453        /* Enable VBAT monitoring if needed */
3454        tmp = nct6775_read_value(data, data->REG_VBAT);
3455        if (!(tmp & 0x01))
3456                nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3457
3458        diode = nct6775_read_value(data, data->REG_DIODE);
3459
3460        for (i = 0; i < data->temp_fixed_num; i++) {
3461                if (!(data->have_temp_fixed & BIT(i)))
3462                        continue;
3463                if ((tmp & (data->DIODE_MASK << i)))    /* diode */
3464                        data->temp_type[i]
3465                          = 3 - ((diode >> i) & data->DIODE_MASK);
3466                else                            /* thermistor */
3467                        data->temp_type[i] = 4;
3468        }
3469}
3470
3471static void
3472nct6775_check_fan_inputs(struct nct6775_data *data)
3473{
3474        bool fan3pin = false, fan4pin = false, fan4min = false;
3475        bool fan5pin = false, fan6pin = false, fan7pin = false;
3476        bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3477        bool pwm6pin = false, pwm7pin = false;
3478        int sioreg = data->sioreg;
3479
3480        /* Store SIO_REG_ENABLE for use during resume */
3481        superio_select(sioreg, NCT6775_LD_HWM);
3482        data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3483
3484        /* fan4 and fan5 share some pins with the GPIO and serial flash */
3485        if (data->kind == nct6775) {
3486                int cr2c = superio_inb(sioreg, 0x2c);
3487
3488                fan3pin = cr2c & BIT(6);
3489                pwm3pin = cr2c & BIT(7);
3490
3491                /* On NCT6775, fan4 shares pins with the fdc interface */
3492                fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3493        } else if (data->kind == nct6776) {
3494                bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3495                const char *board_vendor, *board_name;
3496
3497                board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3498                board_name = dmi_get_system_info(DMI_BOARD_NAME);
3499
3500                if (board_name && board_vendor &&
3501                    !strcmp(board_vendor, "ASRock")) {
3502                        /*
3503                         * Auxiliary fan monitoring is not enabled on ASRock
3504                         * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3505                         * Observed with BIOS version 2.00.
3506                         */
3507                        if (!strcmp(board_name, "Z77 Pro4-M")) {
3508                                if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3509                                        data->sio_reg_enable |= 0xe0;
3510                                        superio_outb(sioreg, SIO_REG_ENABLE,
3511                                                     data->sio_reg_enable);
3512                                }
3513                        }
3514                }
3515
3516                if (data->sio_reg_enable & 0x80)
3517                        fan3pin = gpok;
3518                else
3519                        fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3520
3521                if (data->sio_reg_enable & 0x40)
3522                        fan4pin = gpok;
3523                else
3524                        fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3525
3526                if (data->sio_reg_enable & 0x20)
3527                        fan5pin = gpok;
3528                else
3529                        fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3530
3531                fan4min = fan4pin;
3532                pwm3pin = fan3pin;
3533        } else if (data->kind == nct6106) {
3534                int cr24 = superio_inb(sioreg, 0x24);
3535
3536                fan3pin = !(cr24 & 0x80);
3537                pwm3pin = cr24 & 0x08;
3538        } else {
3539                /*
3540                 * NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D,
3541                 * NCT6797D, NCT6798D
3542                 */
3543                int cr1a = superio_inb(sioreg, 0x1a);
3544                int cr1b = superio_inb(sioreg, 0x1b);
3545                int cr1c = superio_inb(sioreg, 0x1c);
3546                int cr1d = superio_inb(sioreg, 0x1d);
3547                int cr2a = superio_inb(sioreg, 0x2a);
3548                int cr2b = superio_inb(sioreg, 0x2b);
3549                int cr2d = superio_inb(sioreg, 0x2d);
3550                int cr2f = superio_inb(sioreg, 0x2f);
3551                bool dsw_en = cr2f & BIT(3);
3552                bool ddr4_en = cr2f & BIT(4);
3553                int cre0;
3554                int creb;
3555                int cred;
3556
3557                superio_select(sioreg, NCT6775_LD_12);
3558                cre0 = superio_inb(sioreg, 0xe0);
3559                creb = superio_inb(sioreg, 0xeb);
3560                cred = superio_inb(sioreg, 0xed);
3561
3562                fan3pin = !(cr1c & BIT(5));
3563                fan4pin = !(cr1c & BIT(6));
3564                fan5pin = !(cr1c & BIT(7));
3565
3566                pwm3pin = !(cr1c & BIT(0));
3567                pwm4pin = !(cr1c & BIT(1));
3568                pwm5pin = !(cr1c & BIT(2));
3569
3570                switch (data->kind) {
3571                case nct6791:
3572                        fan6pin = cr2d & BIT(1);
3573                        pwm6pin = cr2d & BIT(0);
3574                        break;
3575                case nct6792:
3576                        fan6pin = !dsw_en && (cr2d & BIT(1));
3577                        pwm6pin = !dsw_en && (cr2d & BIT(0));
3578                        break;
3579                case nct6793:
3580                        fan5pin |= cr1b & BIT(5);
3581                        fan5pin |= creb & BIT(5);
3582
3583                        fan6pin = !dsw_en && (cr2d & BIT(1));
3584                        fan6pin |= creb & BIT(3);
3585
3586                        pwm5pin |= cr2d & BIT(7);
3587                        pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3588
3589                        pwm6pin = !dsw_en && (cr2d & BIT(0));
3590                        pwm6pin |= creb & BIT(2);
3591                        break;
3592                case nct6795:
3593                        fan5pin |= cr1b & BIT(5);
3594                        fan5pin |= creb & BIT(5);
3595
3596                        fan6pin = (cr2a & BIT(4)) &&
3597                                        (!dsw_en || (cred & BIT(4)));
3598                        fan6pin |= creb & BIT(3);
3599
3600                        pwm5pin |= cr2d & BIT(7);
3601                        pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3602
3603                        pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
3604                        pwm6pin |= creb & BIT(2);
3605                        break;
3606                case nct6796:
3607                        fan5pin |= cr1b & BIT(5);
3608                        fan5pin |= (cre0 & BIT(3)) && !(cr1b & BIT(0));
3609                        fan5pin |= creb & BIT(5);
3610
3611                        fan6pin = (cr2a & BIT(4)) &&
3612                                        (!dsw_en || (cred & BIT(4)));
3613                        fan6pin |= creb & BIT(3);
3614
3615                        fan7pin = !(cr2b & BIT(2));
3616
3617                        pwm5pin |= cr2d & BIT(7);
3618                        pwm5pin |= (cre0 & BIT(4)) && !(cr1b & BIT(0));
3619                        pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3620
3621                        pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
3622                        pwm6pin |= creb & BIT(2);
3623
3624                        pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3625                        break;
3626                case nct6797:
3627                        fan5pin |= !ddr4_en && (cr1b & BIT(5));
3628                        fan5pin |= creb & BIT(5);
3629
3630                        fan6pin = cr2a & BIT(4);
3631                        fan6pin |= creb & BIT(3);
3632
3633                        fan7pin = cr1a & BIT(1);
3634
3635                        pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3636                        pwm5pin |= !ddr4_en && (cr2d & BIT(7));
3637
3638                        pwm6pin = creb & BIT(2);
3639                        pwm6pin |= cred & BIT(2);
3640
3641                        pwm7pin = cr1d & BIT(4);
3642                        break;
3643                case nct6798:
3644                        fan6pin = !(cr1b & BIT(0)) && (cre0 & BIT(3));
3645                        fan6pin |= cr2a & BIT(4);
3646                        fan6pin |= creb & BIT(5);
3647
3648                        fan7pin = cr1b & BIT(5);
3649                        fan7pin |= !(cr2b & BIT(2));
3650                        fan7pin |= creb & BIT(3);
3651
3652                        pwm6pin = !(cr1b & BIT(0)) && (cre0 & BIT(4));
3653                        pwm6pin |= !(cred & BIT(2)) && (cr2a & BIT(3));
3654                        pwm6pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3655
3656                        pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3657                        pwm7pin |= cr2d & BIT(7);
3658                        pwm7pin |= creb & BIT(2);
3659                        break;
3660                default:        /* NCT6779D */
3661                        break;
3662                }
3663
3664                fan4min = fan4pin;
3665        }
3666
3667        /* fan 1 and 2 (0x03) are always present */
3668        data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3669                (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3670        data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3671                (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3672        data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3673                (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3674}
3675
3676static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3677                             int *available, int *mask)
3678{
3679        int i;
3680        u8 src;
3681
3682        for (i = 0; i < data->pwm_num && *available; i++) {
3683                int index;
3684
3685                if (!regp[i])
3686                        continue;
3687                src = nct6775_read_value(data, regp[i]);
3688                src &= 0x1f;
3689                if (!src || (*mask & BIT(src)))
3690                        continue;
3691                if (!(data->temp_mask & BIT(src)))
3692                        continue;
3693
3694                index = __ffs(*available);
3695                nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3696                *available &= ~BIT(index);
3697                *mask |= BIT(src);
3698        }
3699}
3700
3701static int nct6775_probe(struct platform_device *pdev)
3702{
3703        struct device *dev = &pdev->dev;
3704        struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3705        struct nct6775_data *data;
3706        struct resource *res;
3707        int i, s, err = 0;
3708        int src, mask, available;
3709        const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3710        const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3711        const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3712        int num_reg_temp, num_reg_temp_mon;
3713        u8 cr2a;
3714        struct attribute_group *group;
3715        struct device *hwmon_dev;
3716        int num_attr_groups = 0;
3717
3718        res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3719        if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3720                                 DRVNAME))
3721                return -EBUSY;
3722
3723        data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3724                            GFP_KERNEL);
3725        if (!data)
3726                return -ENOMEM;
3727
3728        data->kind = sio_data->kind;
3729        data->sioreg = sio_data->sioreg;
3730        data->addr = res->start;
3731        mutex_init(&data->update_lock);
3732        data->name = nct6775_device_names[data->kind];
3733        data->bank = 0xff;              /* Force initial bank selection */
3734        platform_set_drvdata(pdev, data);
3735
3736        switch (data->kind) {
3737        case nct6106:
3738                data->in_num = 9;
3739                data->pwm_num = 3;
3740                data->auto_pwm_num = 4;
3741                data->temp_fixed_num = 3;
3742                data->num_temp_alarms = 6;
3743                data->num_temp_beeps = 6;
3744
3745                data->fan_from_reg = fan_from_reg13;
3746                data->fan_from_reg_min = fan_from_reg13;
3747
3748                data->temp_label = nct6776_temp_label;
3749                data->temp_mask = NCT6776_TEMP_MASK;
3750                data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3751
3752                data->REG_VBAT = NCT6106_REG_VBAT;
3753                data->REG_DIODE = NCT6106_REG_DIODE;
3754                data->DIODE_MASK = NCT6106_DIODE_MASK;
3755                data->REG_VIN = NCT6106_REG_IN;
3756                data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3757                data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3758                data->REG_TARGET = NCT6106_REG_TARGET;
3759                data->REG_FAN = NCT6106_REG_FAN;
3760                data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3761                data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3762                data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3763                data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3764                data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3765                data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3766                data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3767                data->REG_TOLERANCE_H = NCT6106_REG_TOLERANCE_H;
3768                data->REG_PWM[0] = NCT6106_REG_PWM;
3769                data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3770                data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3771                data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3772                data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3773                data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3774                data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3775                data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3776                data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3777                data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3778                data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3779                data->REG_CRITICAL_TEMP_TOLERANCE
3780                  = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3781                data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3782                data->CRITICAL_PWM_ENABLE_MASK
3783                  = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3784                data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3785                data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3786                data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3787                data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3788                data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3789                data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3790                data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3791                data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3792                data->REG_ALARM = NCT6106_REG_ALARM;
3793                data->ALARM_BITS = NCT6106_ALARM_BITS;
3794                data->REG_BEEP = NCT6106_REG_BEEP;
3795                data->BEEP_BITS = NCT6106_BEEP_BITS;
3796
3797                reg_temp = NCT6106_REG_TEMP;
3798                reg_temp_mon = NCT6106_REG_TEMP_MON;
3799                num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3800                num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3801                reg_temp_over = NCT6106_REG_TEMP_OVER;
3802                reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3803                reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3804                reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3805                reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3806                reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3807                reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3808
3809                break;
3810        case nct6775:
3811                data->in_num = 9;
3812                data->pwm_num = 3;
3813                data->auto_pwm_num = 6;
3814                data->has_fan_div = true;
3815                data->temp_fixed_num = 3;
3816                data->num_temp_alarms = 3;
3817                data->num_temp_beeps = 3;
3818
3819                data->ALARM_BITS = NCT6775_ALARM_BITS;
3820                data->BEEP_BITS = NCT6775_BEEP_BITS;
3821
3822                data->fan_from_reg = fan_from_reg16;
3823                data->fan_from_reg_min = fan_from_reg8;
3824                data->target_temp_mask = 0x7f;
3825                data->tolerance_mask = 0x0f;
3826                data->speed_tolerance_limit = 15;
3827
3828                data->temp_label = nct6775_temp_label;
3829                data->temp_mask = NCT6775_TEMP_MASK;
3830                data->virt_temp_mask = NCT6775_VIRT_TEMP_MASK;
3831
3832                data->REG_CONFIG = NCT6775_REG_CONFIG;
3833                data->REG_VBAT = NCT6775_REG_VBAT;
3834                data->REG_DIODE = NCT6775_REG_DIODE;
3835                data->DIODE_MASK = NCT6775_DIODE_MASK;
3836                data->REG_VIN = NCT6775_REG_IN;
3837                data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3838                data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3839                data->REG_TARGET = NCT6775_REG_TARGET;
3840                data->REG_FAN = NCT6775_REG_FAN;
3841                data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3842                data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3843                data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3844                data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3845                data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3846                data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3847                data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3848                data->REG_PWM[0] = NCT6775_REG_PWM;
3849                data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3850                data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3851                data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3852                data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3853                data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3854                data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3855                data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3856                data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3857                data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3858                data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3859                data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3860                data->REG_CRITICAL_TEMP_TOLERANCE
3861                  = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3862                data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3863                data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3864                data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3865                data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3866                data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3867                data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3868                data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3869                data->REG_ALARM = NCT6775_REG_ALARM;
3870                data->REG_BEEP = NCT6775_REG_BEEP;
3871
3872                reg_temp = NCT6775_REG_TEMP;
3873                reg_temp_mon = NCT6775_REG_TEMP_MON;
3874                num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3875                num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3876                reg_temp_over = NCT6775_REG_TEMP_OVER;
3877                reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3878                reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3879                reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3880                reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3881
3882                break;
3883        case nct6776:
3884                data->in_num = 9;
3885                data->pwm_num = 3;
3886                data->auto_pwm_num = 4;
3887                data->has_fan_div = false;
3888                data->temp_fixed_num = 3;
3889                data->num_temp_alarms = 3;
3890                data->num_temp_beeps = 6;
3891
3892                data->ALARM_BITS = NCT6776_ALARM_BITS;
3893                data->BEEP_BITS = NCT6776_BEEP_BITS;
3894
3895                data->fan_from_reg = fan_from_reg13;
3896                data->fan_from_reg_min = fan_from_reg13;
3897                data->target_temp_mask = 0xff;
3898                data->tolerance_mask = 0x07;
3899                data->speed_tolerance_limit = 63;
3900
3901                data->temp_label = nct6776_temp_label;
3902                data->temp_mask = NCT6776_TEMP_MASK;
3903                data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3904
3905                data->REG_CONFIG = NCT6775_REG_CONFIG;
3906                data->REG_VBAT = NCT6775_REG_VBAT;
3907                data->REG_DIODE = NCT6775_REG_DIODE;
3908                data->DIODE_MASK = NCT6775_DIODE_MASK;
3909                data->REG_VIN = NCT6775_REG_IN;
3910                data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3911                data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3912                data->REG_TARGET = NCT6775_REG_TARGET;
3913                data->REG_FAN = NCT6775_REG_FAN;
3914                data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3915                data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3916                data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3917                data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3918                data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3919                data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3920                data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3921                data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3922                data->REG_PWM[0] = NCT6775_REG_PWM;
3923                data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3924                data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3925                data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3926                data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3927                data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3928                data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3929                data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3930                data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3931                data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3932                data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3933                data->REG_CRITICAL_TEMP_TOLERANCE
3934                  = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3935                data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3936                data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3937                data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3938                data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3939                data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3940                data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3941                data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3942                data->REG_ALARM = NCT6775_REG_ALARM;
3943                data->REG_BEEP = NCT6776_REG_BEEP;
3944
3945                reg_temp = NCT6775_REG_TEMP;
3946                reg_temp_mon = NCT6775_REG_TEMP_MON;
3947                num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3948                num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3949                reg_temp_over = NCT6775_REG_TEMP_OVER;
3950                reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3951                reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3952                reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3953                reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3954
3955                break;
3956        case nct6779:
3957                data->in_num = 15;
3958                data->pwm_num = 5;
3959                data->auto_pwm_num = 4;
3960                data->has_fan_div = false;
3961                data->temp_fixed_num = 6;
3962                data->num_temp_alarms = 2;
3963                data->num_temp_beeps = 2;
3964
3965                data->ALARM_BITS = NCT6779_ALARM_BITS;
3966                data->BEEP_BITS = NCT6779_BEEP_BITS;
3967
3968                data->fan_from_reg = fan_from_reg_rpm;
3969                data->fan_from_reg_min = fan_from_reg13;
3970                data->target_temp_mask = 0xff;
3971                data->tolerance_mask = 0x07;
3972                data->speed_tolerance_limit = 63;
3973
3974                data->temp_label = nct6779_temp_label;
3975                data->temp_mask = NCT6779_TEMP_MASK;
3976                data->virt_temp_mask = NCT6779_VIRT_TEMP_MASK;
3977
3978                data->REG_CONFIG = NCT6775_REG_CONFIG;
3979                data->REG_VBAT = NCT6775_REG_VBAT;
3980                data->REG_DIODE = NCT6775_REG_DIODE;
3981                data->DIODE_MASK = NCT6775_DIODE_MASK;
3982                data->REG_VIN = NCT6779_REG_IN;
3983                data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3984                data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3985                data->REG_TARGET = NCT6775_REG_TARGET;
3986                data->REG_FAN = NCT6779_REG_FAN;
3987                data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3988                data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3989                data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3990                data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3991                data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3992                data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3993                data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3994                data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3995                data->REG_PWM[0] = NCT6775_REG_PWM;
3996                data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3997                data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3998                data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3999                data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
4000                data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4001                data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4002                data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4003                data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4004                data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4005                data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4006                data->REG_CRITICAL_TEMP_TOLERANCE
4007                  = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4008                data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4009                data->CRITICAL_PWM_ENABLE_MASK
4010                  = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4011                data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4012                data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4013                data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4014                data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4015                data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
4016                data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
4017                data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
4018                data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
4019                data->REG_ALARM = NCT6779_REG_ALARM;
4020                data->REG_BEEP = NCT6776_REG_BEEP;
4021
4022                reg_temp = NCT6779_REG_TEMP;
4023                reg_temp_mon = NCT6779_REG_TEMP_MON;
4024                num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4025                num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4026                reg_temp_over = NCT6779_REG_TEMP_OVER;
4027                reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4028                reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4029                reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4030                reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4031
4032                break;
4033        case nct6791:
4034        case nct6792:
4035        case nct6793:
4036        case nct6795:
4037        case nct6796:
4038        case nct6797:
4039        case nct6798:
4040                data->in_num = 15;
4041                data->pwm_num = (data->kind == nct6796 ||
4042                                 data->kind == nct6797 ||
4043                                 data->kind == nct6798) ? 7 : 6;
4044                data->auto_pwm_num = 4;
4045                data->has_fan_div = false;
4046                data->temp_fixed_num = 6;
4047                data->num_temp_alarms = 2;
4048                data->num_temp_beeps = 2;
4049
4050                data->ALARM_BITS = NCT6791_ALARM_BITS;
4051                data->BEEP_BITS = NCT6779_BEEP_BITS;
4052
4053                data->fan_from_reg = fan_from_reg_rpm;
4054                data->fan_from_reg_min = fan_from_reg13;
4055                data->target_temp_mask = 0xff;
4056                data->tolerance_mask = 0x07;
4057                data->speed_tolerance_limit = 63;
4058
4059                switch (data->kind) {
4060                default:
4061                case nct6791:
4062                        data->temp_label = nct6779_temp_label;
4063                        data->temp_mask = NCT6791_TEMP_MASK;
4064                        data->virt_temp_mask = NCT6791_VIRT_TEMP_MASK;
4065                        break;
4066                case nct6792:
4067                        data->temp_label = nct6792_temp_label;
4068                        data->temp_mask = NCT6792_TEMP_MASK;
4069                        data->virt_temp_mask = NCT6792_VIRT_TEMP_MASK;
4070                        break;
4071                case nct6793:
4072                        data->temp_label = nct6793_temp_label;
4073                        data->temp_mask = NCT6793_TEMP_MASK;
4074                        data->virt_temp_mask = NCT6793_VIRT_TEMP_MASK;
4075                        break;
4076                case nct6795:
4077                case nct6797:
4078                        data->temp_label = nct6795_temp_label;
4079                        data->temp_mask = NCT6795_TEMP_MASK;
4080                        data->virt_temp_mask = NCT6795_VIRT_TEMP_MASK;
4081                        break;
4082                case nct6796:
4083                        data->temp_label = nct6796_temp_label;
4084                        data->temp_mask = NCT6796_TEMP_MASK;
4085                        data->virt_temp_mask = NCT6796_VIRT_TEMP_MASK;
4086                        break;
4087                case nct6798:
4088                        data->temp_label = nct6798_temp_label;
4089                        data->temp_mask = NCT6798_TEMP_MASK;
4090                        data->virt_temp_mask = NCT6798_VIRT_TEMP_MASK;
4091                        break;
4092                }
4093
4094                data->REG_CONFIG = NCT6775_REG_CONFIG;
4095                data->REG_VBAT = NCT6775_REG_VBAT;
4096                data->REG_DIODE = NCT6775_REG_DIODE;
4097                data->DIODE_MASK = NCT6775_DIODE_MASK;
4098                data->REG_VIN = NCT6779_REG_IN;
4099                data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
4100                data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
4101                data->REG_TARGET = NCT6775_REG_TARGET;
4102                data->REG_FAN = NCT6779_REG_FAN;
4103                data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4104                data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4105                data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4106                data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4107                data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4108                data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4109                data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4110                data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4111                data->REG_PWM[0] = NCT6775_REG_PWM;
4112                data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4113                data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4114                data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
4115                data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
4116                data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4117                data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4118                data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4119                data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4120                data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4121                data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4122                data->REG_CRITICAL_TEMP_TOLERANCE
4123                  = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4124                data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4125                data->CRITICAL_PWM_ENABLE_MASK
4126                  = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4127                data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4128                data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4129                data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4130                data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4131                data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4132                data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4133                data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4134                data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4135                data->REG_ALARM = NCT6791_REG_ALARM;
4136                if (data->kind == nct6791)
4137                        data->REG_BEEP = NCT6776_REG_BEEP;
4138                else
4139                        data->REG_BEEP = NCT6792_REG_BEEP;
4140
4141                reg_temp = NCT6779_REG_TEMP;
4142                num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4143                if (data->kind == nct6791) {
4144                        reg_temp_mon = NCT6779_REG_TEMP_MON;
4145                        num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4146                } else {
4147                        reg_temp_mon = NCT6792_REG_TEMP_MON;
4148                        num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4149                }
4150                reg_temp_over = NCT6779_REG_TEMP_OVER;
4151                reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4152                reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4153                reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4154                reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4155
4156                break;
4157        default:
4158                return -ENODEV;
4159        }
4160        data->have_in = BIT(data->in_num) - 1;
4161        data->have_temp = 0;
4162
4163        /*
4164         * On some boards, not all available temperature sources are monitored,
4165         * even though some of the monitoring registers are unused.
4166         * Get list of unused monitoring registers, then detect if any fan
4167         * controls are configured to use unmonitored temperature sources.
4168         * If so, assign the unmonitored temperature sources to available
4169         * monitoring registers.
4170         */
4171        mask = 0;
4172        available = 0;
4173        for (i = 0; i < num_reg_temp; i++) {
4174                if (reg_temp[i] == 0)
4175                        continue;
4176
4177                src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4178                if (!src || (mask & BIT(src)))
4179                        available |= BIT(i);
4180
4181                mask |= BIT(src);
4182        }
4183
4184        /*
4185         * Now find unmonitored temperature registers and enable monitoring
4186         * if additional monitoring registers are available.
4187         */
4188        add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4189        add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4190
4191        mask = 0;
4192        s = NUM_TEMP_FIXED;     /* First dynamic temperature attribute */
4193        for (i = 0; i < num_reg_temp; i++) {
4194                if (reg_temp[i] == 0)
4195                        continue;
4196
4197                src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4198                if (!src || (mask & BIT(src)))
4199                        continue;
4200
4201                if (!(data->temp_mask & BIT(src))) {
4202                        dev_info(dev,
4203                                 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4204                                 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4205                        continue;
4206                }
4207
4208                mask |= BIT(src);
4209
4210                /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4211                if (src <= data->temp_fixed_num) {
4212                        data->have_temp |= BIT(src - 1);
4213                        data->have_temp_fixed |= BIT(src - 1);
4214                        data->reg_temp[0][src - 1] = reg_temp[i];
4215                        data->reg_temp[1][src - 1] = reg_temp_over[i];
4216                        data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4217                        if (reg_temp_crit_h && reg_temp_crit_h[i])
4218                                data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4219                        else if (reg_temp_crit[src - 1])
4220                                data->reg_temp[3][src - 1]
4221                                  = reg_temp_crit[src - 1];
4222                        if (reg_temp_crit_l && reg_temp_crit_l[i])
4223                                data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4224                        data->reg_temp_config[src - 1] = reg_temp_config[i];
4225                        data->temp_src[src - 1] = src;
4226                        continue;
4227                }
4228
4229                if (s >= NUM_TEMP)
4230                        continue;
4231
4232                /* Use dynamic index for other sources */
4233                data->have_temp |= BIT(s);
4234                data->reg_temp[0][s] = reg_temp[i];
4235                data->reg_temp[1][s] = reg_temp_over[i];
4236                data->reg_temp[2][s] = reg_temp_hyst[i];
4237                data->reg_temp_config[s] = reg_temp_config[i];
4238                if (reg_temp_crit_h && reg_temp_crit_h[i])
4239                        data->reg_temp[3][s] = reg_temp_crit_h[i];
4240                else if (reg_temp_crit[src - 1])
4241                        data->reg_temp[3][s] = reg_temp_crit[src - 1];
4242                if (reg_temp_crit_l && reg_temp_crit_l[i])
4243                        data->reg_temp[4][s] = reg_temp_crit_l[i];
4244
4245                data->temp_src[s] = src;
4246                s++;
4247        }
4248
4249        /*
4250         * Repeat with temperatures used for fan control.
4251         * This set of registers does not support limits.
4252         */
4253        for (i = 0; i < num_reg_temp_mon; i++) {
4254                if (reg_temp_mon[i] == 0)
4255                        continue;
4256
4257                src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4258                if (!src)
4259                        continue;
4260
4261                if (!(data->temp_mask & BIT(src))) {
4262                        dev_info(dev,
4263                                 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4264                                 src, i, data->REG_TEMP_SEL[i],
4265                                 reg_temp_mon[i]);
4266                        continue;
4267                }
4268
4269                /*
4270                 * For virtual temperature sources, the 'virtual' temperature
4271                 * for each fan reflects a different temperature, and there
4272                 * are no duplicates.
4273                 */
4274                if (!(data->virt_temp_mask & BIT(src))) {
4275                        if (mask & BIT(src))
4276                                continue;
4277                        mask |= BIT(src);
4278                }
4279
4280                /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4281                if (src <= data->temp_fixed_num) {
4282                        if (data->have_temp & BIT(src - 1))
4283                                continue;
4284                        data->have_temp |= BIT(src - 1);
4285                        data->have_temp_fixed |= BIT(src - 1);
4286                        data->reg_temp[0][src - 1] = reg_temp_mon[i];
4287                        data->temp_src[src - 1] = src;
4288                        continue;
4289                }
4290
4291                if (s >= NUM_TEMP)
4292                        continue;
4293
4294                /* Use dynamic index for other sources */
4295                data->have_temp |= BIT(s);
4296                data->reg_temp[0][s] = reg_temp_mon[i];
4297                data->temp_src[s] = src;
4298                s++;
4299        }
4300
4301#ifdef USE_ALTERNATE
4302        /*
4303         * Go through the list of alternate temp registers and enable
4304         * if possible.
4305         * The temperature is already monitored if the respective bit in <mask>
4306         * is set.
4307         */
4308        for (i = 0; i < 31; i++) {
4309                if (!(data->temp_mask & BIT(i + 1)))
4310                        continue;
4311                if (!reg_temp_alternate[i])
4312                        continue;
4313                if (mask & BIT(i + 1))
4314                        continue;
4315                if (i < data->temp_fixed_num) {
4316                        if (data->have_temp & BIT(i))
4317                                continue;
4318                        data->have_temp |= BIT(i);
4319                        data->have_temp_fixed |= BIT(i);
4320                        data->reg_temp[0][i] = reg_temp_alternate[i];
4321                        if (i < num_reg_temp) {
4322                                data->reg_temp[1][i] = reg_temp_over[i];
4323                                data->reg_temp[2][i] = reg_temp_hyst[i];
4324                        }
4325                        data->temp_src[i] = i + 1;
4326                        continue;
4327                }
4328
4329                if (s >= NUM_TEMP)      /* Abort if no more space */
4330                        break;
4331
4332                data->have_temp |= BIT(s);
4333                data->reg_temp[0][s] = reg_temp_alternate[i];
4334                data->temp_src[s] = i + 1;
4335                s++;
4336        }
4337#endif /* USE_ALTERNATE */
4338
4339        /* Initialize the chip */
4340        nct6775_init_device(data);
4341
4342        err = superio_enter(sio_data->sioreg);
4343        if (err)
4344                return err;
4345
4346        cr2a = superio_inb(sio_data->sioreg, 0x2a);
4347        switch (data->kind) {
4348        case nct6775:
4349                data->have_vid = (cr2a & 0x40);
4350                break;
4351        case nct6776:
4352                data->have_vid = (cr2a & 0x60) == 0x40;
4353                break;
4354        case nct6106:
4355        case nct6779:
4356        case nct6791:
4357        case nct6792:
4358        case nct6793:
4359        case nct6795:
4360        case nct6796:
4361        case nct6797:
4362        case nct6798:
4363                break;
4364        }
4365
4366        /*
4367         * Read VID value
4368         * We can get the VID input values directly at logical device D 0xe3.
4369         */
4370        if (data->have_vid) {
4371                superio_select(sio_data->sioreg, NCT6775_LD_VID);
4372                data->vid = superio_inb(sio_data->sioreg, 0xe3);
4373                data->vrm = vid_which_vrm();
4374        }
4375
4376        if (fan_debounce) {
4377                u8 tmp;
4378
4379                superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4380                tmp = superio_inb(sio_data->sioreg,
4381                                  NCT6775_REG_CR_FAN_DEBOUNCE);
4382                switch (data->kind) {
4383                case nct6106:
4384                        tmp |= 0xe0;
4385                        break;
4386                case nct6775:
4387                        tmp |= 0x1e;
4388                        break;
4389                case nct6776:
4390                case nct6779:
4391                        tmp |= 0x3e;
4392                        break;
4393                case nct6791:
4394                case nct6792:
4395                case nct6793:
4396                case nct6795:
4397                case nct6796:
4398                case nct6797:
4399                case nct6798:
4400                        tmp |= 0x7e;
4401                        break;
4402                }
4403                superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4404                             tmp);
4405                dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4406                         data->name);
4407        }
4408
4409        nct6775_check_fan_inputs(data);
4410
4411        superio_exit(sio_data->sioreg);
4412
4413        /* Read fan clock dividers immediately */
4414        nct6775_init_fan_common(dev, data);
4415
4416        /* Register sysfs hooks */
4417        group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4418                                          data->pwm_num);
4419        if (IS_ERR(group))
4420                return PTR_ERR(group);
4421
4422        data->groups[num_attr_groups++] = group;
4423
4424        group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4425                                          fls(data->have_in));
4426        if (IS_ERR(group))
4427                return PTR_ERR(group);
4428
4429        data->groups[num_attr_groups++] = group;
4430
4431        group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4432                                          fls(data->has_fan));
4433        if (IS_ERR(group))
4434                return PTR_ERR(group);
4435
4436        data->groups[num_attr_groups++] = group;
4437
4438        group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4439                                          fls(data->have_temp));
4440        if (IS_ERR(group))
4441                return PTR_ERR(group);
4442
4443        data->groups[num_attr_groups++] = group;
4444        data->groups[num_attr_groups++] = &nct6775_group_other;
4445
4446        hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4447                                                           data, data->groups);
4448        return PTR_ERR_OR_ZERO(hwmon_dev);
4449}
4450
4451static void nct6791_enable_io_mapping(int sioaddr)
4452{
4453        int val;
4454
4455        val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4456        if (val & 0x10) {
4457                pr_info("Enabling hardware monitor logical device mappings.\n");
4458                superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4459                             val & ~0x10);
4460        }
4461}
4462
4463static int __maybe_unused nct6775_suspend(struct device *dev)
4464{
4465        struct nct6775_data *data = nct6775_update_device(dev);
4466
4467        mutex_lock(&data->update_lock);
4468        data->vbat = nct6775_read_value(data, data->REG_VBAT);
4469        if (data->kind == nct6775) {
4470                data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4471                data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4472        }
4473        mutex_unlock(&data->update_lock);
4474
4475        return 0;
4476}
4477
4478static int __maybe_unused nct6775_resume(struct device *dev)
4479{
4480        struct nct6775_data *data = dev_get_drvdata(dev);
4481        int sioreg = data->sioreg;
4482        int i, j, err = 0;
4483        u8 reg;
4484
4485        mutex_lock(&data->update_lock);
4486        data->bank = 0xff;              /* Force initial bank selection */
4487
4488        err = superio_enter(sioreg);
4489        if (err)
4490                goto abort;
4491
4492        superio_select(sioreg, NCT6775_LD_HWM);
4493        reg = superio_inb(sioreg, SIO_REG_ENABLE);
4494        if (reg != data->sio_reg_enable)
4495                superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4496
4497        if (data->kind == nct6791 || data->kind == nct6792 ||
4498            data->kind == nct6793 || data->kind == nct6795 ||
4499            data->kind == nct6796 || data->kind == nct6797 ||
4500            data->kind == nct6798)
4501                nct6791_enable_io_mapping(sioreg);
4502
4503        superio_exit(sioreg);
4504
4505        /* Restore limits */
4506        for (i = 0; i < data->in_num; i++) {
4507                if (!(data->have_in & BIT(i)))
4508                        continue;
4509
4510                nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4511                                    data->in[i][1]);
4512                nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4513                                    data->in[i][2]);
4514        }
4515
4516        for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4517                if (!(data->has_fan_min & BIT(i)))
4518                        continue;
4519
4520                nct6775_write_value(data, data->REG_FAN_MIN[i],
4521                                    data->fan_min[i]);
4522        }
4523
4524        for (i = 0; i < NUM_TEMP; i++) {
4525                if (!(data->have_temp & BIT(i)))
4526                        continue;
4527
4528                for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4529                        if (data->reg_temp[j][i])
4530                                nct6775_write_temp(data, data->reg_temp[j][i],
4531                                                   data->temp[j][i]);
4532        }
4533
4534        /* Restore other settings */
4535        nct6775_write_value(data, data->REG_VBAT, data->vbat);
4536        if (data->kind == nct6775) {
4537                nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4538                nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4539        }
4540
4541abort:
4542        /* Force re-reading all values */
4543        data->valid = false;
4544        mutex_unlock(&data->update_lock);
4545
4546        return err;
4547}
4548
4549static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4550
4551static struct platform_driver nct6775_driver = {
4552        .driver = {
4553                .name   = DRVNAME,
4554                .pm     = &nct6775_dev_pm_ops,
4555        },
4556        .probe          = nct6775_probe,
4557};
4558
4559/* nct6775_find() looks for a '627 in the Super-I/O config space */
4560static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4561{
4562        u16 val;
4563        int err;
4564        int addr;
4565
4566        err = superio_enter(sioaddr);
4567        if (err)
4568                return err;
4569
4570        val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4571                superio_inb(sioaddr, SIO_REG_DEVID + 1);
4572        if (force_id && val != 0xffff)
4573                val = force_id;
4574
4575        switch (val & SIO_ID_MASK) {
4576        case SIO_NCT6106_ID:
4577                sio_data->kind = nct6106;
4578                break;
4579        case SIO_NCT6775_ID:
4580                sio_data->kind = nct6775;
4581                break;
4582        case SIO_NCT6776_ID:
4583                sio_data->kind = nct6776;
4584                break;
4585        case SIO_NCT6779_ID:
4586                sio_data->kind = nct6779;
4587                break;
4588        case SIO_NCT6791_ID:
4589                sio_data->kind = nct6791;
4590                break;
4591        case SIO_NCT6792_ID:
4592                sio_data->kind = nct6792;
4593                break;
4594        case SIO_NCT6793_ID:
4595                sio_data->kind = nct6793;
4596                break;
4597        case SIO_NCT6795_ID:
4598                sio_data->kind = nct6795;
4599                break;
4600        case SIO_NCT6796_ID:
4601                sio_data->kind = nct6796;
4602                break;
4603        case SIO_NCT6797_ID:
4604                sio_data->kind = nct6797;
4605                break;
4606        case SIO_NCT6798_ID:
4607                sio_data->kind = nct6798;
4608                break;
4609        default:
4610                if (val != 0xffff)
4611                        pr_debug("unsupported chip ID: 0x%04x\n", val);
4612                superio_exit(sioaddr);
4613                return -ENODEV;
4614        }
4615
4616        /* We have a known chip, find the HWM I/O address */
4617        superio_select(sioaddr, NCT6775_LD_HWM);
4618        val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4619            | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4620        addr = val & IOREGION_ALIGNMENT;
4621        if (addr == 0) {
4622                pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4623                superio_exit(sioaddr);
4624                return -ENODEV;
4625        }
4626
4627        /* Activate logical device if needed */
4628        val = superio_inb(sioaddr, SIO_REG_ENABLE);
4629        if (!(val & 0x01)) {
4630                pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4631                superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4632        }
4633
4634        if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4635            sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4636            sio_data->kind == nct6796 || sio_data->kind == nct6797 ||
4637            sio_data->kind == nct6798)
4638                nct6791_enable_io_mapping(sioaddr);
4639
4640        superio_exit(sioaddr);
4641        pr_info("Found %s or compatible chip at %#x:%#x\n",
4642                nct6775_sio_names[sio_data->kind], sioaddr, addr);
4643        sio_data->sioreg = sioaddr;
4644
4645        return addr;
4646}
4647
4648/*
4649 * when Super-I/O functions move to a separate file, the Super-I/O
4650 * bus will manage the lifetime of the device and this module will only keep
4651 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4652 * must keep track of the device
4653 */
4654static struct platform_device *pdev[2];
4655
4656static int __init sensors_nct6775_init(void)
4657{
4658        int i, err;
4659        bool found = false;
4660        int address;
4661        struct resource res;
4662        struct nct6775_sio_data sio_data;
4663        int sioaddr[2] = { 0x2e, 0x4e };
4664
4665        err = platform_driver_register(&nct6775_driver);
4666        if (err)
4667                return err;
4668
4669        /*
4670         * initialize sio_data->kind and sio_data->sioreg.
4671         *
4672         * when Super-I/O functions move to a separate file, the Super-I/O
4673         * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4674         * nct6775 hardware monitor, and call probe()
4675         */
4676        for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4677                address = nct6775_find(sioaddr[i], &sio_data);
4678                if (address <= 0)
4679                        continue;
4680
4681                found = true;
4682
4683                pdev[i] = platform_device_alloc(DRVNAME, address);
4684                if (!pdev[i]) {
4685                        err = -ENOMEM;
4686                        goto exit_device_unregister;
4687                }
4688
4689                err = platform_device_add_data(pdev[i], &sio_data,
4690                                               sizeof(struct nct6775_sio_data));
4691                if (err)
4692                        goto exit_device_put;
4693
4694                memset(&res, 0, sizeof(res));
4695                res.name = DRVNAME;
4696                res.start = address + IOREGION_OFFSET;
4697                res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4698                res.flags = IORESOURCE_IO;
4699
4700                err = acpi_check_resource_conflict(&res);
4701                if (err) {
4702                        platform_device_put(pdev[i]);
4703                        pdev[i] = NULL;
4704                        continue;
4705                }
4706
4707                err = platform_device_add_resources(pdev[i], &res, 1);
4708                if (err)
4709                        goto exit_device_put;
4710
4711                /* platform_device_add calls probe() */
4712                err = platform_device_add(pdev[i]);
4713                if (err)
4714                        goto exit_device_put;
4715        }
4716        if (!found) {
4717                err = -ENODEV;
4718                goto exit_unregister;
4719        }
4720
4721        return 0;
4722
4723exit_device_put:
4724        platform_device_put(pdev[i]);
4725exit_device_unregister:
4726        while (--i >= 0) {
4727                if (pdev[i])
4728                        platform_device_unregister(pdev[i]);
4729        }
4730exit_unregister:
4731        platform_driver_unregister(&nct6775_driver);
4732        return err;
4733}
4734
4735static void __exit sensors_nct6775_exit(void)
4736{
4737        int i;
4738
4739        for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4740                if (pdev[i])
4741                        platform_device_unregister(pdev[i]);
4742        }
4743        platform_driver_unregister(&nct6775_driver);
4744}
4745
4746MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4747MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4748MODULE_LICENSE("GPL");
4749
4750module_init(sensors_nct6775_init);
4751module_exit(sensors_nct6775_exit);
4752