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10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21
22#define SCL_WAIT_TIMEOUT_NS 25000000
23#define I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
24#define I2C_STOP_TIMEOUT (msecs_to_jiffies(100))
25#define FIFO_SIZE 8
26#define SEQ_LEN 2
27
28#define GLOBAL_CONTROL 0x00
29#define GLOBAL_MST_EN BIT(0)
30#define GLOBAL_SLV_EN BIT(1)
31#define GLOBAL_IBML_EN BIT(2)
32#define INTERRUPT_STATUS 0x04
33#define INTERRUPT_ENABLE 0x08
34#define INT_SLV BIT(1)
35#define INT_MST BIT(0)
36#define WAIT_TIMER_CONTROL 0x0c
37#define WT_EN BIT(15)
38#define WT_VALUE(_x) ((_x) & 0x7fff)
39#define IBML_TIMEOUT 0x10
40#define IBML_LOW_MEXT 0x14
41#define IBML_LOW_SEXT 0x18
42#define TIMER_CLOCK_DIV 0x1c
43#define I2C_BUS_MONITOR 0x20
44#define BM_SDAC BIT(3)
45#define BM_SCLC BIT(2)
46#define BM_SDAS BIT(1)
47#define BM_SCLS BIT(0)
48#define SOFT_RESET 0x24
49#define MST_COMMAND 0x28
50#define CMD_BUSY (1<<3)
51#define CMD_MANUAL (0x00 | CMD_BUSY)
52#define CMD_AUTO (0x01 | CMD_BUSY)
53#define CMD_SEQUENCE (0x02 | CMD_BUSY)
54#define MST_RX_XFER 0x2c
55#define MST_TX_XFER 0x30
56#define MST_ADDR_1 0x34
57#define MST_ADDR_2 0x38
58#define MST_DATA 0x3c
59#define MST_TX_FIFO 0x40
60#define MST_RX_FIFO 0x44
61#define MST_INT_ENABLE 0x48
62#define MST_INT_STATUS 0x4c
63#define MST_STATUS_RFL (1 << 13)
64#define MST_STATUS_TFL (1 << 12)
65#define MST_STATUS_SNS (1 << 11)
66#define MST_STATUS_SS (1 << 10)
67#define MST_STATUS_SCC (1 << 9)
68#define MST_STATUS_IP (1 << 8)
69#define MST_STATUS_TSS (1 << 7)
70#define MST_STATUS_AL (1 << 6)
71#define MST_STATUS_ND (1 << 5)
72#define MST_STATUS_NA (1 << 4)
73#define MST_STATUS_NAK (MST_STATUS_NA | \
74 MST_STATUS_ND)
75#define MST_STATUS_ERR (MST_STATUS_NAK | \
76 MST_STATUS_AL | \
77 MST_STATUS_IP)
78#define MST_TX_BYTES_XFRD 0x50
79#define MST_RX_BYTES_XFRD 0x54
80#define SCL_HIGH_PERIOD 0x80
81#define SCL_LOW_PERIOD 0x84
82#define SPIKE_FLTR_LEN 0x88
83#define SDA_SETUP_TIME 0x8c
84#define SDA_HOLD_TIME 0x90
85
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100
101struct axxia_i2c_dev {
102 void __iomem *base;
103 struct i2c_msg *msg;
104 struct i2c_msg *msg_r;
105 size_t msg_xfrd;
106 size_t msg_xfrd_r;
107 int msg_err;
108 struct completion msg_complete;
109 struct device *dev;
110 struct i2c_adapter adapter;
111 struct clk *i2c_clk;
112 u32 bus_clk_rate;
113 bool last;
114};
115
116static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
117{
118 u32 int_en;
119
120 int_en = readl(idev->base + MST_INT_ENABLE);
121 writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
122}
123
124static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
125{
126 u32 int_en;
127
128 int_en = readl(idev->base + MST_INT_ENABLE);
129 writel(int_en | mask, idev->base + MST_INT_ENABLE);
130}
131
132
133
134
135static u32 ns_to_clk(u64 ns, u32 clk_mhz)
136{
137 return div_u64(ns * clk_mhz, 1000);
138}
139
140static int axxia_i2c_init(struct axxia_i2c_dev *idev)
141{
142 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
143 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
144 u32 t_setup;
145 u32 t_high, t_low;
146 u32 tmo_clk;
147 u32 prescale;
148 unsigned long timeout;
149
150 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
151 idev->bus_clk_rate, clk_mhz, divisor);
152
153
154 writel(0x01, idev->base + SOFT_RESET);
155 timeout = jiffies + msecs_to_jiffies(100);
156 while (readl(idev->base + SOFT_RESET) & 1) {
157 if (time_after(jiffies, timeout)) {
158 dev_warn(idev->dev, "Soft reset failed\n");
159 break;
160 }
161 }
162
163
164 writel(0x1, idev->base + GLOBAL_CONTROL);
165
166 if (idev->bus_clk_rate <= 100000) {
167
168 t_high = divisor * 1 / 2;
169 t_low = divisor * 1 / 2;
170 t_setup = ns_to_clk(250, clk_mhz);
171 } else {
172
173 t_high = divisor * 1 / 3;
174 t_low = divisor * 2 / 3;
175 t_setup = ns_to_clk(100, clk_mhz);
176 }
177
178
179 writel(t_high, idev->base + SCL_HIGH_PERIOD);
180
181 writel(t_low, idev->base + SCL_LOW_PERIOD);
182
183 writel(t_setup, idev->base + SDA_SETUP_TIME);
184
185 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
186
187 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
188
189
190 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
191
192
193 for (prescale = 0; prescale < 15; ++prescale) {
194 if (tmo_clk <= 0x7fff)
195 break;
196 tmo_clk >>= 1;
197 }
198 if (tmo_clk > 0x7fff)
199 tmo_clk = 0x7fff;
200
201
202 writel(prescale, idev->base + TIMER_CLOCK_DIV);
203
204 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
205
206
207 i2c_int_disable(idev, ~0);
208
209
210 writel(0x01, idev->base + INTERRUPT_ENABLE);
211
212 return 0;
213}
214
215static int i2c_m_rd(const struct i2c_msg *msg)
216{
217 return (msg->flags & I2C_M_RD) != 0;
218}
219
220static int i2c_m_ten(const struct i2c_msg *msg)
221{
222 return (msg->flags & I2C_M_TEN) != 0;
223}
224
225static int i2c_m_recv_len(const struct i2c_msg *msg)
226{
227 return (msg->flags & I2C_M_RECV_LEN) != 0;
228}
229
230
231
232
233
234static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
235{
236 struct i2c_msg *msg = idev->msg_r;
237 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
238 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
239
240 while (bytes_to_transfer-- > 0) {
241 int c = readl(idev->base + MST_DATA);
242
243 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
244
245
246
247 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
248 idev->msg_err = -EPROTO;
249 i2c_int_disable(idev, ~MST_STATUS_TSS);
250 complete(&idev->msg_complete);
251 break;
252 }
253 msg->len = 1 + c;
254 writel(msg->len, idev->base + MST_RX_XFER);
255 }
256 msg->buf[idev->msg_xfrd_r++] = c;
257 }
258
259 return 0;
260}
261
262
263
264
265
266static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
267{
268 struct i2c_msg *msg = idev->msg;
269 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
270 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
271 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
272
273 while (bytes_to_transfer-- > 0)
274 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
275
276 return ret;
277}
278
279static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
280{
281 struct axxia_i2c_dev *idev = _dev;
282 u32 status;
283
284 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST))
285 return IRQ_NONE;
286
287
288 status = readl(idev->base + MST_INT_STATUS);
289
290 if (!idev->msg) {
291 dev_warn(idev->dev, "unexpected interrupt\n");
292 goto out;
293 }
294
295
296 if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
297 axxia_i2c_empty_rx_fifo(idev);
298
299
300 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
301 if (axxia_i2c_fill_tx_fifo(idev) == 0)
302 i2c_int_disable(idev, MST_STATUS_TFL);
303 }
304
305 if (unlikely(status & MST_STATUS_ERR)) {
306
307 i2c_int_disable(idev, ~0);
308 if (status & MST_STATUS_AL)
309 idev->msg_err = -EAGAIN;
310 else if (status & MST_STATUS_NAK)
311 idev->msg_err = -ENXIO;
312 else
313 idev->msg_err = -EIO;
314 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
315 status,
316 idev->msg->addr,
317 readl(idev->base + MST_RX_BYTES_XFRD),
318 readl(idev->base + MST_RX_XFER),
319 readl(idev->base + MST_TX_BYTES_XFRD),
320 readl(idev->base + MST_TX_XFER));
321 complete(&idev->msg_complete);
322 } else if (status & MST_STATUS_SCC) {
323
324 i2c_int_disable(idev, ~MST_STATUS_TSS);
325 complete(&idev->msg_complete);
326 } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
327
328 int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
329
330 i2c_int_disable(idev, mask);
331 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
332 axxia_i2c_empty_rx_fifo(idev);
333 complete(&idev->msg_complete);
334 } else if (status & MST_STATUS_TSS) {
335
336 idev->msg_err = -ETIMEDOUT;
337 i2c_int_disable(idev, ~MST_STATUS_TSS);
338 complete(&idev->msg_complete);
339 }
340
341out:
342
343 writel(INT_MST, idev->base + INTERRUPT_STATUS);
344
345 return IRQ_HANDLED;
346}
347
348static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
349{
350 u32 addr_1, addr_2;
351
352 if (i2c_m_ten(msg)) {
353
354
355
356
357 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
358 if (i2c_m_rd(msg))
359 addr_1 |= 1;
360 addr_2 = msg->addr & 0xFF;
361 } else {
362
363
364
365
366 addr_1 = i2c_8bit_addr_from_msg(msg);
367 addr_2 = 0;
368 }
369
370 writel(addr_1, idev->base + MST_ADDR_1);
371 writel(addr_2, idev->base + MST_ADDR_2);
372}
373
374
375
376
377
378static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
379{
380 unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
381
382 do {
383 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
384 return 0;
385 usleep_range(1, 100);
386 } while (time_before(jiffies, timeout));
387
388 return -ETIMEDOUT;
389}
390
391static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
392{
393 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
394 u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
395 unsigned long time_left;
396
397 axxia_i2c_set_addr(idev, &msgs[0]);
398
399 writel(msgs[0].len, idev->base + MST_TX_XFER);
400 writel(rlen, idev->base + MST_RX_XFER);
401
402 idev->msg = &msgs[0];
403 idev->msg_r = &msgs[1];
404 idev->msg_xfrd = 0;
405 idev->msg_xfrd_r = 0;
406 idev->last = true;
407 axxia_i2c_fill_tx_fifo(idev);
408
409 writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
410
411 reinit_completion(&idev->msg_complete);
412 i2c_int_enable(idev, int_mask);
413
414 time_left = wait_for_completion_timeout(&idev->msg_complete,
415 I2C_XFER_TIMEOUT);
416
417 if (idev->msg_err == -ENXIO) {
418 if (axxia_i2c_handle_seq_nak(idev))
419 axxia_i2c_init(idev);
420 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
421 dev_warn(idev->dev, "busy after xfer\n");
422 }
423
424 if (time_left == 0) {
425 idev->msg_err = -ETIMEDOUT;
426 i2c_recover_bus(&idev->adapter);
427 axxia_i2c_init(idev);
428 }
429
430 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
431 axxia_i2c_init(idev);
432
433 return idev->msg_err;
434}
435
436static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
437 bool last)
438{
439 u32 int_mask = MST_STATUS_ERR;
440 u32 rx_xfer, tx_xfer;
441 unsigned long time_left;
442 unsigned int wt_value;
443
444 idev->msg = msg;
445 idev->msg_r = msg;
446 idev->msg_xfrd = 0;
447 idev->msg_xfrd_r = 0;
448 idev->last = last;
449 reinit_completion(&idev->msg_complete);
450
451 axxia_i2c_set_addr(idev, msg);
452
453 if (i2c_m_rd(msg)) {
454
455 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
456 tx_xfer = 0;
457 } else {
458
459 rx_xfer = 0;
460 tx_xfer = msg->len;
461 }
462
463 writel(rx_xfer, idev->base + MST_RX_XFER);
464 writel(tx_xfer, idev->base + MST_TX_XFER);
465
466 if (i2c_m_rd(msg))
467 int_mask |= MST_STATUS_RFL;
468 else if (axxia_i2c_fill_tx_fifo(idev) != 0)
469 int_mask |= MST_STATUS_TFL;
470
471 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
472
473 writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
474
475 if (idev->msg_err)
476 goto out;
477
478 if (!last) {
479 writel(CMD_MANUAL, idev->base + MST_COMMAND);
480 int_mask |= MST_STATUS_SNS;
481 } else {
482 writel(CMD_AUTO, idev->base + MST_COMMAND);
483 int_mask |= MST_STATUS_SS;
484 }
485
486 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
487
488 i2c_int_enable(idev, int_mask);
489
490 time_left = wait_for_completion_timeout(&idev->msg_complete,
491 I2C_XFER_TIMEOUT);
492
493 i2c_int_disable(idev, int_mask);
494
495 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
496 dev_warn(idev->dev, "busy after xfer\n");
497
498 if (time_left == 0) {
499 idev->msg_err = -ETIMEDOUT;
500 i2c_recover_bus(&idev->adapter);
501 axxia_i2c_init(idev);
502 }
503
504out:
505 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
506 idev->msg_err != -ETIMEDOUT)
507 axxia_i2c_init(idev);
508
509 return idev->msg_err;
510}
511
512
513
514
515
516
517static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
518{
519 return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
520 msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
521 msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
522}
523
524static int
525axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
526{
527 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
528 int i;
529 int ret = 0;
530
531 idev->msg_err = 0;
532
533 if (axxia_i2c_sequence_ok(msgs, num)) {
534 ret = axxia_i2c_xfer_seq(idev, msgs);
535 return ret ? : SEQ_LEN;
536 }
537
538 i2c_int_enable(idev, MST_STATUS_TSS);
539
540 for (i = 0; ret == 0 && i < num; ++i)
541 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
542
543 return ret ? : i;
544}
545
546static int axxia_i2c_get_scl(struct i2c_adapter *adap)
547{
548 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
549
550 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
551}
552
553static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
554{
555 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
556 u32 tmp;
557
558
559 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
560 if (!val)
561 tmp |= BM_SCLC;
562 writel(tmp, idev->base + I2C_BUS_MONITOR);
563}
564
565static int axxia_i2c_get_sda(struct i2c_adapter *adap)
566{
567 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
568
569 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
570}
571
572static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
573 .recover_bus = i2c_generic_scl_recovery,
574 .get_scl = axxia_i2c_get_scl,
575 .set_scl = axxia_i2c_set_scl,
576 .get_sda = axxia_i2c_get_sda,
577};
578
579static u32 axxia_i2c_func(struct i2c_adapter *adap)
580{
581 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
582 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
583 return caps;
584}
585
586static const struct i2c_algorithm axxia_i2c_algo = {
587 .master_xfer = axxia_i2c_xfer,
588 .functionality = axxia_i2c_func,
589};
590
591static const struct i2c_adapter_quirks axxia_i2c_quirks = {
592 .max_read_len = 255,
593 .max_write_len = 255,
594};
595
596static int axxia_i2c_probe(struct platform_device *pdev)
597{
598 struct device_node *np = pdev->dev.of_node;
599 struct axxia_i2c_dev *idev = NULL;
600 struct resource *res;
601 void __iomem *base;
602 int irq;
603 int ret = 0;
604
605 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
606 if (!idev)
607 return -ENOMEM;
608
609 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
610 base = devm_ioremap_resource(&pdev->dev, res);
611 if (IS_ERR(base))
612 return PTR_ERR(base);
613
614 irq = platform_get_irq(pdev, 0);
615 if (irq < 0) {
616 dev_err(&pdev->dev, "missing interrupt resource\n");
617 return irq;
618 }
619
620 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
621 if (IS_ERR(idev->i2c_clk)) {
622 dev_err(&pdev->dev, "missing clock\n");
623 return PTR_ERR(idev->i2c_clk);
624 }
625
626 idev->base = base;
627 idev->dev = &pdev->dev;
628 init_completion(&idev->msg_complete);
629
630 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
631 if (idev->bus_clk_rate == 0)
632 idev->bus_clk_rate = 100000;
633
634 ret = clk_prepare_enable(idev->i2c_clk);
635 if (ret) {
636 dev_err(&pdev->dev, "failed to enable clock\n");
637 return ret;
638 }
639
640 ret = axxia_i2c_init(idev);
641 if (ret) {
642 dev_err(&pdev->dev, "failed to initialize\n");
643 goto error_disable_clk;
644 }
645
646 ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0,
647 pdev->name, idev);
648 if (ret) {
649 dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq);
650 goto error_disable_clk;
651 }
652
653 i2c_set_adapdata(&idev->adapter, idev);
654 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
655 idev->adapter.owner = THIS_MODULE;
656 idev->adapter.algo = &axxia_i2c_algo;
657 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
658 idev->adapter.quirks = &axxia_i2c_quirks;
659 idev->adapter.dev.parent = &pdev->dev;
660 idev->adapter.dev.of_node = pdev->dev.of_node;
661
662 platform_set_drvdata(pdev, idev);
663
664 ret = i2c_add_adapter(&idev->adapter);
665 if (ret)
666 goto error_disable_clk;
667
668 return 0;
669
670error_disable_clk:
671 clk_disable_unprepare(idev->i2c_clk);
672 return ret;
673}
674
675static int axxia_i2c_remove(struct platform_device *pdev)
676{
677 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
678
679 clk_disable_unprepare(idev->i2c_clk);
680 i2c_del_adapter(&idev->adapter);
681
682 return 0;
683}
684
685
686static const struct of_device_id axxia_i2c_of_match[] = {
687 { .compatible = "lsi,api2c", },
688 {},
689};
690
691MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
692
693static struct platform_driver axxia_i2c_driver = {
694 .probe = axxia_i2c_probe,
695 .remove = axxia_i2c_remove,
696 .driver = {
697 .name = "axxia-i2c",
698 .of_match_table = axxia_i2c_of_match,
699 },
700};
701
702module_platform_driver(axxia_i2c_driver);
703
704MODULE_DESCRIPTION("Axxia I2C Bus driver");
705MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
706MODULE_LICENSE("GPL v2");
707