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5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <linux/errno.h>
10#include <linux/i2c.h>
11#include <linux/fs.h>
12#include <linux/io.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/jiffies.h>
16#include <linux/pci.h>
17#include <linux/mutex.h>
18#include <linux/ktime.h>
19#include <linux/slab.h>
20
21#define PCH_EVENT_SET 0
22#define PCH_EVENT_NONE 1
23#define PCH_MAX_CLK 100000
24#define PCH_BUFFER_MODE_ENABLE 0x0002
25#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008
26
27#define PCH_I2CSADR 0x00
28#define PCH_I2CCTL 0x04
29#define PCH_I2CSR 0x08
30#define PCH_I2CDR 0x0C
31#define PCH_I2CMON 0x10
32#define PCH_I2CBC 0x14
33#define PCH_I2CMOD 0x18
34#define PCH_I2CBUFSLV 0x1C
35#define PCH_I2CBUFSUB 0x20
36#define PCH_I2CBUFFOR 0x24
37#define PCH_I2CBUFCTL 0x28
38#define PCH_I2CBUFMSK 0x2C
39#define PCH_I2CBUFSTA 0x30
40#define PCH_I2CBUFLEV 0x34
41#define PCH_I2CESRFOR 0x38
42#define PCH_I2CESRCTL 0x3C
43#define PCH_I2CESRMSK 0x40
44#define PCH_I2CESRSTA 0x44
45#define PCH_I2CTMR 0x48
46#define PCH_I2CSRST 0xFC
47#define PCH_I2CNF 0xF8
48
49#define BUS_IDLE_TIMEOUT 20
50#define PCH_I2CCTL_I2CMEN 0x0080
51#define TEN_BIT_ADDR_DEFAULT 0xF000
52#define TEN_BIT_ADDR_MASK 0xF0
53#define PCH_START 0x0020
54#define PCH_RESTART 0x0004
55#define PCH_ESR_START 0x0001
56#define PCH_BUFF_START 0x1
57#define PCH_REPSTART 0x0004
58#define PCH_ACK 0x0008
59#define PCH_GETACK 0x0001
60#define CLR_REG 0x0
61#define I2C_RD 0x1
62#define I2CMCF_BIT 0x0080
63#define I2CMIF_BIT 0x0002
64#define I2CMAL_BIT 0x0010
65#define I2CBMFI_BIT 0x0001
66#define I2CBMAL_BIT 0x0002
67#define I2CBMNA_BIT 0x0004
68#define I2CBMTO_BIT 0x0008
69#define I2CBMIS_BIT 0x0010
70#define I2CESRFI_BIT 0X0001
71#define I2CESRTO_BIT 0x0002
72#define I2CESRFIIE_BIT 0x1
73#define I2CESRTOIE_BIT 0x2
74#define I2CBMDZ_BIT 0x0040
75#define I2CBMAG_BIT 0x0020
76#define I2CMBB_BIT 0x0020
77#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
78 I2CBMTO_BIT | I2CBMIS_BIT)
79#define I2C_ADDR_MSK 0xFF
80#define I2C_MSB_2B_MSK 0x300
81#define FAST_MODE_CLK 400
82#define FAST_MODE_EN 0x0001
83#define SUB_ADDR_LEN_MAX 4
84#define BUF_LEN_MAX 32
85#define PCH_BUFFER_MODE 0x1
86#define EEPROM_SW_RST_MODE 0x0002
87#define NORMAL_INTR_ENBL 0x0300
88#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
89#define EEPROM_RST_INTR_DISBL 0x0
90#define BUFFER_MODE_INTR_ENBL 0x001F
91#define BUFFER_MODE_INTR_DISBL 0x0
92#define NORMAL_MODE 0x0
93#define BUFFER_MODE 0x1
94#define EEPROM_SR_MODE 0x2
95#define I2C_TX_MODE 0x0010
96#define PCH_BUF_TX 0xFFF7
97#define PCH_BUF_RD 0x0008
98#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
99 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
100#define I2CMAL_EVENT 0x0001
101#define I2CMCF_EVENT 0x0002
102#define I2CBMFI_EVENT 0x0004
103#define I2CBMAL_EVENT 0x0008
104#define I2CBMNA_EVENT 0x0010
105#define I2CBMTO_EVENT 0x0020
106#define I2CBMIS_EVENT 0x0040
107#define I2CESRFI_EVENT 0x0080
108#define I2CESRTO_EVENT 0x0100
109#define PCI_DEVICE_ID_PCH_I2C 0x8817
110
111#define pch_dbg(adap, fmt, arg...) \
112 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
113
114#define pch_err(adap, fmt, arg...) \
115 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
116
117#define pch_pci_err(pdev, fmt, arg...) \
118 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
119
120#define pch_pci_dbg(pdev, fmt, arg...) \
121 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
122
123
124
125
126
127
128
129#define PCH_I2C_MAX_DEV 2
130
131
132
133
134
135
136
137
138
139
140struct i2c_algo_pch_data {
141 struct i2c_adapter pch_adapter;
142 struct adapter_info *p_adapter_info;
143 void __iomem *pch_base_address;
144 int pch_buff_mode_en;
145 u32 pch_event_flag;
146 bool pch_i2c_xfer_in_progress;
147};
148
149
150
151
152
153
154
155
156
157
158
159struct adapter_info {
160 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
161 bool pch_i2c_suspended;
162 int ch_num;
163};
164
165
166static int pch_i2c_speed = 100;
167static int pch_clk = 50000;
168static wait_queue_head_t pch_event;
169static DEFINE_MUTEX(pch_mutex);
170
171
172#define PCI_DEVICE_ID_ML7213_I2C 0x802D
173#define PCI_DEVICE_ID_ML7223_I2C 0x8010
174#define PCI_DEVICE_ID_ML7831_I2C 0x8817
175
176static const struct pci_device_id pch_pcidev_id[] = {
177 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
178 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
179 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
180 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
181 {0,}
182};
183
184static irqreturn_t pch_i2c_handler(int irq, void *pData);
185
186static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
187{
188 u32 val;
189 val = ioread32(addr + offset);
190 val |= bitmask;
191 iowrite32(val, addr + offset);
192}
193
194static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
195{
196 u32 val;
197 val = ioread32(addr + offset);
198 val &= (~bitmask);
199 iowrite32(val, addr + offset);
200}
201
202
203
204
205
206static void pch_i2c_init(struct i2c_algo_pch_data *adap)
207{
208 void __iomem *p = adap->pch_base_address;
209 u32 pch_i2cbc;
210 u32 pch_i2ctmr;
211 u32 reg_value;
212
213
214 iowrite32(0x01, p + PCH_I2CSRST);
215 msleep(20);
216 iowrite32(0x0, p + PCH_I2CSRST);
217
218
219 iowrite32(0x21, p + PCH_I2CNF);
220
221 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
222
223 if (pch_i2c_speed != 400)
224 pch_i2c_speed = 100;
225
226 reg_value = PCH_I2CCTL_I2CMEN;
227 if (pch_i2c_speed == FAST_MODE_CLK) {
228 reg_value |= FAST_MODE_EN;
229 pch_dbg(adap, "Fast mode enabled\n");
230 }
231
232 if (pch_clk > PCH_MAX_CLK)
233 pch_clk = 62500;
234
235 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
236
237 iowrite32(pch_i2cbc, p + PCH_I2CBC);
238
239 pch_i2ctmr = (pch_clk) / 8;
240 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
241
242 reg_value |= NORMAL_INTR_ENBL;
243 iowrite32(reg_value, p + PCH_I2CCTL);
244
245 pch_dbg(adap,
246 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
247 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
248
249 init_waitqueue_head(&pch_event);
250}
251
252
253
254
255
256
257static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
258 s32 timeout)
259{
260 void __iomem *p = adap->pch_base_address;
261 int schedule = 0;
262 unsigned long end = jiffies + msecs_to_jiffies(timeout);
263
264 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
265 if (time_after(jiffies, end)) {
266 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
267 pch_err(adap, "%s: Timeout Error.return%d\n",
268 __func__, -ETIME);
269 pch_i2c_init(adap);
270
271 return -ETIME;
272 }
273
274 if (!schedule)
275
276 udelay(5);
277 else
278
279 usleep_range(20, 1000);
280
281 schedule = 1;
282 }
283
284 return 0;
285}
286
287
288
289
290
291
292
293static void pch_i2c_start(struct i2c_algo_pch_data *adap)
294{
295 void __iomem *p = adap->pch_base_address;
296 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
297 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
298}
299
300
301
302
303
304static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
305{
306 void __iomem *p = adap->pch_base_address;
307 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
308
309 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
310}
311
312static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
313{
314 long ret;
315 void __iomem *p = adap->pch_base_address;
316
317 ret = wait_event_timeout(pch_event,
318 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
319 if (!ret) {
320 pch_err(adap, "%s:wait-event timeout\n", __func__);
321 adap->pch_event_flag = 0;
322 pch_i2c_stop(adap);
323 pch_i2c_init(adap);
324 return -ETIMEDOUT;
325 }
326
327 if (adap->pch_event_flag & I2C_ERROR_MASK) {
328 pch_err(adap, "Lost Arbitration\n");
329 adap->pch_event_flag = 0;
330 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
331 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
332 pch_i2c_init(adap);
333 return -EAGAIN;
334 }
335
336 adap->pch_event_flag = 0;
337
338 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
339 pch_dbg(adap, "Receive NACK for slave address setting\n");
340 return -ENXIO;
341 }
342
343 return 0;
344}
345
346
347
348
349
350static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
351{
352 void __iomem *p = adap->pch_base_address;
353 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
354 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
355}
356
357
358
359
360
361
362
363
364
365
366static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
367 struct i2c_msg *msgs, u32 last, u32 first)
368{
369 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
370 u8 *buf;
371 u32 length;
372 u32 addr;
373 u32 addr_2_msb;
374 u32 addr_8_lsb;
375 s32 wrcount;
376 s32 rtn;
377 void __iomem *p = adap->pch_base_address;
378
379 length = msgs->len;
380 buf = msgs->buf;
381 addr = msgs->addr;
382
383
384 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
385
386 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
387 length);
388
389 if (first) {
390 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
391 return -ETIME;
392 }
393
394 if (msgs->flags & I2C_M_TEN) {
395 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
396 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
397 if (first)
398 pch_i2c_start(adap);
399
400 rtn = pch_i2c_wait_for_check_xfer(adap);
401 if (rtn)
402 return rtn;
403
404 addr_8_lsb = (addr & I2C_ADDR_MSK);
405 iowrite32(addr_8_lsb, p + PCH_I2CDR);
406 } else {
407
408 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
409 if (first)
410 pch_i2c_start(adap);
411 }
412
413 rtn = pch_i2c_wait_for_check_xfer(adap);
414 if (rtn)
415 return rtn;
416
417 for (wrcount = 0; wrcount < length; ++wrcount) {
418
419 iowrite32(buf[wrcount], p + PCH_I2CDR);
420 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
421
422 rtn = pch_i2c_wait_for_check_xfer(adap);
423 if (rtn)
424 return rtn;
425
426 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
427 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
428 }
429
430
431 if (last)
432 pch_i2c_stop(adap);
433 else
434 pch_i2c_repstart(adap);
435
436 pch_dbg(adap, "return=%d\n", wrcount);
437
438 return wrcount;
439}
440
441
442
443
444
445static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
446{
447 void __iomem *p = adap->pch_base_address;
448 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
449 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
450}
451
452
453
454
455
456static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
457{
458 void __iomem *p = adap->pch_base_address;
459 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
460 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
461}
462
463
464
465
466
467
468
469static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
470{
471 void __iomem *p = adap->pch_base_address;
472 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
473 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
474}
475
476
477
478
479
480
481
482
483static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
484 u32 last, u32 first)
485{
486 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
487
488 u8 *buf;
489 u32 count;
490 u32 length;
491 u32 addr;
492 u32 addr_2_msb;
493 u32 addr_8_lsb;
494 void __iomem *p = adap->pch_base_address;
495 s32 rtn;
496
497 length = msgs->len;
498 buf = msgs->buf;
499 addr = msgs->addr;
500
501
502 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
503
504 if (first) {
505 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
506 return -ETIME;
507 }
508
509 if (msgs->flags & I2C_M_TEN) {
510 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
511 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
512 if (first)
513 pch_i2c_start(adap);
514
515 rtn = pch_i2c_wait_for_check_xfer(adap);
516 if (rtn)
517 return rtn;
518
519 addr_8_lsb = (addr & I2C_ADDR_MSK);
520 iowrite32(addr_8_lsb, p + PCH_I2CDR);
521
522 pch_i2c_restart(adap);
523
524 rtn = pch_i2c_wait_for_check_xfer(adap);
525 if (rtn)
526 return rtn;
527
528 addr_2_msb |= I2C_RD;
529 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
530 } else {
531
532 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
533 }
534
535
536 if (first)
537 pch_i2c_start(adap);
538
539 rtn = pch_i2c_wait_for_check_xfer(adap);
540 if (rtn)
541 return rtn;
542
543 if (length == 0) {
544 pch_i2c_stop(adap);
545 ioread32(p + PCH_I2CDR);
546
547 count = length;
548 } else {
549 int read_index;
550 int loop;
551 pch_i2c_sendack(adap);
552
553
554 for (loop = 1, read_index = 0; loop < length; loop++) {
555 buf[read_index] = ioread32(p + PCH_I2CDR);
556
557 if (loop != 1)
558 read_index++;
559
560 rtn = pch_i2c_wait_for_check_xfer(adap);
561 if (rtn)
562 return rtn;
563 }
564
565 pch_i2c_sendnack(adap);
566
567 buf[read_index] = ioread32(p + PCH_I2CDR);
568
569 if (length != 1)
570 read_index++;
571
572 rtn = pch_i2c_wait_for_check_xfer(adap);
573 if (rtn)
574 return rtn;
575
576 if (last)
577 pch_i2c_stop(adap);
578 else
579 pch_i2c_repstart(adap);
580
581 buf[read_index++] = ioread32(p + PCH_I2CDR);
582 count = read_index;
583 }
584
585 return count;
586}
587
588
589
590
591
592static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
593{
594 u32 sts;
595 void __iomem *p = adap->pch_base_address;
596
597 sts = ioread32(p + PCH_I2CSR);
598 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
599 if (sts & I2CMAL_BIT)
600 adap->pch_event_flag |= I2CMAL_EVENT;
601
602 if (sts & I2CMCF_BIT)
603 adap->pch_event_flag |= I2CMCF_EVENT;
604
605
606 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
607
608 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
609
610 wake_up(&pch_event);
611}
612
613
614
615
616
617
618static irqreturn_t pch_i2c_handler(int irq, void *pData)
619{
620 u32 reg_val;
621 int flag;
622 int i;
623 struct adapter_info *adap_info = pData;
624 void __iomem *p;
625 u32 mode;
626
627 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
628 p = adap_info->pch_data[i].pch_base_address;
629 mode = ioread32(p + PCH_I2CMOD);
630 mode &= BUFFER_MODE | EEPROM_SR_MODE;
631 if (mode != NORMAL_MODE) {
632 pch_err(adap_info->pch_data,
633 "I2C-%d mode(%d) is not supported\n", mode, i);
634 continue;
635 }
636 reg_val = ioread32(p + PCH_I2CSR);
637 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
638 pch_i2c_cb(&adap_info->pch_data[i]);
639 flag = 1;
640 }
641 }
642
643 return flag ? IRQ_HANDLED : IRQ_NONE;
644}
645
646
647
648
649
650
651
652static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
653 struct i2c_msg *msgs, s32 num)
654{
655 struct i2c_msg *pmsg;
656 u32 i = 0;
657 u32 status;
658 s32 ret;
659
660 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
661
662 ret = mutex_lock_interruptible(&pch_mutex);
663 if (ret)
664 return ret;
665
666 if (adap->p_adapter_info->pch_i2c_suspended) {
667 mutex_unlock(&pch_mutex);
668 return -EBUSY;
669 }
670
671 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
672 adap->p_adapter_info->pch_i2c_suspended);
673
674 adap->pch_i2c_xfer_in_progress = true;
675
676 for (i = 0; i < num && ret >= 0; i++) {
677 pmsg = &msgs[i];
678 pmsg->flags |= adap->pch_buff_mode_en;
679 status = pmsg->flags;
680 pch_dbg(adap,
681 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
682
683 if ((status & (I2C_M_RD)) != false) {
684 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
685 (i == 0));
686 } else {
687 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
688 (i == 0));
689 }
690 }
691
692 adap->pch_i2c_xfer_in_progress = false;
693
694 mutex_unlock(&pch_mutex);
695
696 return (ret < 0) ? ret : num;
697}
698
699
700
701
702
703static u32 pch_i2c_func(struct i2c_adapter *adap)
704{
705 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
706}
707
708static const struct i2c_algorithm pch_algorithm = {
709 .master_xfer = pch_i2c_xfer,
710 .functionality = pch_i2c_func
711};
712
713
714
715
716
717static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
718{
719 void __iomem *p = adap->pch_base_address;
720
721 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
722
723 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
724
725 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
726}
727
728static int pch_i2c_probe(struct pci_dev *pdev,
729 const struct pci_device_id *id)
730{
731 void __iomem *base_addr;
732 int ret;
733 int i, j;
734 struct adapter_info *adap_info;
735 struct i2c_adapter *pch_adap;
736
737 pch_pci_dbg(pdev, "Entered.\n");
738
739 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
740 if (adap_info == NULL)
741 return -ENOMEM;
742
743 ret = pci_enable_device(pdev);
744 if (ret) {
745 pch_pci_err(pdev, "pci_enable_device FAILED\n");
746 goto err_pci_enable;
747 }
748
749 ret = pci_request_regions(pdev, KBUILD_MODNAME);
750 if (ret) {
751 pch_pci_err(pdev, "pci_request_regions FAILED\n");
752 goto err_pci_req;
753 }
754
755 base_addr = pci_iomap(pdev, 1, 0);
756
757 if (base_addr == NULL) {
758 pch_pci_err(pdev, "pci_iomap FAILED\n");
759 ret = -ENOMEM;
760 goto err_pci_iomap;
761 }
762
763
764 adap_info->ch_num = id->driver_data;
765
766 for (i = 0; i < adap_info->ch_num; i++) {
767 pch_adap = &adap_info->pch_data[i].pch_adapter;
768 adap_info->pch_i2c_suspended = false;
769
770 adap_info->pch_data[i].p_adapter_info = adap_info;
771
772 pch_adap->owner = THIS_MODULE;
773 pch_adap->class = I2C_CLASS_HWMON;
774 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
775 pch_adap->algo = &pch_algorithm;
776 pch_adap->algo_data = &adap_info->pch_data[i];
777
778
779 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
780
781 pch_adap->dev.of_node = pdev->dev.of_node;
782 pch_adap->dev.parent = &pdev->dev;
783 }
784
785 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
786 KBUILD_MODNAME, adap_info);
787 if (ret) {
788 pch_pci_err(pdev, "request_irq FAILED\n");
789 goto err_request_irq;
790 }
791
792 for (i = 0; i < adap_info->ch_num; i++) {
793 pch_adap = &adap_info->pch_data[i].pch_adapter;
794
795 pch_i2c_init(&adap_info->pch_data[i]);
796
797 pch_adap->nr = i;
798 ret = i2c_add_numbered_adapter(pch_adap);
799 if (ret) {
800 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
801 goto err_add_adapter;
802 }
803 }
804
805 pci_set_drvdata(pdev, adap_info);
806 pch_pci_dbg(pdev, "returns %d.\n", ret);
807 return 0;
808
809err_add_adapter:
810 for (j = 0; j < i; j++)
811 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
812 free_irq(pdev->irq, adap_info);
813err_request_irq:
814 pci_iounmap(pdev, base_addr);
815err_pci_iomap:
816 pci_release_regions(pdev);
817err_pci_req:
818 pci_disable_device(pdev);
819err_pci_enable:
820 kfree(adap_info);
821 return ret;
822}
823
824static void pch_i2c_remove(struct pci_dev *pdev)
825{
826 int i;
827 struct adapter_info *adap_info = pci_get_drvdata(pdev);
828
829 free_irq(pdev->irq, adap_info);
830
831 for (i = 0; i < adap_info->ch_num; i++) {
832 pch_i2c_disbl_int(&adap_info->pch_data[i]);
833 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
834 }
835
836 if (adap_info->pch_data[0].pch_base_address)
837 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
838
839 for (i = 0; i < adap_info->ch_num; i++)
840 adap_info->pch_data[i].pch_base_address = NULL;
841
842 pci_release_regions(pdev);
843
844 pci_disable_device(pdev);
845 kfree(adap_info);
846}
847
848#ifdef CONFIG_PM
849static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
850{
851 int ret;
852 int i;
853 struct adapter_info *adap_info = pci_get_drvdata(pdev);
854 void __iomem *p = adap_info->pch_data[0].pch_base_address;
855
856 adap_info->pch_i2c_suspended = true;
857
858 for (i = 0; i < adap_info->ch_num; i++) {
859 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
860
861 msleep(20);
862 }
863 }
864
865
866 for (i = 0; i < adap_info->ch_num; i++)
867 pch_i2c_disbl_int(&adap_info->pch_data[i]);
868
869 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
870 "invoked function pch_i2c_disbl_int successfully\n",
871 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
872 ioread32(p + PCH_I2CESRSTA));
873
874 ret = pci_save_state(pdev);
875
876 if (ret) {
877 pch_pci_err(pdev, "pci_save_state\n");
878 return ret;
879 }
880
881 pci_enable_wake(pdev, PCI_D3hot, 0);
882 pci_disable_device(pdev);
883 pci_set_power_state(pdev, pci_choose_state(pdev, state));
884
885 return 0;
886}
887
888static int pch_i2c_resume(struct pci_dev *pdev)
889{
890 int i;
891 struct adapter_info *adap_info = pci_get_drvdata(pdev);
892
893 pci_set_power_state(pdev, PCI_D0);
894 pci_restore_state(pdev);
895
896 if (pci_enable_device(pdev) < 0) {
897 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
898 return -EIO;
899 }
900
901 pci_enable_wake(pdev, PCI_D3hot, 0);
902
903 for (i = 0; i < adap_info->ch_num; i++)
904 pch_i2c_init(&adap_info->pch_data[i]);
905
906 adap_info->pch_i2c_suspended = false;
907
908 return 0;
909}
910#else
911#define pch_i2c_suspend NULL
912#define pch_i2c_resume NULL
913#endif
914
915static struct pci_driver pch_pcidriver = {
916 .name = KBUILD_MODNAME,
917 .id_table = pch_pcidev_id,
918 .probe = pch_i2c_probe,
919 .remove = pch_i2c_remove,
920 .suspend = pch_i2c_suspend,
921 .resume = pch_i2c_resume
922};
923
924module_pci_driver(pch_pcidriver);
925
926MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
927MODULE_LICENSE("GPL");
928MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
929module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
930module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
931