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12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/errno.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/wait.h>
22#include <linux/platform_data/i2c-ocores.h>
23#include <linux/slab.h>
24#include <linux/io.h>
25#include <linux/log2.h>
26#include <linux/spinlock.h>
27#include <linux/jiffies.h>
28
29
30
31
32
33struct ocores_i2c {
34 void __iomem *base;
35 int iobase;
36 u32 reg_shift;
37 u32 reg_io_width;
38 unsigned long flags;
39 wait_queue_head_t wait;
40 struct i2c_adapter adap;
41 struct i2c_msg *msg;
42 int pos;
43 int nmsgs;
44 int state;
45 spinlock_t process_lock;
46 struct clk *clk;
47 int ip_clock_khz;
48 int bus_clock_khz;
49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
50 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
51};
52
53
54#define OCI2C_PRELOW 0
55#define OCI2C_PREHIGH 1
56#define OCI2C_CONTROL 2
57#define OCI2C_DATA 3
58#define OCI2C_CMD 4
59#define OCI2C_STATUS 4
60
61#define OCI2C_CTRL_IEN 0x40
62#define OCI2C_CTRL_EN 0x80
63
64#define OCI2C_CMD_START 0x91
65#define OCI2C_CMD_STOP 0x41
66#define OCI2C_CMD_READ 0x21
67#define OCI2C_CMD_WRITE 0x11
68#define OCI2C_CMD_READ_ACK 0x21
69#define OCI2C_CMD_READ_NACK 0x29
70#define OCI2C_CMD_IACK 0x01
71
72#define OCI2C_STAT_IF 0x01
73#define OCI2C_STAT_TIP 0x02
74#define OCI2C_STAT_ARBLOST 0x20
75#define OCI2C_STAT_BUSY 0x40
76#define OCI2C_STAT_NACK 0x80
77
78#define STATE_DONE 0
79#define STATE_START 1
80#define STATE_WRITE 2
81#define STATE_READ 3
82#define STATE_ERROR 4
83
84#define TYPE_OCORES 0
85#define TYPE_GRLIB 1
86#define TYPE_SIFIVE_REV0 2
87
88#define OCORES_FLAG_BROKEN_IRQ BIT(1)
89
90static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
91{
92 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
93}
94
95static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
96{
97 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
98}
99
100static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
101{
102 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
103}
104
105static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
106{
107 iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
108}
109
110static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
111{
112 iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
113}
114
115static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
116{
117 return ioread8(i2c->base + (reg << i2c->reg_shift));
118}
119
120static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
121{
122 return ioread16(i2c->base + (reg << i2c->reg_shift));
123}
124
125static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
126{
127 return ioread32(i2c->base + (reg << i2c->reg_shift));
128}
129
130static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
131{
132 return ioread16be(i2c->base + (reg << i2c->reg_shift));
133}
134
135static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
136{
137 return ioread32be(i2c->base + (reg << i2c->reg_shift));
138}
139
140static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
141{
142 outb(value, i2c->iobase + reg);
143}
144
145static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
146{
147 return inb(i2c->iobase + reg);
148}
149
150static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
151{
152 i2c->setreg(i2c, reg, value);
153}
154
155static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
156{
157 return i2c->getreg(i2c, reg);
158}
159
160static void ocores_process(struct ocores_i2c *i2c, u8 stat)
161{
162 struct i2c_msg *msg = i2c->msg;
163 unsigned long flags;
164
165
166
167
168
169 spin_lock_irqsave(&i2c->process_lock, flags);
170
171 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
172
173 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
174 wake_up(&i2c->wait);
175 goto out;
176 }
177
178
179 if (stat & OCI2C_STAT_ARBLOST) {
180 i2c->state = STATE_ERROR;
181 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
182 goto out;
183 }
184
185 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
186 i2c->state =
187 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
188
189 if (stat & OCI2C_STAT_NACK) {
190 i2c->state = STATE_ERROR;
191 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
192 goto out;
193 }
194 } else {
195 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
196 }
197
198
199 if (i2c->pos == msg->len) {
200 i2c->nmsgs--;
201 i2c->msg++;
202 i2c->pos = 0;
203 msg = i2c->msg;
204
205 if (i2c->nmsgs) {
206
207 if (!(msg->flags & I2C_M_NOSTART)) {
208 u8 addr = i2c_8bit_addr_from_msg(msg);
209
210 i2c->state = STATE_START;
211
212 oc_setreg(i2c, OCI2C_DATA, addr);
213 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
214 goto out;
215 }
216 i2c->state = (msg->flags & I2C_M_RD)
217 ? STATE_READ : STATE_WRITE;
218 } else {
219 i2c->state = STATE_DONE;
220 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
221 goto out;
222 }
223 }
224
225 if (i2c->state == STATE_READ) {
226 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
227 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
228 } else {
229 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
230 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
231 }
232
233out:
234 spin_unlock_irqrestore(&i2c->process_lock, flags);
235}
236
237static irqreturn_t ocores_isr(int irq, void *dev_id)
238{
239 struct ocores_i2c *i2c = dev_id;
240 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
241
242 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
243 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
244 return IRQ_NONE;
245 } else if (!(stat & OCI2C_STAT_IF)) {
246 return IRQ_NONE;
247 }
248 ocores_process(i2c, stat);
249
250 return IRQ_HANDLED;
251}
252
253
254
255
256
257static void ocores_process_timeout(struct ocores_i2c *i2c)
258{
259 unsigned long flags;
260
261 spin_lock_irqsave(&i2c->process_lock, flags);
262 i2c->state = STATE_ERROR;
263 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
264 spin_unlock_irqrestore(&i2c->process_lock, flags);
265}
266
267
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270
271
272
273
274
275
276
277
278
279
280static int ocores_wait(struct ocores_i2c *i2c,
281 int reg, u8 mask, u8 val,
282 const unsigned long timeout)
283{
284 unsigned long j;
285
286 j = jiffies + timeout;
287 while (1) {
288 u8 status = oc_getreg(i2c, reg);
289
290 if ((status & mask) == val)
291 break;
292
293 if (time_after(jiffies, j))
294 return -ETIMEDOUT;
295 }
296 return 0;
297}
298
299
300
301
302
303
304
305
306
307static int ocores_poll_wait(struct ocores_i2c *i2c)
308{
309 u8 mask;
310 int err;
311
312 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
313
314 mask = OCI2C_STAT_BUSY;
315 } else {
316
317 mask = OCI2C_STAT_TIP;
318
319
320
321
322 udelay((8 * 1000) / i2c->bus_clock_khz);
323 }
324
325
326
327
328
329 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
330 if (err)
331 dev_warn(i2c->adap.dev.parent,
332 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
333 __func__, mask);
334 return err;
335}
336
337
338
339
340
341
342
343
344
345
346
347static void ocores_process_polling(struct ocores_i2c *i2c)
348{
349 while (1) {
350 irqreturn_t ret;
351 int err;
352
353 err = ocores_poll_wait(i2c);
354 if (err) {
355 i2c->state = STATE_ERROR;
356 break;
357 }
358
359 ret = ocores_isr(-1, i2c);
360 if (ret == IRQ_NONE)
361 break;
362 else {
363 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
364 if (i2c->state == STATE_DONE)
365 break;
366 }
367 }
368}
369
370static int ocores_xfer_core(struct ocores_i2c *i2c,
371 struct i2c_msg *msgs, int num,
372 bool polling)
373{
374 int ret;
375 u8 ctrl;
376
377 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
378 if (polling)
379 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
380 else
381 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
382
383 i2c->msg = msgs;
384 i2c->pos = 0;
385 i2c->nmsgs = num;
386 i2c->state = STATE_START;
387
388 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
389 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
390
391 if (polling) {
392 ocores_process_polling(i2c);
393 } else {
394 ret = wait_event_timeout(i2c->wait,
395 (i2c->state == STATE_ERROR) ||
396 (i2c->state == STATE_DONE), HZ);
397 if (ret == 0) {
398 ocores_process_timeout(i2c);
399 return -ETIMEDOUT;
400 }
401 }
402
403 return (i2c->state == STATE_DONE) ? num : -EIO;
404}
405
406static int ocores_xfer_polling(struct i2c_adapter *adap,
407 struct i2c_msg *msgs, int num)
408{
409 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
410}
411
412static int ocores_xfer(struct i2c_adapter *adap,
413 struct i2c_msg *msgs, int num)
414{
415 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
416}
417
418static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
419{
420 int prescale;
421 int diff;
422 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
423
424
425 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
426 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
427
428 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
429 prescale = clamp(prescale, 0, 0xffff);
430
431 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
432 if (abs(diff) > i2c->bus_clock_khz / 10) {
433 dev_err(dev,
434 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
435 i2c->ip_clock_khz, i2c->bus_clock_khz);
436 return -EINVAL;
437 }
438
439 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
440 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
441
442
443 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
444 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
445
446 return 0;
447}
448
449
450static u32 ocores_func(struct i2c_adapter *adap)
451{
452 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
453}
454
455static struct i2c_algorithm ocores_algorithm = {
456 .master_xfer = ocores_xfer,
457 .master_xfer_atomic = ocores_xfer_polling,
458 .functionality = ocores_func,
459};
460
461static const struct i2c_adapter ocores_adapter = {
462 .owner = THIS_MODULE,
463 .name = "i2c-ocores",
464 .class = I2C_CLASS_DEPRECATED,
465 .algo = &ocores_algorithm,
466};
467
468static const struct of_device_id ocores_i2c_match[] = {
469 {
470 .compatible = "opencores,i2c-ocores",
471 .data = (void *)TYPE_OCORES,
472 },
473 {
474 .compatible = "aeroflexgaisler,i2cmst",
475 .data = (void *)TYPE_GRLIB,
476 },
477 {
478 .compatible = "sifive,fu540-c000-i2c",
479 .data = (void *)TYPE_SIFIVE_REV0,
480 },
481 {
482 .compatible = "sifive,i2c0",
483 .data = (void *)TYPE_SIFIVE_REV0,
484 },
485 {},
486};
487MODULE_DEVICE_TABLE(of, ocores_i2c_match);
488
489#ifdef CONFIG_OF
490
491
492
493
494
495static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
496{
497 u32 rd;
498 int rreg = reg;
499
500 if (reg != OCI2C_PRELOW)
501 rreg--;
502 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
503 if (reg == OCI2C_PREHIGH)
504 return (u8)(rd >> 8);
505 else
506 return (u8)rd;
507}
508
509static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
510{
511 u32 curr, wr;
512 int rreg = reg;
513
514 if (reg != OCI2C_PRELOW)
515 rreg--;
516 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
517 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
518 if (reg == OCI2C_PRELOW)
519 wr = (curr & 0xff00) | value;
520 else
521 wr = (((u32)value) << 8) | (curr & 0xff);
522 } else {
523 wr = value;
524 }
525 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
526}
527
528static int ocores_i2c_of_probe(struct platform_device *pdev,
529 struct ocores_i2c *i2c)
530{
531 struct device_node *np = pdev->dev.of_node;
532 const struct of_device_id *match;
533 u32 val;
534 u32 clock_frequency;
535 bool clock_frequency_present;
536
537 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
538
539 if (!of_property_read_u32(np, "regstep", &val)) {
540 if (!is_power_of_2(val)) {
541 dev_err(&pdev->dev, "invalid regstep %d\n",
542 val);
543 return -EINVAL;
544 }
545 i2c->reg_shift = ilog2(val);
546 dev_warn(&pdev->dev,
547 "regstep property deprecated, use reg-shift\n");
548 }
549 }
550
551 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
552 &clock_frequency);
553 i2c->bus_clock_khz = 100;
554
555 i2c->clk = devm_clk_get(&pdev->dev, NULL);
556
557 if (!IS_ERR(i2c->clk)) {
558 int ret = clk_prepare_enable(i2c->clk);
559
560 if (ret) {
561 dev_err(&pdev->dev,
562 "clk_prepare_enable failed: %d\n", ret);
563 return ret;
564 }
565 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
566 if (clock_frequency_present)
567 i2c->bus_clock_khz = clock_frequency / 1000;
568 }
569
570 if (i2c->ip_clock_khz == 0) {
571 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
572 &val)) {
573 if (!clock_frequency_present) {
574 dev_err(&pdev->dev,
575 "Missing required parameter 'opencores,ip-clock-frequency'\n");
576 clk_disable_unprepare(i2c->clk);
577 return -ENODEV;
578 }
579 i2c->ip_clock_khz = clock_frequency / 1000;
580 dev_warn(&pdev->dev,
581 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
582 } else {
583 i2c->ip_clock_khz = val / 1000;
584 if (clock_frequency_present)
585 i2c->bus_clock_khz = clock_frequency / 1000;
586 }
587 }
588
589 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
590 &i2c->reg_io_width);
591
592 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
593 if (match && (long)match->data == TYPE_GRLIB) {
594 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
595 i2c->setreg = oc_setreg_grlib;
596 i2c->getreg = oc_getreg_grlib;
597 }
598
599 return 0;
600}
601#else
602#define ocores_i2c_of_probe(pdev, i2c) -ENODEV
603#endif
604
605static int ocores_i2c_probe(struct platform_device *pdev)
606{
607 struct ocores_i2c *i2c;
608 struct ocores_i2c_platform_data *pdata;
609 const struct of_device_id *match;
610 struct resource *res;
611 int irq;
612 int ret;
613 int i;
614
615 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
616 if (!i2c)
617 return -ENOMEM;
618
619 spin_lock_init(&i2c->process_lock);
620
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
622 if (res) {
623 i2c->base = devm_ioremap_resource(&pdev->dev, res);
624 if (IS_ERR(i2c->base))
625 return PTR_ERR(i2c->base);
626 } else {
627 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
628 if (!res)
629 return -EINVAL;
630 i2c->iobase = res->start;
631 if (!devm_request_region(&pdev->dev, res->start,
632 resource_size(res),
633 pdev->name)) {
634 dev_err(&pdev->dev, "Can't get I/O resource.\n");
635 return -EBUSY;
636 }
637 i2c->setreg = oc_setreg_io_8;
638 i2c->getreg = oc_getreg_io_8;
639 }
640
641 pdata = dev_get_platdata(&pdev->dev);
642 if (pdata) {
643 i2c->reg_shift = pdata->reg_shift;
644 i2c->reg_io_width = pdata->reg_io_width;
645 i2c->ip_clock_khz = pdata->clock_khz;
646 if (pdata->bus_khz)
647 i2c->bus_clock_khz = pdata->bus_khz;
648 else
649 i2c->bus_clock_khz = 100;
650 } else {
651 ret = ocores_i2c_of_probe(pdev, i2c);
652 if (ret)
653 return ret;
654 }
655
656 if (i2c->reg_io_width == 0)
657 i2c->reg_io_width = 1;
658
659 if (!i2c->setreg || !i2c->getreg) {
660 bool be = pdata ? pdata->big_endian :
661 of_device_is_big_endian(pdev->dev.of_node);
662
663 switch (i2c->reg_io_width) {
664 case 1:
665 i2c->setreg = oc_setreg_8;
666 i2c->getreg = oc_getreg_8;
667 break;
668
669 case 2:
670 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
671 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
672 break;
673
674 case 4:
675 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
676 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
677 break;
678
679 default:
680 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
681 i2c->reg_io_width);
682 ret = -EINVAL;
683 goto err_clk;
684 }
685 }
686
687 init_waitqueue_head(&i2c->wait);
688
689 irq = platform_get_irq(pdev, 0);
690 if (irq == -ENXIO) {
691 ocores_algorithm.master_xfer = ocores_xfer_polling;
692
693
694
695
696
697 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
698 if (match && (long)match->data == TYPE_SIFIVE_REV0)
699 i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
700 } else {
701 if (irq < 0)
702 return irq;
703 }
704
705 if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
706 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
707 pdev->name, i2c);
708 if (ret) {
709 dev_err(&pdev->dev, "Cannot claim IRQ\n");
710 goto err_clk;
711 }
712 }
713
714 ret = ocores_init(&pdev->dev, i2c);
715 if (ret)
716 goto err_clk;
717
718
719 platform_set_drvdata(pdev, i2c);
720 i2c->adap = ocores_adapter;
721 i2c_set_adapdata(&i2c->adap, i2c);
722 i2c->adap.dev.parent = &pdev->dev;
723 i2c->adap.dev.of_node = pdev->dev.of_node;
724
725
726 ret = i2c_add_adapter(&i2c->adap);
727 if (ret)
728 goto err_clk;
729
730
731 if (pdata) {
732 for (i = 0; i < pdata->num_devices; i++)
733 i2c_new_device(&i2c->adap, pdata->devices + i);
734 }
735
736 return 0;
737
738err_clk:
739 clk_disable_unprepare(i2c->clk);
740 return ret;
741}
742
743static int ocores_i2c_remove(struct platform_device *pdev)
744{
745 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
746 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
747
748
749 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
750 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
751
752
753 i2c_del_adapter(&i2c->adap);
754
755 if (!IS_ERR(i2c->clk))
756 clk_disable_unprepare(i2c->clk);
757
758 return 0;
759}
760
761#ifdef CONFIG_PM_SLEEP
762static int ocores_i2c_suspend(struct device *dev)
763{
764 struct ocores_i2c *i2c = dev_get_drvdata(dev);
765 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
766
767
768 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
769 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
770
771 if (!IS_ERR(i2c->clk))
772 clk_disable_unprepare(i2c->clk);
773 return 0;
774}
775
776static int ocores_i2c_resume(struct device *dev)
777{
778 struct ocores_i2c *i2c = dev_get_drvdata(dev);
779
780 if (!IS_ERR(i2c->clk)) {
781 unsigned long rate;
782 int ret = clk_prepare_enable(i2c->clk);
783
784 if (ret) {
785 dev_err(dev,
786 "clk_prepare_enable failed: %d\n", ret);
787 return ret;
788 }
789 rate = clk_get_rate(i2c->clk) / 1000;
790 if (rate)
791 i2c->ip_clock_khz = rate;
792 }
793 return ocores_init(dev, i2c);
794}
795
796static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
797#define OCORES_I2C_PM (&ocores_i2c_pm)
798#else
799#define OCORES_I2C_PM NULL
800#endif
801
802static struct platform_driver ocores_i2c_driver = {
803 .probe = ocores_i2c_probe,
804 .remove = ocores_i2c_remove,
805 .driver = {
806 .name = "ocores-i2c",
807 .of_match_table = ocores_i2c_match,
808 .pm = OCORES_I2C_PM,
809 },
810};
811
812module_platform_driver(ocores_i2c_driver);
813
814MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
815MODULE_DESCRIPTION("OpenCores I2C bus driver");
816MODULE_LICENSE("GPL");
817MODULE_ALIAS("platform:ocores-i2c");
818
