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24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/stddef.h>
30#include <linux/ioport.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/dmi.h>
34#include <linux/acpi.h>
35#include <linux/io.h>
36
37
38
39#define SMBHSTSTS (0 + piix4_smba)
40#define SMBHSLVSTS (1 + piix4_smba)
41#define SMBHSTCNT (2 + piix4_smba)
42#define SMBHSTCMD (3 + piix4_smba)
43#define SMBHSTADD (4 + piix4_smba)
44#define SMBHSTDAT0 (5 + piix4_smba)
45#define SMBHSTDAT1 (6 + piix4_smba)
46#define SMBBLKDAT (7 + piix4_smba)
47#define SMBSLVCNT (8 + piix4_smba)
48#define SMBSHDWCMD (9 + piix4_smba)
49#define SMBSLVEVT (0xA + piix4_smba)
50#define SMBSLVDAT (0xC + piix4_smba)
51
52
53#define SMBIOSIZE 9
54
55
56#define SMBBA 0x090
57#define SMBHSTCFG 0x0D2
58#define SMBSLVC 0x0D3
59#define SMBSHDW1 0x0D4
60#define SMBSHDW2 0x0D5
61#define SMBREV 0x0D6
62
63
64#define MAX_TIMEOUT 500
65#define ENABLE_INT9 0
66
67
68#define PIIX4_QUICK 0x00
69#define PIIX4_BYTE 0x04
70#define PIIX4_BYTE_DATA 0x08
71#define PIIX4_WORD_DATA 0x0C
72#define PIIX4_BLOCK_DATA 0x14
73
74
75#define PIIX4_MAX_ADAPTERS 4
76
77
78#define SB800_PIIX4_SMB_IDX 0xcd6
79
80#define KERNCZ_IMC_IDX 0x3e
81#define KERNCZ_IMC_DATA 0x3f
82
83
84
85
86
87
88#define SB800_PIIX4_PORT_IDX 0x2c
89#define SB800_PIIX4_PORT_IDX_ALT 0x2e
90#define SB800_PIIX4_PORT_IDX_SEL 0x2f
91#define SB800_PIIX4_PORT_IDX_MASK 0x06
92#define SB800_PIIX4_PORT_IDX_SHIFT 1
93
94
95#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
96#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
97#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
98
99
100
101
102
103static int force;
104module_param (force, int, 0);
105MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
106
107
108
109static int force_addr;
110module_param_hw(force_addr, int, ioport, 0);
111MODULE_PARM_DESC(force_addr,
112 "Forcibly enable the PIIX4 at the given address. "
113 "EXTREMELY DANGEROUS!");
114
115static int srvrworks_csb5_delay;
116static struct pci_driver piix4_driver;
117
118static const struct dmi_system_id piix4_dmi_blacklist[] = {
119 {
120 .ident = "Sapphire AM2RD790",
121 .matches = {
122 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
123 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
124 },
125 },
126 {
127 .ident = "DFI Lanparty UT 790FX",
128 .matches = {
129 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
130 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
131 },
132 },
133 { }
134};
135
136
137
138static const struct dmi_system_id piix4_dmi_ibm[] = {
139 {
140 .ident = "IBM",
141 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
142 },
143 { },
144};
145
146
147
148
149static u8 piix4_port_sel_sb800;
150static u8 piix4_port_mask_sb800;
151static u8 piix4_port_shift_sb800;
152static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
153 " port 0", " port 2", " port 3", " port 4"
154};
155static const char *piix4_aux_port_name_sb800 = " port 1";
156
157struct i2c_piix4_adapdata {
158 unsigned short smba;
159
160
161 bool sb800_main;
162 bool notify_imc;
163 u8 port;
164};
165
166static int piix4_setup(struct pci_dev *PIIX4_dev,
167 const struct pci_device_id *id)
168{
169 unsigned char temp;
170 unsigned short piix4_smba;
171
172 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
173 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
174 srvrworks_csb5_delay = 1;
175
176
177
178 if (dmi_check_system(piix4_dmi_blacklist)) {
179 dev_err(&PIIX4_dev->dev,
180 "Accessing the SMBus on this system is unsafe!\n");
181 return -EPERM;
182 }
183
184
185 if (dmi_check_system(piix4_dmi_ibm) &&
186 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
187 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
188 "may corrupt your serial eeprom! Refusing to load "
189 "module!\n");
190 return -EPERM;
191 }
192
193
194 if (force_addr) {
195 piix4_smba = force_addr & 0xfff0;
196 force = 0;
197 } else {
198 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
199 piix4_smba &= 0xfff0;
200 if(piix4_smba == 0) {
201 dev_err(&PIIX4_dev->dev, "SMBus base address "
202 "uninitialized - upgrade BIOS or use "
203 "force_addr=0xaddr\n");
204 return -ENODEV;
205 }
206 }
207
208 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
209 return -ENODEV;
210
211 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
212 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
213 piix4_smba);
214 return -EBUSY;
215 }
216
217 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
218
219
220
221 if (force_addr) {
222 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
223 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
224 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
225 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
226 "new address %04x!\n", piix4_smba);
227 } else if ((temp & 1) == 0) {
228 if (force) {
229
230
231
232
233
234
235
236
237 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
238 temp | 1);
239 dev_notice(&PIIX4_dev->dev,
240 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
241 } else {
242 dev_err(&PIIX4_dev->dev,
243 "SMBus Host Controller not enabled!\n");
244 release_region(piix4_smba, SMBIOSIZE);
245 return -ENODEV;
246 }
247 }
248
249 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
250 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
251 else if ((temp & 0x0E) == 0)
252 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
253 else
254 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
255 "(or code out of date)!\n");
256
257 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
258 dev_info(&PIIX4_dev->dev,
259 "SMBus Host Controller at 0x%x, revision %d\n",
260 piix4_smba, temp);
261
262 return piix4_smba;
263}
264
265static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
266 const struct pci_device_id *id, u8 aux)
267{
268 unsigned short piix4_smba;
269 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
270 u8 i2ccfg, i2ccfg_offset = 0x10;
271
272
273 if (force || force_addr) {
274 dev_err(&PIIX4_dev->dev, "SMBus does not support "
275 "forcing address!\n");
276 return -EINVAL;
277 }
278
279
280 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
281 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
282 PIIX4_dev->revision >= 0x41) ||
283 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
284 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
285 PIIX4_dev->revision >= 0x49) ||
286 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
287 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
288 smb_en = 0x00;
289 else
290 smb_en = (aux) ? 0x28 : 0x2c;
291
292 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) {
293 dev_err(&PIIX4_dev->dev,
294 "SMB base address index region 0x%x already in use.\n",
295 SB800_PIIX4_SMB_IDX);
296 return -EBUSY;
297 }
298
299 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
300 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
301 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
302 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
303
304 release_region(SB800_PIIX4_SMB_IDX, 2);
305
306 if (!smb_en) {
307 smb_en_status = smba_en_lo & 0x10;
308 piix4_smba = smba_en_hi << 8;
309 if (aux)
310 piix4_smba |= 0x20;
311 } else {
312 smb_en_status = smba_en_lo & 0x01;
313 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
314 }
315
316 if (!smb_en_status) {
317 dev_err(&PIIX4_dev->dev,
318 "SMBus Host Controller not enabled!\n");
319 return -ENODEV;
320 }
321
322 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
323 return -ENODEV;
324
325 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
326 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
327 piix4_smba);
328 return -EBUSY;
329 }
330
331
332 if (aux) {
333 dev_info(&PIIX4_dev->dev,
334 "Auxiliary SMBus Host Controller at 0x%x\n",
335 piix4_smba);
336 return piix4_smba;
337 }
338
339
340 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
341 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
342 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
343 release_region(piix4_smba, SMBIOSIZE);
344 return -EBUSY;
345 }
346 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
347 release_region(piix4_smba + i2ccfg_offset, 1);
348
349 if (i2ccfg & 1)
350 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
351 else
352 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
353
354 dev_info(&PIIX4_dev->dev,
355 "SMBus Host Controller at 0x%x, revision %d\n",
356 piix4_smba, i2ccfg >> 4);
357
358
359 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
360 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
361 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
362 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
363 PIIX4_dev->revision >= 0x1F)) {
364 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
365 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
366 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
367 } else {
368 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
369 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
370 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
371 }
372 } else {
373 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
374 "sb800_piix4_smb")) {
375 release_region(piix4_smba, SMBIOSIZE);
376 return -EBUSY;
377 }
378
379 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
380 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
381 piix4_port_sel_sb800 = (port_sel & 0x01) ?
382 SB800_PIIX4_PORT_IDX_ALT :
383 SB800_PIIX4_PORT_IDX;
384 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
385 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
386 release_region(SB800_PIIX4_SMB_IDX, 2);
387 }
388
389 dev_info(&PIIX4_dev->dev,
390 "Using register 0x%02x for SMBus port selection\n",
391 (unsigned int)piix4_port_sel_sb800);
392
393 return piix4_smba;
394}
395
396static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
397 const struct pci_device_id *id,
398 unsigned short base_reg_addr)
399{
400
401
402
403 unsigned short piix4_smba;
404
405
406 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
407 if ((piix4_smba & 1) == 0) {
408 dev_dbg(&PIIX4_dev->dev,
409 "Auxiliary SMBus controller not enabled\n");
410 return -ENODEV;
411 }
412
413 piix4_smba &= 0xfff0;
414 if (piix4_smba == 0) {
415 dev_dbg(&PIIX4_dev->dev,
416 "Auxiliary SMBus base address uninitialized\n");
417 return -ENODEV;
418 }
419
420 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
421 return -ENODEV;
422
423 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
424 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
425 "already in use!\n", piix4_smba);
426 return -EBUSY;
427 }
428
429 dev_info(&PIIX4_dev->dev,
430 "Auxiliary SMBus Host Controller at 0x%x\n",
431 piix4_smba);
432
433 return piix4_smba;
434}
435
436static int piix4_transaction(struct i2c_adapter *piix4_adapter)
437{
438 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
439 unsigned short piix4_smba = adapdata->smba;
440 int temp;
441 int result = 0;
442 int timeout = 0;
443
444 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
445 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
446 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
447 inb_p(SMBHSTDAT1));
448
449
450 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
451 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
452 "Resetting...\n", temp);
453 outb_p(temp, SMBHSTSTS);
454 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
455 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
456 return -EBUSY;
457 } else {
458 dev_dbg(&piix4_adapter->dev, "Successful!\n");
459 }
460 }
461
462
463 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
464
465
466 if (srvrworks_csb5_delay)
467 usleep_range(2000, 2100);
468 else
469 usleep_range(250, 500);
470
471 while ((++timeout < MAX_TIMEOUT) &&
472 ((temp = inb_p(SMBHSTSTS)) & 0x01))
473 usleep_range(250, 500);
474
475
476 if (timeout == MAX_TIMEOUT) {
477 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
478 result = -ETIMEDOUT;
479 }
480
481 if (temp & 0x10) {
482 result = -EIO;
483 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
484 }
485
486 if (temp & 0x08) {
487 result = -EIO;
488 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
489 "locked until next hard reset. (sorry!)\n");
490
491 }
492
493 if (temp & 0x04) {
494 result = -ENXIO;
495 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
496 }
497
498 if (inb_p(SMBHSTSTS) != 0x00)
499 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
500
501 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
502 dev_err(&piix4_adapter->dev, "Failed reset at end of "
503 "transaction (%02x)\n", temp);
504 }
505 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
506 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
507 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
508 inb_p(SMBHSTDAT1));
509 return result;
510}
511
512
513static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
514 unsigned short flags, char read_write,
515 u8 command, int size, union i2c_smbus_data * data)
516{
517 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
518 unsigned short piix4_smba = adapdata->smba;
519 int i, len;
520 int status;
521
522 switch (size) {
523 case I2C_SMBUS_QUICK:
524 outb_p((addr << 1) | read_write,
525 SMBHSTADD);
526 size = PIIX4_QUICK;
527 break;
528 case I2C_SMBUS_BYTE:
529 outb_p((addr << 1) | read_write,
530 SMBHSTADD);
531 if (read_write == I2C_SMBUS_WRITE)
532 outb_p(command, SMBHSTCMD);
533 size = PIIX4_BYTE;
534 break;
535 case I2C_SMBUS_BYTE_DATA:
536 outb_p((addr << 1) | read_write,
537 SMBHSTADD);
538 outb_p(command, SMBHSTCMD);
539 if (read_write == I2C_SMBUS_WRITE)
540 outb_p(data->byte, SMBHSTDAT0);
541 size = PIIX4_BYTE_DATA;
542 break;
543 case I2C_SMBUS_WORD_DATA:
544 outb_p((addr << 1) | read_write,
545 SMBHSTADD);
546 outb_p(command, SMBHSTCMD);
547 if (read_write == I2C_SMBUS_WRITE) {
548 outb_p(data->word & 0xff, SMBHSTDAT0);
549 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
550 }
551 size = PIIX4_WORD_DATA;
552 break;
553 case I2C_SMBUS_BLOCK_DATA:
554 outb_p((addr << 1) | read_write,
555 SMBHSTADD);
556 outb_p(command, SMBHSTCMD);
557 if (read_write == I2C_SMBUS_WRITE) {
558 len = data->block[0];
559 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
560 return -EINVAL;
561 outb_p(len, SMBHSTDAT0);
562 inb_p(SMBHSTCNT);
563 for (i = 1; i <= len; i++)
564 outb_p(data->block[i], SMBBLKDAT);
565 }
566 size = PIIX4_BLOCK_DATA;
567 break;
568 default:
569 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
570 return -EOPNOTSUPP;
571 }
572
573 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
574
575 status = piix4_transaction(adap);
576 if (status)
577 return status;
578
579 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
580 return 0;
581
582
583 switch (size) {
584 case PIIX4_BYTE:
585 case PIIX4_BYTE_DATA:
586 data->byte = inb_p(SMBHSTDAT0);
587 break;
588 case PIIX4_WORD_DATA:
589 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
590 break;
591 case PIIX4_BLOCK_DATA:
592 data->block[0] = inb_p(SMBHSTDAT0);
593 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
594 return -EPROTO;
595 inb_p(SMBHSTCNT);
596 for (i = 1; i <= data->block[0]; i++)
597 data->block[i] = inb_p(SMBBLKDAT);
598 break;
599 }
600 return 0;
601}
602
603static uint8_t piix4_imc_read(uint8_t idx)
604{
605 outb_p(idx, KERNCZ_IMC_IDX);
606 return inb_p(KERNCZ_IMC_DATA);
607}
608
609static void piix4_imc_write(uint8_t idx, uint8_t value)
610{
611 outb_p(idx, KERNCZ_IMC_IDX);
612 outb_p(value, KERNCZ_IMC_DATA);
613}
614
615static int piix4_imc_sleep(void)
616{
617 int timeout = MAX_TIMEOUT;
618
619 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
620 return -EBUSY;
621
622
623 piix4_imc_write(0x82, 0x00);
624
625 piix4_imc_write(0x83, 0xB4);
626
627 piix4_imc_write(0x80, 0x96);
628
629 while (timeout--) {
630 if (piix4_imc_read(0x82) == 0xfa) {
631 release_region(KERNCZ_IMC_IDX, 2);
632 return 0;
633 }
634 usleep_range(1000, 2000);
635 }
636
637 release_region(KERNCZ_IMC_IDX, 2);
638 return -ETIMEDOUT;
639}
640
641static void piix4_imc_wakeup(void)
642{
643 int timeout = MAX_TIMEOUT;
644
645 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
646 return;
647
648
649 piix4_imc_write(0x82, 0x00);
650
651 piix4_imc_write(0x83, 0xB5);
652
653 piix4_imc_write(0x80, 0x96);
654
655 while (timeout--) {
656 if (piix4_imc_read(0x82) == 0xfa)
657 break;
658 usleep_range(1000, 2000);
659 }
660
661 release_region(KERNCZ_IMC_IDX, 2);
662}
663
664
665
666
667
668
669
670
671
672static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
673 unsigned short flags, char read_write,
674 u8 command, int size, union i2c_smbus_data *data)
675{
676 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
677 unsigned short piix4_smba = adapdata->smba;
678 int retries = MAX_TIMEOUT;
679 int smbslvcnt;
680 u8 smba_en_lo;
681 u8 port;
682 int retval;
683
684 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb"))
685 return -EBUSY;
686
687
688 smbslvcnt = inb_p(SMBSLVCNT);
689 do {
690 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
691
692
693 smbslvcnt = inb_p(SMBSLVCNT);
694 if (smbslvcnt & 0x10)
695 break;
696
697 usleep_range(1000, 2000);
698 } while (--retries);
699
700 if (!retries) {
701 retval = -EBUSY;
702 goto release;
703 }
704
705
706
707
708
709
710
711
712
713
714 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
715 int ret;
716
717 ret = piix4_imc_sleep();
718 switch (ret) {
719 case -EBUSY:
720 dev_warn(&adap->dev,
721 "IMC base address index region 0x%x already in use.\n",
722 KERNCZ_IMC_IDX);
723 break;
724 case -ETIMEDOUT:
725 dev_warn(&adap->dev,
726 "Failed to communicate with the IMC.\n");
727 break;
728 default:
729 break;
730 }
731
732
733 if (ret) {
734 dev_warn(&adap->dev,
735 "Continuing without IMC notification.\n");
736 adapdata->notify_imc = false;
737 }
738 }
739
740 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
741 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
742
743 port = adapdata->port;
744 if ((smba_en_lo & piix4_port_mask_sb800) != port)
745 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
746 SB800_PIIX4_SMB_IDX + 1);
747
748 retval = piix4_access(adap, addr, flags, read_write,
749 command, size, data);
750
751 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
752
753
754 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
755
756 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
757 piix4_imc_wakeup();
758
759release:
760 release_region(SB800_PIIX4_SMB_IDX, 2);
761 return retval;
762}
763
764static u32 piix4_func(struct i2c_adapter *adapter)
765{
766 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
767 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
768 I2C_FUNC_SMBUS_BLOCK_DATA;
769}
770
771static const struct i2c_algorithm smbus_algorithm = {
772 .smbus_xfer = piix4_access,
773 .functionality = piix4_func,
774};
775
776static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
777 .smbus_xfer = piix4_access_sb800,
778 .functionality = piix4_func,
779};
780
781static const struct pci_device_id piix4_ids[] = {
782 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
783 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
784 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
785 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
786 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
789 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
791 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
792 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
793 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
794 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
795 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
796 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
797 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
798 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
799 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
800 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
801 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
802 { 0, }
803};
804
805MODULE_DEVICE_TABLE (pci, piix4_ids);
806
807static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
808static struct i2c_adapter *piix4_aux_adapter;
809
810static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
811 bool sb800_main, u8 port, bool notify_imc,
812 const char *name, struct i2c_adapter **padap)
813{
814 struct i2c_adapter *adap;
815 struct i2c_piix4_adapdata *adapdata;
816 int retval;
817
818 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
819 if (adap == NULL) {
820 release_region(smba, SMBIOSIZE);
821 return -ENOMEM;
822 }
823
824 adap->owner = THIS_MODULE;
825 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
826 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
827 : &smbus_algorithm;
828
829 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
830 if (adapdata == NULL) {
831 kfree(adap);
832 release_region(smba, SMBIOSIZE);
833 return -ENOMEM;
834 }
835
836 adapdata->smba = smba;
837 adapdata->sb800_main = sb800_main;
838 adapdata->port = port << piix4_port_shift_sb800;
839 adapdata->notify_imc = notify_imc;
840
841
842 adap->dev.parent = &dev->dev;
843
844 snprintf(adap->name, sizeof(adap->name),
845 "SMBus PIIX4 adapter%s at %04x", name, smba);
846
847 i2c_set_adapdata(adap, adapdata);
848
849 retval = i2c_add_adapter(adap);
850 if (retval) {
851 kfree(adapdata);
852 kfree(adap);
853 release_region(smba, SMBIOSIZE);
854 return retval;
855 }
856
857 *padap = adap;
858 return 0;
859}
860
861static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
862 bool notify_imc)
863{
864 struct i2c_piix4_adapdata *adapdata;
865 int port;
866 int retval;
867
868 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) {
869 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
870 piix4_main_port_names_sb800[port],
871 &piix4_main_adapters[port]);
872 if (retval < 0)
873 goto error;
874 }
875
876 return retval;
877
878error:
879 dev_err(&dev->dev,
880 "Error setting up SB800 adapters. Unregistering!\n");
881 while (--port >= 0) {
882 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
883 if (adapdata->smba) {
884 i2c_del_adapter(piix4_main_adapters[port]);
885 kfree(adapdata);
886 kfree(piix4_main_adapters[port]);
887 piix4_main_adapters[port] = NULL;
888 }
889 }
890
891 return retval;
892}
893
894static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
895{
896 int retval;
897 bool is_sb800 = false;
898
899 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
900 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
901 dev->revision >= 0x40) ||
902 dev->vendor == PCI_VENDOR_ID_AMD ||
903 dev->vendor == PCI_VENDOR_ID_HYGON) {
904 bool notify_imc = false;
905 is_sb800 = true;
906
907 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
908 dev->vendor == PCI_VENDOR_ID_HYGON) &&
909 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
910 u8 imc;
911
912
913
914
915
916 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
917 0x40, &imc);
918 if (imc & 0x80)
919 notify_imc = true;
920 }
921
922
923 retval = piix4_setup_sb800(dev, id, 0);
924 if (retval < 0)
925 return retval;
926
927
928
929
930
931 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
932 if (retval < 0)
933 return retval;
934 } else {
935 retval = piix4_setup(dev, id);
936 if (retval < 0)
937 return retval;
938
939
940 retval = piix4_add_adapter(dev, retval, false, 0, false, "",
941 &piix4_main_adapters[0]);
942 if (retval < 0)
943 return retval;
944 }
945
946
947 retval = -ENODEV;
948
949 if (dev->vendor == PCI_VENDOR_ID_ATI &&
950 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
951 if (dev->revision < 0x40) {
952 retval = piix4_setup_aux(dev, id, 0x58);
953 } else {
954
955 retval = piix4_setup_sb800(dev, id, 1);
956 }
957 }
958
959 if (dev->vendor == PCI_VENDOR_ID_AMD &&
960 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
961 retval = piix4_setup_sb800(dev, id, 1);
962 }
963
964 if (retval > 0) {
965
966
967 piix4_add_adapter(dev, retval, false, 0, false,
968 is_sb800 ? piix4_aux_port_name_sb800 : "",
969 &piix4_aux_adapter);
970 }
971
972 return 0;
973}
974
975static void piix4_adap_remove(struct i2c_adapter *adap)
976{
977 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
978
979 if (adapdata->smba) {
980 i2c_del_adapter(adap);
981 if (adapdata->port == (0 << piix4_port_shift_sb800))
982 release_region(adapdata->smba, SMBIOSIZE);
983 kfree(adapdata);
984 kfree(adap);
985 }
986}
987
988static void piix4_remove(struct pci_dev *dev)
989{
990 int port = PIIX4_MAX_ADAPTERS;
991
992 while (--port >= 0) {
993 if (piix4_main_adapters[port]) {
994 piix4_adap_remove(piix4_main_adapters[port]);
995 piix4_main_adapters[port] = NULL;
996 }
997 }
998
999 if (piix4_aux_adapter) {
1000 piix4_adap_remove(piix4_aux_adapter);
1001 piix4_aux_adapter = NULL;
1002 }
1003}
1004
1005static struct pci_driver piix4_driver = {
1006 .name = "piix4_smbus",
1007 .id_table = piix4_ids,
1008 .probe = piix4_probe,
1009 .remove = piix4_remove,
1010};
1011
1012module_pci_driver(piix4_driver);
1013
1014MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
1015 "Philip Edelbrock <phil@netroedge.com>");
1016MODULE_DESCRIPTION("PIIX4 SMBus driver");
1017MODULE_LICENSE("GPL");
1018
