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19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/i2c.h>
22#include <linux/init.h>
23#include <linux/time.h>
24#include <linux/sched.h>
25#include <linux/delay.h>
26#include <linux/errno.h>
27#include <linux/interrupt.h>
28#include <linux/i2c-pxa.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/platform_device.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/slab.h>
35#include <linux/io.h>
36#include <linux/platform_data/i2c-pxa.h>
37
38#include <asm/irq.h>
39
40struct pxa_reg_layout {
41 u32 ibmr;
42 u32 idbr;
43 u32 icr;
44 u32 isr;
45 u32 isar;
46 u32 ilcr;
47 u32 iwcr;
48 u32 fm;
49 u32 hs;
50};
51
52enum pxa_i2c_types {
53 REGS_PXA2XX,
54 REGS_PXA3XX,
55 REGS_CE4100,
56 REGS_PXA910,
57 REGS_A3700,
58};
59
60#define ICR_BUSMODE_FM (1 << 16)
61#define ICR_BUSMODE_HS (1 << 17)
62
63
64
65
66static struct pxa_reg_layout pxa_reg_layout[] = {
67 [REGS_PXA2XX] = {
68 .ibmr = 0x00,
69 .idbr = 0x08,
70 .icr = 0x10,
71 .isr = 0x18,
72 .isar = 0x20,
73 },
74 [REGS_PXA3XX] = {
75 .ibmr = 0x00,
76 .idbr = 0x04,
77 .icr = 0x08,
78 .isr = 0x0c,
79 .isar = 0x10,
80 },
81 [REGS_CE4100] = {
82 .ibmr = 0x14,
83 .idbr = 0x0c,
84 .icr = 0x00,
85 .isr = 0x04,
86
87 },
88 [REGS_PXA910] = {
89 .ibmr = 0x00,
90 .idbr = 0x08,
91 .icr = 0x10,
92 .isr = 0x18,
93 .isar = 0x20,
94 .ilcr = 0x28,
95 .iwcr = 0x30,
96 },
97 [REGS_A3700] = {
98 .ibmr = 0x00,
99 .idbr = 0x04,
100 .icr = 0x08,
101 .isr = 0x0c,
102 .isar = 0x10,
103 .fm = ICR_BUSMODE_FM,
104 .hs = ICR_BUSMODE_HS,
105 },
106};
107
108static const struct platform_device_id i2c_pxa_id_table[] = {
109 { "pxa2xx-i2c", REGS_PXA2XX },
110 { "pxa3xx-pwri2c", REGS_PXA3XX },
111 { "ce4100-i2c", REGS_CE4100 },
112 { "pxa910-i2c", REGS_PXA910 },
113 { "armada-3700-i2c", REGS_A3700 },
114 { },
115};
116MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
117
118
119
120
121
122#define ICR_START (1 << 0)
123#define ICR_STOP (1 << 1)
124#define ICR_ACKNAK (1 << 2)
125#define ICR_TB (1 << 3)
126#define ICR_MA (1 << 4)
127#define ICR_SCLE (1 << 5)
128#define ICR_IUE (1 << 6)
129#define ICR_GCD (1 << 7)
130#define ICR_ITEIE (1 << 8)
131#define ICR_IRFIE (1 << 9)
132#define ICR_BEIE (1 << 10)
133#define ICR_SSDIE (1 << 11)
134#define ICR_ALDIE (1 << 12)
135#define ICR_SADIE (1 << 13)
136#define ICR_UR (1 << 14)
137#define ICR_FM (1 << 15)
138#define ICR_HS (1 << 16)
139#define ICR_GPIOEN (1 << 19)
140
141#define ISR_RWM (1 << 0)
142#define ISR_ACKNAK (1 << 1)
143#define ISR_UB (1 << 2)
144#define ISR_IBB (1 << 3)
145#define ISR_SSD (1 << 4)
146#define ISR_ALD (1 << 5)
147#define ISR_ITE (1 << 6)
148#define ISR_IRF (1 << 7)
149#define ISR_GCAD (1 << 8)
150#define ISR_SAD (1 << 9)
151#define ISR_BED (1 << 10)
152
153
154#define ILCR_SLV_SHIFT 0
155#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
156#define ILCR_FLV_SHIFT 9
157#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
158#define ILCR_HLVL_SHIFT 18
159#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
160#define ILCR_HLVH_SHIFT 27
161#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
162
163#define IWCR_CNT_SHIFT 0
164#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
165#define IWCR_HS_CNT1_SHIFT 5
166#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
167#define IWCR_HS_CNT2_SHIFT 10
168#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
169
170struct pxa_i2c {
171 spinlock_t lock;
172 wait_queue_head_t wait;
173 struct i2c_msg *msg;
174 unsigned int msg_num;
175 unsigned int msg_idx;
176 unsigned int msg_ptr;
177 unsigned int slave_addr;
178 unsigned int req_slave_addr;
179
180 struct i2c_adapter adap;
181 struct clk *clk;
182#ifdef CONFIG_I2C_PXA_SLAVE
183 struct i2c_slave_client *slave;
184#endif
185
186 unsigned int irqlogidx;
187 u32 isrlog[32];
188 u32 icrlog[32];
189
190 void __iomem *reg_base;
191 void __iomem *reg_ibmr;
192 void __iomem *reg_idbr;
193 void __iomem *reg_icr;
194 void __iomem *reg_isr;
195 void __iomem *reg_isar;
196 void __iomem *reg_ilcr;
197 void __iomem *reg_iwcr;
198
199 unsigned long iobase;
200 unsigned long iosize;
201
202 int irq;
203 unsigned int use_pio :1;
204 unsigned int fast_mode :1;
205 unsigned int high_mode:1;
206 unsigned char master_code;
207 unsigned long rate;
208 bool highmode_enter;
209 u32 fm_mask;
210 u32 hs_mask;
211};
212
213#define _IBMR(i2c) ((i2c)->reg_ibmr)
214#define _IDBR(i2c) ((i2c)->reg_idbr)
215#define _ICR(i2c) ((i2c)->reg_icr)
216#define _ISR(i2c) ((i2c)->reg_isr)
217#define _ISAR(i2c) ((i2c)->reg_isar)
218#define _ILCR(i2c) ((i2c)->reg_ilcr)
219#define _IWCR(i2c) ((i2c)->reg_iwcr)
220
221
222
223
224#define I2C_PXA_SLAVE_ADDR 0x1
225
226#ifdef DEBUG
227
228struct bits {
229 u32 mask;
230 const char *set;
231 const char *unset;
232};
233#define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
234
235static inline void
236decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
237{
238 printk("%s %08x: ", prefix, val);
239 while (num--) {
240 const char *str = val & bits->mask ? bits->set : bits->unset;
241 if (str)
242 printk("%s ", str);
243 bits++;
244 }
245}
246
247static const struct bits isr_bits[] = {
248 PXA_BIT(ISR_RWM, "RX", "TX"),
249 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
250 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
251 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
252 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
253 PXA_BIT(ISR_ALD, "ALD", NULL),
254 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
255 PXA_BIT(ISR_IRF, "RxFull", NULL),
256 PXA_BIT(ISR_GCAD, "GenCall", NULL),
257 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
258 PXA_BIT(ISR_BED, "BusErr", NULL),
259};
260
261static void decode_ISR(unsigned int val)
262{
263 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
264 printk("\n");
265}
266
267static const struct bits icr_bits[] = {
268 PXA_BIT(ICR_START, "START", NULL),
269 PXA_BIT(ICR_STOP, "STOP", NULL),
270 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
271 PXA_BIT(ICR_TB, "TB", NULL),
272 PXA_BIT(ICR_MA, "MA", NULL),
273 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
274 PXA_BIT(ICR_IUE, "IUE", "iue"),
275 PXA_BIT(ICR_GCD, "GCD", NULL),
276 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
277 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
278 PXA_BIT(ICR_BEIE, "BEIE", NULL),
279 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
280 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
281 PXA_BIT(ICR_SADIE, "SADIE", NULL),
282 PXA_BIT(ICR_UR, "UR", "ur"),
283};
284
285#ifdef CONFIG_I2C_PXA_SLAVE
286static void decode_ICR(unsigned int val)
287{
288 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
289 printk("\n");
290}
291#endif
292
293static unsigned int i2c_debug = DEBUG;
294
295static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
296{
297 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
298 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
299}
300
301#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
302
303static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
304{
305 unsigned int i;
306 struct device *dev = &i2c->adap.dev;
307
308 dev_err(dev, "slave_0x%x error: %s\n",
309 i2c->req_slave_addr >> 1, why);
310 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
311 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
312 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
313 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
314 readl(_ISR(i2c)));
315 dev_dbg(dev, "log: ");
316 for (i = 0; i < i2c->irqlogidx; i++)
317 pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
318
319 pr_debug("\n");
320}
321
322#else
323
324#define i2c_debug 0
325
326#define show_state(i2c) do { } while (0)
327#define decode_ISR(val) do { } while (0)
328#define decode_ICR(val) do { } while (0)
329#define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
330
331#endif
332
333static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
334static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
335
336static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
337{
338 return !(readl(_ICR(i2c)) & ICR_SCLE);
339}
340
341static void i2c_pxa_abort(struct pxa_i2c *i2c)
342{
343 int i = 250;
344
345 if (i2c_pxa_is_slavemode(i2c)) {
346 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
347 return;
348 }
349
350 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
351 unsigned long icr = readl(_ICR(i2c));
352
353 icr &= ~ICR_START;
354 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
355
356 writel(icr, _ICR(i2c));
357
358 show_state(i2c);
359
360 mdelay(1);
361 i --;
362 }
363
364 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
365 _ICR(i2c));
366}
367
368static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
369{
370 int timeout = DEF_TIMEOUT;
371
372 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
373 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
374 timeout += 4;
375
376 msleep(2);
377 show_state(i2c);
378 }
379
380 if (timeout < 0)
381 show_state(i2c);
382
383 return timeout < 0 ? I2C_RETRY : 0;
384}
385
386static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
387{
388 unsigned long timeout = jiffies + HZ*4;
389
390 while (time_before(jiffies, timeout)) {
391 if (i2c_debug > 1)
392 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
393 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
394
395 if (readl(_ISR(i2c)) & ISR_SAD) {
396 if (i2c_debug > 0)
397 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
398 goto out;
399 }
400
401
402
403
404
405 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
406 if (i2c_debug > 0)
407 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
408 return 1;
409 }
410
411 msleep(1);
412 }
413
414 if (i2c_debug > 0)
415 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
416 out:
417 return 0;
418}
419
420static int i2c_pxa_set_master(struct pxa_i2c *i2c)
421{
422 if (i2c_debug)
423 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
424
425 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
426 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
427 if (!i2c_pxa_wait_master(i2c)) {
428 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
429 return I2C_RETRY;
430 }
431 }
432
433 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
434 return 0;
435}
436
437#ifdef CONFIG_I2C_PXA_SLAVE
438static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
439{
440 unsigned long timeout = jiffies + HZ*1;
441
442
443
444 show_state(i2c);
445
446 while (time_before(jiffies, timeout)) {
447 if (i2c_debug > 1)
448 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
449 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
450
451 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
452 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
453 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
454 if (i2c_debug > 1)
455 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
456 return 1;
457 }
458
459 msleep(1);
460 }
461
462 if (i2c_debug > 0)
463 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
464 return 0;
465}
466
467
468
469
470
471static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
472{
473 show_state(i2c);
474
475 if (errcode < 0) {
476 udelay(100);
477 } else {
478
479
480
481 if (readl(_ICR(i2c)) & ICR_STOP) {
482 udelay(100);
483 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
484 }
485
486 if (!i2c_pxa_wait_slave(i2c)) {
487 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
488 __func__);
489 return;
490 }
491 }
492
493 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
494 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
495
496 if (i2c_debug) {
497 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
498 decode_ICR(readl(_ICR(i2c)));
499 }
500}
501#else
502#define i2c_pxa_set_slave(i2c, err) do { } while (0)
503#endif
504
505static void i2c_pxa_reset(struct pxa_i2c *i2c)
506{
507 pr_debug("Resetting I2C Controller Unit\n");
508
509
510 i2c_pxa_abort(i2c);
511
512
513 writel(ICR_UR, _ICR(i2c));
514 writel(I2C_ISR_INIT, _ISR(i2c));
515 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
516
517 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
518 writel(i2c->slave_addr, _ISAR(i2c));
519
520
521 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
522 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
523
524#ifdef CONFIG_I2C_PXA_SLAVE
525 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
526 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
527#endif
528
529 i2c_pxa_set_slave(i2c, 0);
530
531
532 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
533 udelay(100);
534}
535
536
537#ifdef CONFIG_I2C_PXA_SLAVE
538
539
540
541
542static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
543{
544 if (isr & ISR_BED) {
545
546 } else {
547 int ret = 0;
548
549 if (i2c->slave != NULL)
550 ret = i2c->slave->read(i2c->slave->data);
551
552 writel(ret, _IDBR(i2c));
553 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
554 }
555}
556
557static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
558{
559 unsigned int byte = readl(_IDBR(i2c));
560
561 if (i2c->slave != NULL)
562 i2c->slave->write(i2c->slave->data, byte);
563
564 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
565}
566
567static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
568{
569 int timeout;
570
571 if (i2c_debug > 0)
572 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
573 (isr & ISR_RWM) ? 'r' : 't');
574
575 if (i2c->slave != NULL)
576 i2c->slave->event(i2c->slave->data,
577 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
578
579
580
581
582
583
584 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
585 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
586
587 timeout = 0x10000;
588
589 while (1) {
590 if ((readl(_IBMR(i2c)) & 2) == 2)
591 break;
592
593 timeout--;
594
595 if (timeout <= 0) {
596 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
597 break;
598 }
599 }
600
601 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
602}
603
604static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
605{
606 if (i2c_debug > 2)
607 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
608
609 if (i2c->slave != NULL)
610 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
611
612 if (i2c_debug > 2)
613 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
614
615
616
617
618
619 if (i2c->msg)
620 i2c_pxa_master_complete(i2c, I2C_RETRY);
621}
622#else
623static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
624{
625 if (isr & ISR_BED) {
626
627 } else {
628 writel(0, _IDBR(i2c));
629 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
630 }
631}
632
633static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
634{
635 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
636}
637
638static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
639{
640 int timeout;
641
642
643
644
645
646
647 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
648 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
649
650 timeout = 0x10000;
651
652 while (1) {
653 if ((readl(_IBMR(i2c)) & 2) == 2)
654 break;
655
656 timeout--;
657
658 if (timeout <= 0) {
659 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
660 break;
661 }
662 }
663
664 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
665}
666
667static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
668{
669 if (i2c->msg)
670 i2c_pxa_master_complete(i2c, I2C_RETRY);
671}
672#endif
673
674
675
676
677
678static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
679{
680 unsigned int addr = (msg->addr & 0x7f) << 1;
681
682 if (msg->flags & I2C_M_RD)
683 addr |= 1;
684
685 return addr;
686}
687
688static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
689{
690 u32 icr;
691
692
693
694
695 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
696 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
697
698
699
700
701 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
702 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
703}
704
705static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
706{
707 u32 icr;
708
709
710
711
712 icr = readl(_ICR(i2c));
713 icr &= ~(ICR_STOP | ICR_ACKNAK);
714 writel(icr, _ICR(i2c));
715}
716
717static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
718{
719
720 long timeout = 2 * DEF_TIMEOUT;
721
722
723
724
725 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
726 udelay(1000);
727 show_state(i2c);
728 }
729
730 if (timeout < 0) {
731 show_state(i2c);
732 dev_err(&i2c->adap.dev,
733 "i2c_pxa: timeout waiting for bus free\n");
734 return I2C_RETRY;
735 }
736
737
738
739
740 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
741
742 return 0;
743}
744
745
746
747
748
749
750
751static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
752{
753 u32 icr;
754 long timeout;
755
756 spin_lock_irq(&i2c->lock);
757 i2c->highmode_enter = true;
758 writel(i2c->master_code, _IDBR(i2c));
759
760 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
761 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
762 writel(icr, _ICR(i2c));
763
764 spin_unlock_irq(&i2c->lock);
765 timeout = wait_event_timeout(i2c->wait,
766 i2c->highmode_enter == false, HZ * 1);
767
768 i2c->highmode_enter = false;
769
770 return (timeout == 0) ? I2C_RETRY : 0;
771}
772
773static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
774 struct i2c_msg *msg, int num)
775{
776 unsigned long timeout = 500000;
777 int ret = 0;
778
779 ret = i2c_pxa_pio_set_master(i2c);
780 if (ret)
781 goto out;
782
783 i2c->msg = msg;
784 i2c->msg_num = num;
785 i2c->msg_idx = 0;
786 i2c->msg_ptr = 0;
787 i2c->irqlogidx = 0;
788
789 i2c_pxa_start_message(i2c);
790
791 while (i2c->msg_num > 0 && --timeout) {
792 i2c_pxa_handler(0, i2c);
793 udelay(10);
794 }
795
796 i2c_pxa_stop_message(i2c);
797
798
799
800
801 ret = i2c->msg_idx;
802
803out:
804 if (timeout == 0) {
805 i2c_pxa_scream_blue_murder(i2c, "timeout");
806 ret = I2C_RETRY;
807 }
808
809 return ret;
810}
811
812
813
814
815static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
816{
817 long timeout;
818 int ret;
819
820
821
822
823 ret = i2c_pxa_wait_bus_not_busy(i2c);
824 if (ret) {
825 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
826 goto out;
827 }
828
829
830
831
832 ret = i2c_pxa_set_master(i2c);
833 if (ret) {
834 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
835 goto out;
836 }
837
838 if (i2c->high_mode) {
839 ret = i2c_pxa_send_mastercode(i2c);
840 if (ret) {
841 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
842 goto out;
843 }
844 }
845
846 spin_lock_irq(&i2c->lock);
847
848 i2c->msg = msg;
849 i2c->msg_num = num;
850 i2c->msg_idx = 0;
851 i2c->msg_ptr = 0;
852 i2c->irqlogidx = 0;
853
854 i2c_pxa_start_message(i2c);
855
856 spin_unlock_irq(&i2c->lock);
857
858
859
860
861 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
862 i2c_pxa_stop_message(i2c);
863
864
865
866
867 ret = i2c->msg_idx;
868
869 if (!timeout && i2c->msg_num) {
870 i2c_pxa_scream_blue_murder(i2c, "timeout");
871 ret = I2C_RETRY;
872 }
873
874 out:
875 return ret;
876}
877
878static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
879 struct i2c_msg msgs[], int num)
880{
881 struct pxa_i2c *i2c = adap->algo_data;
882 int ret, i;
883
884
885
886
887
888 if (!(readl(_ICR(i2c)) & ICR_IUE))
889 i2c_pxa_reset(i2c);
890
891 for (i = adap->retries; i >= 0; i--) {
892 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
893 if (ret != I2C_RETRY)
894 goto out;
895
896 if (i2c_debug)
897 dev_dbg(&adap->dev, "Retrying transmission\n");
898 udelay(100);
899 }
900 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
901 ret = -EREMOTEIO;
902 out:
903 i2c_pxa_set_slave(i2c, ret);
904 return ret;
905}
906
907
908
909
910static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
911{
912 i2c->msg_ptr = 0;
913 i2c->msg = NULL;
914 i2c->msg_idx ++;
915 i2c->msg_num = 0;
916 if (ret)
917 i2c->msg_idx = ret;
918 if (!i2c->use_pio)
919 wake_up(&i2c->wait);
920}
921
922static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
923{
924 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
925
926 again:
927
928
929
930 if (isr & ISR_ALD) {
931
932
933
934
935 i2c_pxa_scream_blue_murder(i2c, "ALD set");
936
937
938
939
940
941
942
943 return;
944 }
945
946 if ((isr & ISR_BED) &&
947 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
948 (isr & ISR_ACKNAK)))) {
949 int ret = BUS_ERROR;
950
951
952
953
954
955
956 if (isr & ISR_ACKNAK) {
957 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
958 ret = I2C_RETRY;
959 else
960 ret = XFER_NAKED;
961 }
962 i2c_pxa_master_complete(i2c, ret);
963 } else if (isr & ISR_RWM) {
964
965
966
967
968 if (i2c->msg_ptr == i2c->msg->len - 1 &&
969 i2c->msg_idx == i2c->msg_num - 1)
970 icr |= ICR_STOP | ICR_ACKNAK;
971
972 icr |= ICR_ALDIE | ICR_TB;
973 } else if (i2c->msg_ptr < i2c->msg->len) {
974
975
976
977 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
978
979 icr |= ICR_ALDIE | ICR_TB;
980
981
982
983
984
985 if ((i2c->msg_ptr == i2c->msg->len) &&
986 ((i2c->msg->flags & I2C_M_STOP) ||
987 (i2c->msg_idx == i2c->msg_num - 1)))
988 icr |= ICR_STOP;
989
990 } else if (i2c->msg_idx < i2c->msg_num - 1) {
991
992
993
994 i2c->msg_ptr = 0;
995 i2c->msg_idx ++;
996 i2c->msg++;
997
998
999
1000
1001
1002
1003 if (i2c->msg->flags & I2C_M_NOSTART)
1004 goto again;
1005
1006
1007
1008
1009 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
1010 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
1011
1012
1013
1014
1015 icr &= ~ICR_ALDIE;
1016 icr |= ICR_START | ICR_TB;
1017 } else {
1018 if (i2c->msg->len == 0) {
1019
1020
1021
1022
1023
1024 i2c_pxa_reset(i2c);
1025 }
1026 i2c_pxa_master_complete(i2c, 0);
1027 }
1028
1029 i2c->icrlog[i2c->irqlogidx-1] = icr;
1030
1031 writel(icr, _ICR(i2c));
1032 show_state(i2c);
1033}
1034
1035static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
1036{
1037 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
1038
1039
1040
1041
1042 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
1043
1044 if (i2c->msg_ptr < i2c->msg->len) {
1045
1046
1047
1048
1049 if (i2c->msg_ptr == i2c->msg->len - 1)
1050 icr |= ICR_STOP | ICR_ACKNAK;
1051
1052 icr |= ICR_ALDIE | ICR_TB;
1053 } else {
1054 i2c_pxa_master_complete(i2c, 0);
1055 }
1056
1057 i2c->icrlog[i2c->irqlogidx-1] = icr;
1058
1059 writel(icr, _ICR(i2c));
1060}
1061
1062#define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1063 ISR_SAD | ISR_BED)
1064static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1065{
1066 struct pxa_i2c *i2c = dev_id;
1067 u32 isr = readl(_ISR(i2c));
1068
1069 if (!(isr & VALID_INT_SOURCE))
1070 return IRQ_NONE;
1071
1072 if (i2c_debug > 2 && 0) {
1073 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1074 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1075 decode_ISR(isr);
1076 }
1077
1078 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1079 i2c->isrlog[i2c->irqlogidx++] = isr;
1080
1081 show_state(i2c);
1082
1083
1084
1085
1086 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1087
1088 if (isr & ISR_SAD)
1089 i2c_pxa_slave_start(i2c, isr);
1090 if (isr & ISR_SSD)
1091 i2c_pxa_slave_stop(i2c);
1092
1093 if (i2c_pxa_is_slavemode(i2c)) {
1094 if (isr & ISR_ITE)
1095 i2c_pxa_slave_txempty(i2c, isr);
1096 if (isr & ISR_IRF)
1097 i2c_pxa_slave_rxfull(i2c, isr);
1098 } else if (i2c->msg && (!i2c->highmode_enter)) {
1099 if (isr & ISR_ITE)
1100 i2c_pxa_irq_txempty(i2c, isr);
1101 if (isr & ISR_IRF)
1102 i2c_pxa_irq_rxfull(i2c, isr);
1103 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1104 i2c->highmode_enter = false;
1105 wake_up(&i2c->wait);
1106 } else {
1107 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1108 }
1109
1110 return IRQ_HANDLED;
1111}
1112
1113
1114static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1115{
1116 struct pxa_i2c *i2c = adap->algo_data;
1117 int ret, i;
1118
1119 for (i = adap->retries; i >= 0; i--) {
1120 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1121 if (ret != I2C_RETRY)
1122 goto out;
1123
1124 if (i2c_debug)
1125 dev_dbg(&adap->dev, "Retrying transmission\n");
1126 udelay(100);
1127 }
1128 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1129 ret = -EREMOTEIO;
1130 out:
1131 i2c_pxa_set_slave(i2c, ret);
1132 return ret;
1133}
1134
1135static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1136{
1137 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1138 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1139}
1140
1141static const struct i2c_algorithm i2c_pxa_algorithm = {
1142 .master_xfer = i2c_pxa_xfer,
1143 .functionality = i2c_pxa_functionality,
1144};
1145
1146static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1147 .master_xfer = i2c_pxa_pio_xfer,
1148 .functionality = i2c_pxa_functionality,
1149};
1150
1151static const struct of_device_id i2c_pxa_dt_ids[] = {
1152 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1153 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1154 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
1155 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
1156 {}
1157};
1158MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1159
1160static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1161 enum pxa_i2c_types *i2c_types)
1162{
1163 struct device_node *np = pdev->dev.of_node;
1164 const struct of_device_id *of_id =
1165 of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1166
1167 if (!of_id)
1168 return 1;
1169
1170
1171 i2c->adap.nr = -1;
1172
1173 if (of_get_property(np, "mrvl,i2c-polling", NULL))
1174 i2c->use_pio = 1;
1175 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1176 i2c->fast_mode = 1;
1177
1178 *i2c_types = (enum pxa_i2c_types)(of_id->data);
1179
1180 return 0;
1181}
1182
1183static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1184 struct pxa_i2c *i2c,
1185 enum pxa_i2c_types *i2c_types)
1186{
1187 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1188 const struct platform_device_id *id = platform_get_device_id(pdev);
1189
1190 *i2c_types = id->driver_data;
1191 if (plat) {
1192 i2c->use_pio = plat->use_pio;
1193 i2c->fast_mode = plat->fast_mode;
1194 i2c->high_mode = plat->high_mode;
1195 i2c->master_code = plat->master_code;
1196 if (!i2c->master_code)
1197 i2c->master_code = 0xe;
1198 i2c->rate = plat->rate;
1199 }
1200 return 0;
1201}
1202
1203static int i2c_pxa_probe(struct platform_device *dev)
1204{
1205 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1206 enum pxa_i2c_types i2c_type;
1207 struct pxa_i2c *i2c;
1208 struct resource *res = NULL;
1209 int ret, irq;
1210
1211 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1212 if (!i2c)
1213 return -ENOMEM;
1214
1215 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1216 i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1217 if (IS_ERR(i2c->reg_base))
1218 return PTR_ERR(i2c->reg_base);
1219
1220 irq = platform_get_irq(dev, 0);
1221 if (irq < 0) {
1222 dev_err(&dev->dev, "no irq resource: %d\n", irq);
1223 return irq;
1224 }
1225
1226
1227 i2c->adap.nr = dev->id;
1228
1229 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1230 if (ret > 0)
1231 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1232 if (ret < 0)
1233 return ret;
1234
1235 i2c->adap.owner = THIS_MODULE;
1236 i2c->adap.retries = 5;
1237
1238 spin_lock_init(&i2c->lock);
1239 init_waitqueue_head(&i2c->wait);
1240
1241 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1242
1243 i2c->clk = devm_clk_get(&dev->dev, NULL);
1244 if (IS_ERR(i2c->clk)) {
1245 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1246 return PTR_ERR(i2c->clk);
1247 }
1248
1249 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1250 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1251 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1252 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1253 i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM;
1254 i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS;
1255
1256 if (i2c_type != REGS_CE4100)
1257 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1258
1259 if (i2c_type == REGS_PXA910) {
1260 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1261 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1262 }
1263
1264 i2c->iobase = res->start;
1265 i2c->iosize = resource_size(res);
1266
1267 i2c->irq = irq;
1268
1269 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1270 i2c->highmode_enter = false;
1271
1272 if (plat) {
1273#ifdef CONFIG_I2C_PXA_SLAVE
1274 i2c->slave_addr = plat->slave_addr;
1275 i2c->slave = plat->slave;
1276#endif
1277 i2c->adap.class = plat->class;
1278 }
1279
1280 if (i2c->high_mode) {
1281 if (i2c->rate) {
1282 clk_set_rate(i2c->clk, i2c->rate);
1283 pr_info("i2c: <%s> set rate to %ld\n",
1284 i2c->adap.name, clk_get_rate(i2c->clk));
1285 } else
1286 pr_warn("i2c: <%s> clock rate not set\n",
1287 i2c->adap.name);
1288 }
1289
1290 clk_prepare_enable(i2c->clk);
1291
1292 if (i2c->use_pio) {
1293 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1294 } else {
1295 i2c->adap.algo = &i2c_pxa_algorithm;
1296 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1297 IRQF_SHARED | IRQF_NO_SUSPEND,
1298 dev_name(&dev->dev), i2c);
1299 if (ret) {
1300 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1301 goto ereqirq;
1302 }
1303 }
1304
1305 i2c_pxa_reset(i2c);
1306
1307 i2c->adap.algo_data = i2c;
1308 i2c->adap.dev.parent = &dev->dev;
1309#ifdef CONFIG_OF
1310 i2c->adap.dev.of_node = dev->dev.of_node;
1311#endif
1312
1313 ret = i2c_add_numbered_adapter(&i2c->adap);
1314 if (ret < 0)
1315 goto ereqirq;
1316
1317 platform_set_drvdata(dev, i2c);
1318
1319#ifdef CONFIG_I2C_PXA_SLAVE
1320 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1321 i2c->slave_addr);
1322#else
1323 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1324#endif
1325 return 0;
1326
1327ereqirq:
1328 clk_disable_unprepare(i2c->clk);
1329 return ret;
1330}
1331
1332static int i2c_pxa_remove(struct platform_device *dev)
1333{
1334 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1335
1336 i2c_del_adapter(&i2c->adap);
1337
1338 clk_disable_unprepare(i2c->clk);
1339
1340 return 0;
1341}
1342
1343#ifdef CONFIG_PM
1344static int i2c_pxa_suspend_noirq(struct device *dev)
1345{
1346 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1347
1348 clk_disable(i2c->clk);
1349
1350 return 0;
1351}
1352
1353static int i2c_pxa_resume_noirq(struct device *dev)
1354{
1355 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1356
1357 clk_enable(i2c->clk);
1358 i2c_pxa_reset(i2c);
1359
1360 return 0;
1361}
1362
1363static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1364 .suspend_noirq = i2c_pxa_suspend_noirq,
1365 .resume_noirq = i2c_pxa_resume_noirq,
1366};
1367
1368#define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1369#else
1370#define I2C_PXA_DEV_PM_OPS NULL
1371#endif
1372
1373static struct platform_driver i2c_pxa_driver = {
1374 .probe = i2c_pxa_probe,
1375 .remove = i2c_pxa_remove,
1376 .driver = {
1377 .name = "pxa2xx-i2c",
1378 .pm = I2C_PXA_DEV_PM_OPS,
1379 .of_match_table = i2c_pxa_dt_ids,
1380 },
1381 .id_table = i2c_pxa_id_table,
1382};
1383
1384static int __init i2c_adap_pxa_init(void)
1385{
1386 return platform_driver_register(&i2c_pxa_driver);
1387}
1388
1389static void __exit i2c_adap_pxa_exit(void)
1390{
1391 platform_driver_unregister(&i2c_pxa_driver);
1392}
1393
1394MODULE_LICENSE("GPL");
1395MODULE_ALIAS("platform:pxa2xx-i2c");
1396
1397subsys_initcall(i2c_adap_pxa_init);
1398module_exit(i2c_adap_pxa_exit);
1399
