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9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/err.h>
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/consumer.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/reset.h>
26
27#define BYTES_PER_FIFO_WORD 4
28
29#define I2C_CNFG 0x000
30#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
31#define I2C_CNFG_PACKET_MODE_EN BIT(10)
32#define I2C_CNFG_NEW_MASTER_FSM BIT(11)
33#define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
34#define I2C_STATUS 0x01C
35#define I2C_SL_CNFG 0x020
36#define I2C_SL_CNFG_NACK BIT(1)
37#define I2C_SL_CNFG_NEWSL BIT(2)
38#define I2C_SL_ADDR1 0x02c
39#define I2C_SL_ADDR2 0x030
40#define I2C_TX_FIFO 0x050
41#define I2C_RX_FIFO 0x054
42#define I2C_PACKET_TRANSFER_STATUS 0x058
43#define I2C_FIFO_CONTROL 0x05c
44#define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
45#define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
46#define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
47#define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
48#define I2C_FIFO_STATUS 0x060
49#define I2C_FIFO_STATUS_TX_MASK 0xF0
50#define I2C_FIFO_STATUS_TX_SHIFT 4
51#define I2C_FIFO_STATUS_RX_MASK 0x0F
52#define I2C_FIFO_STATUS_RX_SHIFT 0
53#define I2C_INT_MASK 0x064
54#define I2C_INT_STATUS 0x068
55#define I2C_INT_BUS_CLR_DONE BIT(11)
56#define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
57#define I2C_INT_NO_ACK BIT(3)
58#define I2C_INT_ARBITRATION_LOST BIT(2)
59#define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
60#define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
61#define I2C_CLK_DIVISOR 0x06c
62#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
63
64#define DVC_CTRL_REG1 0x000
65#define DVC_CTRL_REG1_INTR_EN BIT(10)
66#define DVC_CTRL_REG3 0x008
67#define DVC_CTRL_REG3_SW_PROG BIT(26)
68#define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
69#define DVC_STATUS 0x00c
70#define DVC_STATUS_I2C_DONE_INTR BIT(30)
71
72#define I2C_ERR_NONE 0x00
73#define I2C_ERR_NO_ACK BIT(0)
74#define I2C_ERR_ARBITRATION_LOST BIT(1)
75#define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
76#define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
77
78#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
79#define PACKET_HEADER0_PACKET_ID_SHIFT 16
80#define PACKET_HEADER0_CONT_ID_SHIFT 12
81#define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
82
83#define I2C_HEADER_CONT_ON_NAK BIT(21)
84#define I2C_HEADER_READ BIT(19)
85#define I2C_HEADER_10BIT_ADDR BIT(18)
86#define I2C_HEADER_IE_ENABLE BIT(17)
87#define I2C_HEADER_REPEAT_START BIT(16)
88#define I2C_HEADER_CONTINUE_XFER BIT(15)
89#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
90
91#define I2C_BUS_CLEAR_CNFG 0x084
92#define I2C_BC_SCLK_THRESHOLD 9
93#define I2C_BC_SCLK_THRESHOLD_SHIFT 16
94#define I2C_BC_STOP_COND BIT(2)
95#define I2C_BC_TERMINATE BIT(1)
96#define I2C_BC_ENABLE BIT(0)
97#define I2C_BUS_CLEAR_STATUS 0x088
98#define I2C_BC_STATUS BIT(0)
99
100#define I2C_CONFIG_LOAD 0x08C
101#define I2C_MSTR_CONFIG_LOAD BIT(0)
102
103#define I2C_CLKEN_OVERRIDE 0x090
104#define I2C_MST_CORE_CLKEN_OVR BIT(0)
105
106#define I2C_CONFIG_LOAD_TIMEOUT 1000000
107
108#define I2C_MST_FIFO_CONTROL 0x0b4
109#define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
110#define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
111#define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
112#define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
113
114#define I2C_MST_FIFO_STATUS 0x0b8
115#define I2C_MST_FIFO_STATUS_RX_MASK 0xff
116#define I2C_MST_FIFO_STATUS_RX_SHIFT 0
117#define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000
118#define I2C_MST_FIFO_STATUS_TX_SHIFT 16
119
120#define I2C_INTERFACE_TIMING_0 0x94
121#define I2C_THIGH_SHIFT 8
122#define I2C_INTERFACE_TIMING_1 0x98
123
124#define I2C_STANDARD_MODE 100000
125#define I2C_FAST_MODE 400000
126#define I2C_FAST_PLUS_MODE 1000000
127
128
129#define I2C_PACKET_HEADER_SIZE 12
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135
136#define I2C_PIO_MODE_MAX_LEN 32
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144
145enum msg_end_type {
146 MSG_END_STOP,
147 MSG_END_REPEAT_START,
148 MSG_END_CONTINUE,
149};
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196struct tegra_i2c_hw_feature {
197 bool has_continue_xfer_support;
198 bool has_per_pkt_xfer_complete_irq;
199 bool has_single_clk_source;
200 bool has_config_load_reg;
201 int clk_divisor_hs_mode;
202 int clk_divisor_std_mode;
203 int clk_divisor_fast_mode;
204 u16 clk_divisor_fast_plus_mode;
205 bool has_multi_master_mode;
206 bool has_slcg_override_reg;
207 bool has_mst_fifo;
208 const struct i2c_adapter_quirks *quirks;
209 bool supports_bus_clear;
210 bool has_apb_dma;
211 u8 tlow_std_mode;
212 u8 thigh_std_mode;
213 u8 tlow_fast_fastplus_mode;
214 u8 thigh_fast_fastplus_mode;
215 u32 setup_hold_time_std_mode;
216 u32 setup_hold_time_fast_fast_plus_mode;
217 u32 setup_hold_time_hs_mode;
218 bool has_interface_timing_reg;
219};
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252struct tegra_i2c_dev {
253 struct device *dev;
254 const struct tegra_i2c_hw_feature *hw;
255 struct i2c_adapter adapter;
256 struct clk *div_clk;
257 struct clk *fast_clk;
258 struct reset_control *rst;
259 void __iomem *base;
260 phys_addr_t base_phys;
261 int cont_id;
262 int irq;
263 bool irq_disabled;
264 int is_dvc;
265 struct completion msg_complete;
266 int msg_err;
267 u8 *msg_buf;
268 size_t msg_buf_remaining;
269 int msg_read;
270 u32 bus_clk_rate;
271 u16 clk_divisor_non_hs_mode;
272 bool is_multimaster_mode;
273
274 spinlock_t xfer_lock;
275 struct dma_chan *tx_dma_chan;
276 struct dma_chan *rx_dma_chan;
277 dma_addr_t dma_phys;
278 u32 *dma_buf;
279 unsigned int dma_buf_size;
280 bool is_curr_dma_xfer;
281 struct completion dma_complete;
282};
283
284static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
285 unsigned long reg)
286{
287 writel(val, i2c_dev->base + reg);
288}
289
290static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
291{
292 return readl(i2c_dev->base + reg);
293}
294
295
296
297
298
299static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
300 unsigned long reg)
301{
302 if (i2c_dev->is_dvc)
303 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
304 return reg;
305}
306
307static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
308 unsigned long reg)
309{
310 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
311
312
313 if (reg != I2C_TX_FIFO)
314 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
315}
316
317static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
318{
319 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
320}
321
322static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
323 unsigned long reg, int len)
324{
325 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
326}
327
328static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
329 unsigned long reg, int len)
330{
331 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
332}
333
334static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
335{
336 u32 int_mask;
337
338 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
339 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
340}
341
342static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
343{
344 u32 int_mask;
345
346 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
347 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
348}
349
350static void tegra_i2c_dma_complete(void *args)
351{
352 struct tegra_i2c_dev *i2c_dev = args;
353
354 complete(&i2c_dev->dma_complete);
355}
356
357static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
358{
359 struct dma_async_tx_descriptor *dma_desc;
360 enum dma_transfer_direction dir;
361 struct dma_chan *chan;
362
363 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
364 reinit_completion(&i2c_dev->dma_complete);
365 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
366 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
367 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
368 len, dir, DMA_PREP_INTERRUPT |
369 DMA_CTRL_ACK);
370 if (!dma_desc) {
371 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
372 return -EINVAL;
373 }
374
375 dma_desc->callback = tegra_i2c_dma_complete;
376 dma_desc->callback_param = i2c_dev;
377 dmaengine_submit(dma_desc);
378 dma_async_issue_pending(chan);
379 return 0;
380}
381
382static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
383{
384 if (i2c_dev->dma_buf) {
385 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
386 i2c_dev->dma_buf, i2c_dev->dma_phys);
387 i2c_dev->dma_buf = NULL;
388 }
389
390 if (i2c_dev->tx_dma_chan) {
391 dma_release_channel(i2c_dev->tx_dma_chan);
392 i2c_dev->tx_dma_chan = NULL;
393 }
394
395 if (i2c_dev->rx_dma_chan) {
396 dma_release_channel(i2c_dev->rx_dma_chan);
397 i2c_dev->rx_dma_chan = NULL;
398 }
399}
400
401static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
402{
403 struct dma_chan *chan;
404 u32 *dma_buf;
405 dma_addr_t dma_phys;
406 int err;
407
408 if (!i2c_dev->hw->has_apb_dma)
409 return 0;
410
411 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
412 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
413 return 0;
414 }
415
416 chan = dma_request_slave_channel_reason(i2c_dev->dev, "rx");
417 if (IS_ERR(chan)) {
418 err = PTR_ERR(chan);
419 goto err_out;
420 }
421
422 i2c_dev->rx_dma_chan = chan;
423
424 chan = dma_request_slave_channel_reason(i2c_dev->dev, "tx");
425 if (IS_ERR(chan)) {
426 err = PTR_ERR(chan);
427 goto err_out;
428 }
429
430 i2c_dev->tx_dma_chan = chan;
431
432 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
433 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
434 if (!dma_buf) {
435 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
436 err = -ENOMEM;
437 goto err_out;
438 }
439
440 i2c_dev->dma_buf = dma_buf;
441 i2c_dev->dma_phys = dma_phys;
442 return 0;
443
444err_out:
445 tegra_i2c_release_dma(i2c_dev);
446 if (err != -EPROBE_DEFER) {
447 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
448 dev_err(i2c_dev->dev, "falling back to PIO\n");
449 return 0;
450 }
451
452 return err;
453}
454
455static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
456{
457 unsigned long timeout = jiffies + HZ;
458 unsigned int offset;
459 u32 mask, val;
460
461 if (i2c_dev->hw->has_mst_fifo) {
462 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
463 I2C_MST_FIFO_CONTROL_RX_FLUSH;
464 offset = I2C_MST_FIFO_CONTROL;
465 } else {
466 mask = I2C_FIFO_CONTROL_TX_FLUSH |
467 I2C_FIFO_CONTROL_RX_FLUSH;
468 offset = I2C_FIFO_CONTROL;
469 }
470
471 val = i2c_readl(i2c_dev, offset);
472 val |= mask;
473 i2c_writel(i2c_dev, val, offset);
474
475 while (i2c_readl(i2c_dev, offset) & mask) {
476 if (time_after(jiffies, timeout)) {
477 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
478 return -ETIMEDOUT;
479 }
480 usleep_range(1000, 2000);
481 }
482 return 0;
483}
484
485static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
486{
487 u32 val;
488 int rx_fifo_avail;
489 u8 *buf = i2c_dev->msg_buf;
490 size_t buf_remaining = i2c_dev->msg_buf_remaining;
491 int words_to_transfer;
492
493
494
495
496
497 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
498 return -EINVAL;
499
500 if (i2c_dev->hw->has_mst_fifo) {
501 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
502 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
503 I2C_MST_FIFO_STATUS_RX_SHIFT;
504 } else {
505 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
506 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
507 I2C_FIFO_STATUS_RX_SHIFT;
508 }
509
510
511 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
512 if (words_to_transfer > rx_fifo_avail)
513 words_to_transfer = rx_fifo_avail;
514
515 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
516
517 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
518 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
519 rx_fifo_avail -= words_to_transfer;
520
521
522
523
524
525 if (rx_fifo_avail > 0 && buf_remaining > 0) {
526
527
528
529
530
531 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
532 val = cpu_to_le32(val);
533 memcpy(buf, &val, buf_remaining);
534 buf_remaining = 0;
535 rx_fifo_avail--;
536 }
537
538
539 if (WARN_ON_ONCE(rx_fifo_avail))
540 return -EINVAL;
541
542 i2c_dev->msg_buf_remaining = buf_remaining;
543 i2c_dev->msg_buf = buf;
544
545 return 0;
546}
547
548static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
549{
550 u32 val;
551 int tx_fifo_avail;
552 u8 *buf = i2c_dev->msg_buf;
553 size_t buf_remaining = i2c_dev->msg_buf_remaining;
554 int words_to_transfer;
555
556 if (i2c_dev->hw->has_mst_fifo) {
557 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
558 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
559 I2C_MST_FIFO_STATUS_TX_SHIFT;
560 } else {
561 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
562 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
563 I2C_FIFO_STATUS_TX_SHIFT;
564 }
565
566
567 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
568
569
570 if (words_to_transfer) {
571 if (words_to_transfer > tx_fifo_avail)
572 words_to_transfer = tx_fifo_avail;
573
574
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577
578
579
580
581 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
582 tx_fifo_avail -= words_to_transfer;
583 i2c_dev->msg_buf_remaining = buf_remaining;
584 i2c_dev->msg_buf = buf +
585 words_to_transfer * BYTES_PER_FIFO_WORD;
586 barrier();
587
588 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
589
590 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
591 }
592
593
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595
596
597
598 if (tx_fifo_avail > 0 && buf_remaining > 0) {
599
600
601
602
603
604 memcpy(&val, buf, buf_remaining);
605 val = le32_to_cpu(val);
606
607
608 i2c_dev->msg_buf_remaining = 0;
609 i2c_dev->msg_buf = NULL;
610 barrier();
611
612 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
613 }
614
615 return 0;
616}
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623
624
625static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
626{
627 u32 val;
628
629 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
630 val |= DVC_CTRL_REG3_SW_PROG;
631 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
632 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
633
634 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
635 val |= DVC_CTRL_REG1_INTR_EN;
636 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
637}
638
639static int tegra_i2c_runtime_resume(struct device *dev)
640{
641 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
642 int ret;
643
644 ret = pinctrl_pm_select_default_state(i2c_dev->dev);
645 if (ret)
646 return ret;
647
648 if (!i2c_dev->hw->has_single_clk_source) {
649 ret = clk_enable(i2c_dev->fast_clk);
650 if (ret < 0) {
651 dev_err(i2c_dev->dev,
652 "Enabling fast clk failed, err %d\n", ret);
653 return ret;
654 }
655 }
656
657 ret = clk_enable(i2c_dev->div_clk);
658 if (ret < 0) {
659 dev_err(i2c_dev->dev,
660 "Enabling div clk failed, err %d\n", ret);
661 clk_disable(i2c_dev->fast_clk);
662 return ret;
663 }
664
665 return 0;
666}
667
668static int tegra_i2c_runtime_suspend(struct device *dev)
669{
670 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
671
672 clk_disable(i2c_dev->div_clk);
673 if (!i2c_dev->hw->has_single_clk_source)
674 clk_disable(i2c_dev->fast_clk);
675
676 return pinctrl_pm_select_idle_state(i2c_dev->dev);
677}
678
679static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
680{
681 unsigned long reg_offset;
682 void __iomem *addr;
683 u32 val;
684 int err;
685
686 if (i2c_dev->hw->has_config_load_reg) {
687 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
688 addr = i2c_dev->base + reg_offset;
689 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
690 if (in_interrupt())
691 err = readl_poll_timeout_atomic(addr, val, val == 0,
692 1000,
693 I2C_CONFIG_LOAD_TIMEOUT);
694 else
695 err = readl_poll_timeout(addr, val, val == 0, 1000,
696 I2C_CONFIG_LOAD_TIMEOUT);
697
698 if (err) {
699 dev_warn(i2c_dev->dev,
700 "timeout waiting for config load\n");
701 return err;
702 }
703 }
704
705 return 0;
706}
707
708static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
709{
710 u32 val;
711 int err;
712 u32 clk_divisor, clk_multiplier;
713 u32 tsu_thd;
714 u8 tlow, thigh;
715
716 err = pm_runtime_get_sync(i2c_dev->dev);
717 if (err < 0) {
718 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
719 return err;
720 }
721
722 reset_control_assert(i2c_dev->rst);
723 udelay(2);
724 reset_control_deassert(i2c_dev->rst);
725
726 if (i2c_dev->is_dvc)
727 tegra_dvc_init(i2c_dev);
728
729 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
730 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
731
732 if (i2c_dev->hw->has_multi_master_mode)
733 val |= I2C_CNFG_MULTI_MASTER_MODE;
734
735 i2c_writel(i2c_dev, val, I2C_CNFG);
736 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
737
738
739 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
740 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
741 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
742 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
743
744 if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
745 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) {
746 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
747 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
748 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
749 } else {
750 tlow = i2c_dev->hw->tlow_std_mode;
751 thigh = i2c_dev->hw->thigh_std_mode;
752 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
753 }
754
755 if (i2c_dev->hw->has_interface_timing_reg) {
756 val = (thigh << I2C_THIGH_SHIFT) | tlow;
757 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
758 }
759
760
761
762
763
764 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
765 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
766
767 if (!clk_reinit) {
768 clk_multiplier = (tlow + thigh + 2);
769 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
770 err = clk_set_rate(i2c_dev->div_clk,
771 i2c_dev->bus_clk_rate * clk_multiplier);
772 if (err) {
773 dev_err(i2c_dev->dev,
774 "failed changing clock rate: %d\n", err);
775 goto err;
776 }
777 }
778
779 if (!i2c_dev->is_dvc) {
780 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
781
782 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
783 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
784 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
785 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
786 }
787
788 err = tegra_i2c_flush_fifos(i2c_dev);
789 if (err)
790 goto err;
791
792 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
793 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
794
795 err = tegra_i2c_wait_for_config_load(i2c_dev);
796 if (err)
797 goto err;
798
799 if (i2c_dev->irq_disabled) {
800 i2c_dev->irq_disabled = false;
801 enable_irq(i2c_dev->irq);
802 }
803
804err:
805 pm_runtime_put(i2c_dev->dev);
806 return err;
807}
808
809static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
810{
811 u32 cnfg;
812
813
814
815
816
817
818
819 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
820
821 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
822 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
823 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
824
825 return tegra_i2c_wait_for_config_load(i2c_dev);
826}
827
828static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
829{
830 u32 status;
831 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
832 struct tegra_i2c_dev *i2c_dev = dev_id;
833
834 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
835
836 spin_lock(&i2c_dev->xfer_lock);
837 if (status == 0) {
838 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
839 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
840 i2c_readl(i2c_dev, I2C_STATUS),
841 i2c_readl(i2c_dev, I2C_CNFG));
842 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
843
844 if (!i2c_dev->irq_disabled) {
845 disable_irq_nosync(i2c_dev->irq);
846 i2c_dev->irq_disabled = true;
847 }
848 goto err;
849 }
850
851 if (unlikely(status & status_err)) {
852 tegra_i2c_disable_packet_mode(i2c_dev);
853 if (status & I2C_INT_NO_ACK)
854 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
855 if (status & I2C_INT_ARBITRATION_LOST)
856 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
857 goto err;
858 }
859
860
861
862
863
864 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
865 goto err;
866
867 if (!i2c_dev->is_curr_dma_xfer) {
868 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
869 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
870
871
872
873
874
875 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
876 goto err;
877 }
878 }
879
880 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
881 if (i2c_dev->msg_buf_remaining)
882 tegra_i2c_fill_tx_fifo(i2c_dev);
883 else
884 tegra_i2c_mask_irq(i2c_dev,
885 I2C_INT_TX_FIFO_DATA_REQ);
886 }
887 }
888
889 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
890 if (i2c_dev->is_dvc)
891 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
892
893
894
895
896
897
898
899
900 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
901 if (i2c_dev->is_curr_dma_xfer)
902 i2c_dev->msg_buf_remaining = 0;
903
904
905
906
907 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
908 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
909 goto err;
910 }
911 complete(&i2c_dev->msg_complete);
912 }
913 goto done;
914err:
915
916 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
917 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
918 I2C_INT_RX_FIFO_DATA_REQ);
919 if (i2c_dev->hw->supports_bus_clear)
920 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
921 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
922 if (i2c_dev->is_dvc)
923 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
924
925 if (i2c_dev->is_curr_dma_xfer) {
926 if (i2c_dev->msg_read)
927 dmaengine_terminate_async(i2c_dev->rx_dma_chan);
928 else
929 dmaengine_terminate_async(i2c_dev->tx_dma_chan);
930
931 complete(&i2c_dev->dma_complete);
932 }
933
934 complete(&i2c_dev->msg_complete);
935done:
936 spin_unlock(&i2c_dev->xfer_lock);
937 return IRQ_HANDLED;
938}
939
940static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
941 size_t len)
942{
943 u32 val, reg;
944 u8 dma_burst;
945 struct dma_slave_config slv_config = {0};
946 struct dma_chan *chan;
947 int ret;
948 unsigned long reg_offset;
949
950 if (i2c_dev->hw->has_mst_fifo)
951 reg = I2C_MST_FIFO_CONTROL;
952 else
953 reg = I2C_FIFO_CONTROL;
954
955 if (i2c_dev->is_curr_dma_xfer) {
956 if (len & 0xF)
957 dma_burst = 1;
958 else if (len & 0x10)
959 dma_burst = 4;
960 else
961 dma_burst = 8;
962
963 if (i2c_dev->msg_read) {
964 chan = i2c_dev->rx_dma_chan;
965 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
966 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
967 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
968 slv_config.src_maxburst = dma_burst;
969
970 if (i2c_dev->hw->has_mst_fifo)
971 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
972 else
973 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
974 } else {
975 chan = i2c_dev->tx_dma_chan;
976 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
977 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
978 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
979 slv_config.dst_maxburst = dma_burst;
980
981 if (i2c_dev->hw->has_mst_fifo)
982 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
983 else
984 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
985 }
986
987 slv_config.device_fc = true;
988 ret = dmaengine_slave_config(chan, &slv_config);
989 if (ret < 0) {
990 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
991 ret);
992 dev_err(i2c_dev->dev, "falling back to PIO\n");
993 tegra_i2c_release_dma(i2c_dev);
994 i2c_dev->is_curr_dma_xfer = false;
995 } else {
996 goto out;
997 }
998 }
999
1000 if (i2c_dev->hw->has_mst_fifo)
1001 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1002 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1003 else
1004 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1005 I2C_FIFO_CONTROL_RX_TRIG(1);
1006out:
1007 i2c_writel(i2c_dev, val, reg);
1008}
1009
1010static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1011{
1012 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1013 int err;
1014 unsigned long time_left;
1015 u32 reg;
1016
1017 reinit_completion(&i2c_dev->msg_complete);
1018 reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) |
1019 I2C_BC_STOP_COND | I2C_BC_TERMINATE;
1020 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1021 if (i2c_dev->hw->has_config_load_reg) {
1022 err = tegra_i2c_wait_for_config_load(i2c_dev);
1023 if (err)
1024 return err;
1025 }
1026
1027 reg |= I2C_BC_ENABLE;
1028 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1029 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1030
1031 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1032 msecs_to_jiffies(50));
1033 if (time_left == 0) {
1034 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1035 return -ETIMEDOUT;
1036 }
1037
1038 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1039 if (!(reg & I2C_BC_STATUS)) {
1040 dev_err(i2c_dev->dev,
1041 "un-recovered arbitration lost\n");
1042 return -EIO;
1043 }
1044
1045 return -EAGAIN;
1046}
1047
1048static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1049 struct i2c_msg *msg,
1050 enum msg_end_type end_state)
1051{
1052 u32 packet_header;
1053 u32 int_mask;
1054 unsigned long time_left;
1055 unsigned long flags;
1056 size_t xfer_size;
1057 u32 *buffer = NULL;
1058 int err = 0;
1059 bool dma;
1060 u16 xfer_time = 100;
1061
1062 tegra_i2c_flush_fifos(i2c_dev);
1063
1064 i2c_dev->msg_buf = msg->buf;
1065 i2c_dev->msg_buf_remaining = msg->len;
1066 i2c_dev->msg_err = I2C_ERR_NONE;
1067 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1068 reinit_completion(&i2c_dev->msg_complete);
1069
1070 if (i2c_dev->msg_read)
1071 xfer_size = msg->len;
1072 else
1073 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1074
1075 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1076 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_MAX_LEN) &&
1077 i2c_dev->dma_buf;
1078 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1079 dma = i2c_dev->is_curr_dma_xfer;
1080
1081
1082
1083
1084 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1085 i2c_dev->bus_clk_rate);
1086 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
1087
1088 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1089 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1090 if (dma) {
1091 if (i2c_dev->msg_read) {
1092 dma_sync_single_for_device(i2c_dev->dev,
1093 i2c_dev->dma_phys,
1094 xfer_size,
1095 DMA_FROM_DEVICE);
1096 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1097 if (err < 0) {
1098 dev_err(i2c_dev->dev,
1099 "starting RX DMA failed, err %d\n",
1100 err);
1101 goto unlock;
1102 }
1103
1104 } else {
1105 dma_sync_single_for_cpu(i2c_dev->dev,
1106 i2c_dev->dma_phys,
1107 xfer_size,
1108 DMA_TO_DEVICE);
1109 buffer = i2c_dev->dma_buf;
1110 }
1111 }
1112
1113 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
1114 PACKET_HEADER0_PROTOCOL_I2C |
1115 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
1116 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
1117 if (dma && !i2c_dev->msg_read)
1118 *buffer++ = packet_header;
1119 else
1120 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1121
1122 packet_header = msg->len - 1;
1123 if (dma && !i2c_dev->msg_read)
1124 *buffer++ = packet_header;
1125 else
1126 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1127
1128 packet_header = I2C_HEADER_IE_ENABLE;
1129 if (end_state == MSG_END_CONTINUE)
1130 packet_header |= I2C_HEADER_CONTINUE_XFER;
1131 else if (end_state == MSG_END_REPEAT_START)
1132 packet_header |= I2C_HEADER_REPEAT_START;
1133 if (msg->flags & I2C_M_TEN) {
1134 packet_header |= msg->addr;
1135 packet_header |= I2C_HEADER_10BIT_ADDR;
1136 } else {
1137 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1138 }
1139 if (msg->flags & I2C_M_IGNORE_NAK)
1140 packet_header |= I2C_HEADER_CONT_ON_NAK;
1141 if (msg->flags & I2C_M_RD)
1142 packet_header |= I2C_HEADER_READ;
1143 if (dma && !i2c_dev->msg_read)
1144 *buffer++ = packet_header;
1145 else
1146 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1147
1148 if (!i2c_dev->msg_read) {
1149 if (dma) {
1150 memcpy(buffer, msg->buf, msg->len);
1151 dma_sync_single_for_device(i2c_dev->dev,
1152 i2c_dev->dma_phys,
1153 xfer_size,
1154 DMA_TO_DEVICE);
1155 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1156 if (err < 0) {
1157 dev_err(i2c_dev->dev,
1158 "starting TX DMA failed, err %d\n",
1159 err);
1160 goto unlock;
1161 }
1162 } else {
1163 tegra_i2c_fill_tx_fifo(i2c_dev);
1164 }
1165 }
1166
1167 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1168 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1169 if (!dma) {
1170 if (msg->flags & I2C_M_RD)
1171 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1172 else if (i2c_dev->msg_buf_remaining)
1173 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1174 }
1175
1176 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1177 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1178 i2c_readl(i2c_dev, I2C_INT_MASK));
1179
1180unlock:
1181 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
1182
1183 if (dma) {
1184 if (err)
1185 return err;
1186
1187 time_left = wait_for_completion_timeout(&i2c_dev->dma_complete,
1188 msecs_to_jiffies(xfer_time));
1189 if (time_left == 0) {
1190 dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1191 dmaengine_terminate_sync(i2c_dev->msg_read ?
1192 i2c_dev->rx_dma_chan :
1193 i2c_dev->tx_dma_chan);
1194 tegra_i2c_init(i2c_dev, true);
1195 return -ETIMEDOUT;
1196 }
1197
1198 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1199 dma_sync_single_for_cpu(i2c_dev->dev,
1200 i2c_dev->dma_phys,
1201 xfer_size,
1202 DMA_FROM_DEVICE);
1203 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1204 msg->len);
1205 }
1206
1207 if (i2c_dev->msg_err != I2C_ERR_NONE)
1208 dmaengine_synchronize(i2c_dev->msg_read ?
1209 i2c_dev->rx_dma_chan :
1210 i2c_dev->tx_dma_chan);
1211 }
1212
1213 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1214 msecs_to_jiffies(xfer_time));
1215 tegra_i2c_mask_irq(i2c_dev, int_mask);
1216
1217 if (time_left == 0) {
1218 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1219
1220 tegra_i2c_init(i2c_dev, true);
1221 return -ETIMEDOUT;
1222 }
1223
1224 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1225 time_left, completion_done(&i2c_dev->msg_complete),
1226 i2c_dev->msg_err);
1227
1228 i2c_dev->is_curr_dma_xfer = false;
1229 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1230 return 0;
1231
1232 tegra_i2c_init(i2c_dev, true);
1233
1234 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1235 if (!i2c_dev->is_multimaster_mode)
1236 return i2c_recover_bus(&i2c_dev->adapter);
1237 return -EAGAIN;
1238 }
1239
1240 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1241 if (msg->flags & I2C_M_IGNORE_NAK)
1242 return 0;
1243 return -EREMOTEIO;
1244 }
1245
1246 return -EIO;
1247}
1248
1249static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1250 int num)
1251{
1252 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1253 int i;
1254 int ret;
1255
1256 ret = pm_runtime_get_sync(i2c_dev->dev);
1257 if (ret < 0) {
1258 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1259 return ret;
1260 }
1261
1262 for (i = 0; i < num; i++) {
1263 enum msg_end_type end_type = MSG_END_STOP;
1264
1265 if (i < (num - 1)) {
1266 if (msgs[i + 1].flags & I2C_M_NOSTART)
1267 end_type = MSG_END_CONTINUE;
1268 else
1269 end_type = MSG_END_REPEAT_START;
1270 }
1271 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1272 if (ret)
1273 break;
1274 }
1275
1276 pm_runtime_put(i2c_dev->dev);
1277
1278 return ret ?: i;
1279}
1280
1281static u32 tegra_i2c_func(struct i2c_adapter *adap)
1282{
1283 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1284 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1285 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1286
1287 if (i2c_dev->hw->has_continue_xfer_support)
1288 ret |= I2C_FUNC_NOSTART;
1289 return ret;
1290}
1291
1292static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1293{
1294 struct device_node *np = i2c_dev->dev->of_node;
1295 int ret;
1296 bool multi_mode;
1297
1298 ret = of_property_read_u32(np, "clock-frequency",
1299 &i2c_dev->bus_clk_rate);
1300 if (ret)
1301 i2c_dev->bus_clk_rate = 100000;
1302
1303 multi_mode = of_property_read_bool(np, "multi-master");
1304 i2c_dev->is_multimaster_mode = multi_mode;
1305}
1306
1307static const struct i2c_algorithm tegra_i2c_algo = {
1308 .master_xfer = tegra_i2c_xfer,
1309 .functionality = tegra_i2c_func,
1310};
1311
1312
1313static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1314 .flags = I2C_AQ_NO_ZERO_LEN,
1315 .max_read_len = SZ_4K,
1316 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1317};
1318
1319static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1320 .flags = I2C_AQ_NO_ZERO_LEN,
1321 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1322};
1323
1324static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1325 .recover_bus = tegra_i2c_issue_bus_clear,
1326};
1327
1328static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1329 .has_continue_xfer_support = false,
1330 .has_per_pkt_xfer_complete_irq = false,
1331 .has_single_clk_source = false,
1332 .clk_divisor_hs_mode = 3,
1333 .clk_divisor_std_mode = 0,
1334 .clk_divisor_fast_mode = 0,
1335 .clk_divisor_fast_plus_mode = 0,
1336 .has_config_load_reg = false,
1337 .has_multi_master_mode = false,
1338 .has_slcg_override_reg = false,
1339 .has_mst_fifo = false,
1340 .quirks = &tegra_i2c_quirks,
1341 .supports_bus_clear = false,
1342 .has_apb_dma = true,
1343 .tlow_std_mode = 0x4,
1344 .thigh_std_mode = 0x2,
1345 .tlow_fast_fastplus_mode = 0x4,
1346 .thigh_fast_fastplus_mode = 0x2,
1347 .setup_hold_time_std_mode = 0x0,
1348 .setup_hold_time_fast_fast_plus_mode = 0x0,
1349 .setup_hold_time_hs_mode = 0x0,
1350 .has_interface_timing_reg = false,
1351};
1352
1353static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1354 .has_continue_xfer_support = true,
1355 .has_per_pkt_xfer_complete_irq = false,
1356 .has_single_clk_source = false,
1357 .clk_divisor_hs_mode = 3,
1358 .clk_divisor_std_mode = 0,
1359 .clk_divisor_fast_mode = 0,
1360 .clk_divisor_fast_plus_mode = 0,
1361 .has_config_load_reg = false,
1362 .has_multi_master_mode = false,
1363 .has_slcg_override_reg = false,
1364 .has_mst_fifo = false,
1365 .quirks = &tegra_i2c_quirks,
1366 .supports_bus_clear = false,
1367 .has_apb_dma = true,
1368 .tlow_std_mode = 0x4,
1369 .thigh_std_mode = 0x2,
1370 .tlow_fast_fastplus_mode = 0x4,
1371 .thigh_fast_fastplus_mode = 0x2,
1372 .setup_hold_time_std_mode = 0x0,
1373 .setup_hold_time_fast_fast_plus_mode = 0x0,
1374 .setup_hold_time_hs_mode = 0x0,
1375 .has_interface_timing_reg = false,
1376};
1377
1378static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1379 .has_continue_xfer_support = true,
1380 .has_per_pkt_xfer_complete_irq = true,
1381 .has_single_clk_source = true,
1382 .clk_divisor_hs_mode = 1,
1383 .clk_divisor_std_mode = 0x19,
1384 .clk_divisor_fast_mode = 0x19,
1385 .clk_divisor_fast_plus_mode = 0x10,
1386 .has_config_load_reg = false,
1387 .has_multi_master_mode = false,
1388 .has_slcg_override_reg = false,
1389 .has_mst_fifo = false,
1390 .quirks = &tegra_i2c_quirks,
1391 .supports_bus_clear = true,
1392 .has_apb_dma = true,
1393 .tlow_std_mode = 0x4,
1394 .thigh_std_mode = 0x2,
1395 .tlow_fast_fastplus_mode = 0x4,
1396 .thigh_fast_fastplus_mode = 0x2,
1397 .setup_hold_time_std_mode = 0x0,
1398 .setup_hold_time_fast_fast_plus_mode = 0x0,
1399 .setup_hold_time_hs_mode = 0x0,
1400 .has_interface_timing_reg = false,
1401};
1402
1403static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1404 .has_continue_xfer_support = true,
1405 .has_per_pkt_xfer_complete_irq = true,
1406 .has_single_clk_source = true,
1407 .clk_divisor_hs_mode = 1,
1408 .clk_divisor_std_mode = 0x19,
1409 .clk_divisor_fast_mode = 0x19,
1410 .clk_divisor_fast_plus_mode = 0x10,
1411 .has_config_load_reg = true,
1412 .has_multi_master_mode = false,
1413 .has_slcg_override_reg = true,
1414 .has_mst_fifo = false,
1415 .quirks = &tegra_i2c_quirks,
1416 .supports_bus_clear = true,
1417 .has_apb_dma = true,
1418 .tlow_std_mode = 0x4,
1419 .thigh_std_mode = 0x2,
1420 .tlow_fast_fastplus_mode = 0x4,
1421 .thigh_fast_fastplus_mode = 0x2,
1422 .setup_hold_time_std_mode = 0x0,
1423 .setup_hold_time_fast_fast_plus_mode = 0x0,
1424 .setup_hold_time_hs_mode = 0x0,
1425 .has_interface_timing_reg = true,
1426};
1427
1428static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1429 .has_continue_xfer_support = true,
1430 .has_per_pkt_xfer_complete_irq = true,
1431 .has_single_clk_source = true,
1432 .clk_divisor_hs_mode = 1,
1433 .clk_divisor_std_mode = 0x19,
1434 .clk_divisor_fast_mode = 0x19,
1435 .clk_divisor_fast_plus_mode = 0x10,
1436 .has_config_load_reg = true,
1437 .has_multi_master_mode = false,
1438 .has_slcg_override_reg = true,
1439 .has_mst_fifo = false,
1440 .quirks = &tegra_i2c_quirks,
1441 .supports_bus_clear = true,
1442 .has_apb_dma = true,
1443 .tlow_std_mode = 0x4,
1444 .thigh_std_mode = 0x2,
1445 .tlow_fast_fastplus_mode = 0x4,
1446 .thigh_fast_fastplus_mode = 0x2,
1447 .setup_hold_time_std_mode = 0,
1448 .setup_hold_time_fast_fast_plus_mode = 0,
1449 .setup_hold_time_hs_mode = 0,
1450 .has_interface_timing_reg = true,
1451};
1452
1453static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1454 .has_continue_xfer_support = true,
1455 .has_per_pkt_xfer_complete_irq = true,
1456 .has_single_clk_source = true,
1457 .clk_divisor_hs_mode = 1,
1458 .clk_divisor_std_mode = 0x16,
1459 .clk_divisor_fast_mode = 0x19,
1460 .clk_divisor_fast_plus_mode = 0x10,
1461 .has_config_load_reg = true,
1462 .has_multi_master_mode = false,
1463 .has_slcg_override_reg = true,
1464 .has_mst_fifo = false,
1465 .quirks = &tegra_i2c_quirks,
1466 .supports_bus_clear = true,
1467 .has_apb_dma = false,
1468 .tlow_std_mode = 0x4,
1469 .thigh_std_mode = 0x3,
1470 .tlow_fast_fastplus_mode = 0x4,
1471 .thigh_fast_fastplus_mode = 0x2,
1472 .setup_hold_time_std_mode = 0,
1473 .setup_hold_time_fast_fast_plus_mode = 0,
1474 .setup_hold_time_hs_mode = 0,
1475 .has_interface_timing_reg = true,
1476};
1477
1478static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1479 .has_continue_xfer_support = true,
1480 .has_per_pkt_xfer_complete_irq = true,
1481 .has_single_clk_source = true,
1482 .clk_divisor_hs_mode = 1,
1483 .clk_divisor_std_mode = 0x4f,
1484 .clk_divisor_fast_mode = 0x3c,
1485 .clk_divisor_fast_plus_mode = 0x16,
1486 .has_config_load_reg = true,
1487 .has_multi_master_mode = true,
1488 .has_slcg_override_reg = true,
1489 .has_mst_fifo = true,
1490 .quirks = &tegra194_i2c_quirks,
1491 .supports_bus_clear = true,
1492 .has_apb_dma = false,
1493 .tlow_std_mode = 0x8,
1494 .thigh_std_mode = 0x7,
1495 .tlow_fast_fastplus_mode = 0x2,
1496 .thigh_fast_fastplus_mode = 0x2,
1497 .setup_hold_time_std_mode = 0x08080808,
1498 .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1499 .setup_hold_time_hs_mode = 0x090909,
1500 .has_interface_timing_reg = true,
1501};
1502
1503
1504static const struct of_device_id tegra_i2c_of_match[] = {
1505 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1506 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1507 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1508 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1509 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1510 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1511 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1512 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1513 {},
1514};
1515MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1516
1517static int tegra_i2c_probe(struct platform_device *pdev)
1518{
1519 struct tegra_i2c_dev *i2c_dev;
1520 struct resource *res;
1521 struct clk *div_clk;
1522 struct clk *fast_clk;
1523 void __iomem *base;
1524 phys_addr_t base_phys;
1525 int irq;
1526 int ret;
1527
1528 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1529 base_phys = res->start;
1530 base = devm_ioremap_resource(&pdev->dev, res);
1531 if (IS_ERR(base))
1532 return PTR_ERR(base);
1533
1534 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1535 if (!res) {
1536 dev_err(&pdev->dev, "no irq resource\n");
1537 return -EINVAL;
1538 }
1539 irq = res->start;
1540
1541 div_clk = devm_clk_get(&pdev->dev, "div-clk");
1542 if (IS_ERR(div_clk)) {
1543 if (PTR_ERR(div_clk) != -EPROBE_DEFER)
1544 dev_err(&pdev->dev, "missing controller clock\n");
1545
1546 return PTR_ERR(div_clk);
1547 }
1548
1549 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1550 if (!i2c_dev)
1551 return -ENOMEM;
1552
1553 i2c_dev->base = base;
1554 i2c_dev->base_phys = base_phys;
1555 i2c_dev->div_clk = div_clk;
1556 i2c_dev->adapter.algo = &tegra_i2c_algo;
1557 i2c_dev->adapter.retries = 1;
1558 i2c_dev->adapter.timeout = 6 * HZ;
1559 i2c_dev->irq = irq;
1560 i2c_dev->cont_id = pdev->id;
1561 i2c_dev->dev = &pdev->dev;
1562
1563 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1564 if (IS_ERR(i2c_dev->rst)) {
1565 dev_err(&pdev->dev, "missing controller reset\n");
1566 return PTR_ERR(i2c_dev->rst);
1567 }
1568
1569 tegra_i2c_parse_dt(i2c_dev);
1570
1571 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1572 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1573 "nvidia,tegra20-i2c-dvc");
1574 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1575 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1576 I2C_PACKET_HEADER_SIZE;
1577 init_completion(&i2c_dev->msg_complete);
1578 init_completion(&i2c_dev->dma_complete);
1579 spin_lock_init(&i2c_dev->xfer_lock);
1580
1581 if (!i2c_dev->hw->has_single_clk_source) {
1582 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1583 if (IS_ERR(fast_clk)) {
1584 dev_err(&pdev->dev, "missing fast clock\n");
1585 return PTR_ERR(fast_clk);
1586 }
1587 i2c_dev->fast_clk = fast_clk;
1588 }
1589
1590 platform_set_drvdata(pdev, i2c_dev);
1591
1592 if (!i2c_dev->hw->has_single_clk_source) {
1593 ret = clk_prepare(i2c_dev->fast_clk);
1594 if (ret < 0) {
1595 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1596 return ret;
1597 }
1598 }
1599
1600 if (i2c_dev->bus_clk_rate > I2C_FAST_MODE &&
1601 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE)
1602 i2c_dev->clk_divisor_non_hs_mode =
1603 i2c_dev->hw->clk_divisor_fast_plus_mode;
1604 else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
1605 i2c_dev->bus_clk_rate <= I2C_FAST_MODE)
1606 i2c_dev->clk_divisor_non_hs_mode =
1607 i2c_dev->hw->clk_divisor_fast_mode;
1608 else
1609 i2c_dev->clk_divisor_non_hs_mode =
1610 i2c_dev->hw->clk_divisor_std_mode;
1611
1612 ret = clk_prepare(i2c_dev->div_clk);
1613 if (ret < 0) {
1614 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1615 goto unprepare_fast_clk;
1616 }
1617
1618 pm_runtime_enable(&pdev->dev);
1619 if (!pm_runtime_enabled(&pdev->dev)) {
1620 ret = tegra_i2c_runtime_resume(&pdev->dev);
1621 if (ret < 0) {
1622 dev_err(&pdev->dev, "runtime resume failed\n");
1623 goto unprepare_div_clk;
1624 }
1625 }
1626
1627 if (i2c_dev->is_multimaster_mode) {
1628 ret = clk_enable(i2c_dev->div_clk);
1629 if (ret < 0) {
1630 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1631 ret);
1632 goto disable_rpm;
1633 }
1634 }
1635
1636 if (i2c_dev->hw->supports_bus_clear)
1637 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1638
1639 ret = tegra_i2c_init_dma(i2c_dev);
1640 if (ret < 0)
1641 goto disable_div_clk;
1642
1643 ret = tegra_i2c_init(i2c_dev, false);
1644 if (ret) {
1645 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1646 goto release_dma;
1647 }
1648
1649 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1650 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1651 if (ret) {
1652 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1653 goto release_dma;
1654 }
1655
1656 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1657 i2c_dev->adapter.owner = THIS_MODULE;
1658 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1659 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1660 sizeof(i2c_dev->adapter.name));
1661 i2c_dev->adapter.dev.parent = &pdev->dev;
1662 i2c_dev->adapter.nr = pdev->id;
1663 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1664
1665 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1666 if (ret)
1667 goto release_dma;
1668
1669 return 0;
1670
1671release_dma:
1672 tegra_i2c_release_dma(i2c_dev);
1673
1674disable_div_clk:
1675 if (i2c_dev->is_multimaster_mode)
1676 clk_disable(i2c_dev->div_clk);
1677
1678disable_rpm:
1679 pm_runtime_disable(&pdev->dev);
1680 if (!pm_runtime_status_suspended(&pdev->dev))
1681 tegra_i2c_runtime_suspend(&pdev->dev);
1682
1683unprepare_div_clk:
1684 clk_unprepare(i2c_dev->div_clk);
1685
1686unprepare_fast_clk:
1687 if (!i2c_dev->hw->has_single_clk_source)
1688 clk_unprepare(i2c_dev->fast_clk);
1689
1690 return ret;
1691}
1692
1693static int tegra_i2c_remove(struct platform_device *pdev)
1694{
1695 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1696
1697 i2c_del_adapter(&i2c_dev->adapter);
1698
1699 if (i2c_dev->is_multimaster_mode)
1700 clk_disable(i2c_dev->div_clk);
1701
1702 pm_runtime_disable(&pdev->dev);
1703 if (!pm_runtime_status_suspended(&pdev->dev))
1704 tegra_i2c_runtime_suspend(&pdev->dev);
1705
1706 clk_unprepare(i2c_dev->div_clk);
1707 if (!i2c_dev->hw->has_single_clk_source)
1708 clk_unprepare(i2c_dev->fast_clk);
1709
1710 tegra_i2c_release_dma(i2c_dev);
1711 return 0;
1712}
1713
1714#ifdef CONFIG_PM_SLEEP
1715static int tegra_i2c_suspend(struct device *dev)
1716{
1717 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1718
1719 i2c_mark_adapter_suspended(&i2c_dev->adapter);
1720
1721 return 0;
1722}
1723
1724static int tegra_i2c_resume(struct device *dev)
1725{
1726 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1727 int err;
1728
1729 err = tegra_i2c_init(i2c_dev, false);
1730 if (err)
1731 return err;
1732
1733 i2c_mark_adapter_resumed(&i2c_dev->adapter);
1734
1735 return 0;
1736}
1737
1738static const struct dev_pm_ops tegra_i2c_pm = {
1739 SET_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1740 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1741 NULL)
1742};
1743
1744#define TEGRA_I2C_PM (&tegra_i2c_pm)
1745#else
1746#define TEGRA_I2C_PM NULL
1747#endif
1748
1749static struct platform_driver tegra_i2c_driver = {
1750 .probe = tegra_i2c_probe,
1751 .remove = tegra_i2c_remove,
1752 .driver = {
1753 .name = "tegra-i2c",
1754 .of_match_table = tegra_i2c_of_match,
1755 .pm = TEGRA_I2C_PM,
1756 },
1757};
1758
1759module_platform_driver(tegra_i2c_driver);
1760
1761MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1762MODULE_AUTHOR("Colin Cross");
1763MODULE_LICENSE("GPL v2");
1764