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12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdesc.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/regulator/consumer.h>
21#include <linux/slab.h>
22
23#include "stm32-adc-core.h"
24
25
26#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
27#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
28
29
30#define STM32F4_EOC3 BIT(17)
31#define STM32F4_EOC2 BIT(9)
32#define STM32F4_EOC1 BIT(1)
33
34
35#define STM32F4_ADC_ADCPRE_SHIFT 16
36#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
37
38
39#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
40#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
41
42
43#define STM32H7_EOC_SLV BIT(18)
44#define STM32H7_EOC_MST BIT(2)
45
46
47#define STM32H7_PRESC_SHIFT 18
48#define STM32H7_PRESC_MASK GENMASK(21, 18)
49#define STM32H7_CKMODE_SHIFT 16
50#define STM32H7_CKMODE_MASK GENMASK(17, 16)
51
52#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
53
54
55
56
57
58
59
60
61
62struct stm32_adc_common_regs {
63 u32 csr;
64 u32 ccr;
65 u32 eoc1_msk;
66 u32 eoc2_msk;
67 u32 eoc3_msk;
68};
69
70struct stm32_adc_priv;
71
72
73
74
75
76
77
78struct stm32_adc_priv_cfg {
79 const struct stm32_adc_common_regs *regs;
80 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
81 u32 max_clk_rate_hz;
82};
83
84
85
86
87
88
89
90
91
92
93
94
95
96struct stm32_adc_priv {
97 int irq[STM32_ADC_MAX_ADCS];
98 struct irq_domain *domain;
99 struct clk *aclk;
100 struct clk *bclk;
101 struct regulator *vdda;
102 struct regulator *vref;
103 const struct stm32_adc_priv_cfg *cfg;
104 struct stm32_adc_common common;
105 u32 ccr_bak;
106};
107
108static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
109{
110 return container_of(com, struct stm32_adc_priv, common);
111}
112
113
114static int stm32f4_pclk_div[] = {2, 4, 6, 8};
115
116
117
118
119
120
121static int stm32f4_adc_clk_sel(struct platform_device *pdev,
122 struct stm32_adc_priv *priv)
123{
124 unsigned long rate;
125 u32 val;
126 int i;
127
128
129 if (!priv->aclk) {
130 dev_err(&pdev->dev, "No 'adc' clock found\n");
131 return -ENOENT;
132 }
133
134 rate = clk_get_rate(priv->aclk);
135 if (!rate) {
136 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
137 return -EINVAL;
138 }
139
140 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
141 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
142 break;
143 }
144 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
145 dev_err(&pdev->dev, "adc clk selection failed\n");
146 return -EINVAL;
147 }
148
149 priv->common.rate = rate / stm32f4_pclk_div[i];
150 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
151 val &= ~STM32F4_ADC_ADCPRE_MASK;
152 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
153 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
154
155 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
156 priv->common.rate / 1000);
157
158 return 0;
159}
160
161
162
163
164
165
166
167struct stm32h7_adc_ck_spec {
168 u32 ckmode;
169 u32 presc;
170 int div;
171};
172
173static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
174
175 { 0, 0, 1 },
176 { 0, 1, 2 },
177 { 0, 2, 4 },
178 { 0, 3, 6 },
179 { 0, 4, 8 },
180 { 0, 5, 10 },
181 { 0, 6, 12 },
182 { 0, 7, 16 },
183 { 0, 8, 32 },
184 { 0, 9, 64 },
185 { 0, 10, 128 },
186 { 0, 11, 256 },
187
188 { 1, 0, 1 },
189 { 2, 0, 2 },
190 { 3, 0, 4 },
191};
192
193static int stm32h7_adc_clk_sel(struct platform_device *pdev,
194 struct stm32_adc_priv *priv)
195{
196 u32 ckmode, presc, val;
197 unsigned long rate;
198 int i, div;
199
200
201 if (!priv->bclk) {
202 dev_err(&pdev->dev, "No 'bus' clock found\n");
203 return -ENOENT;
204 }
205
206
207
208
209
210
211 if (priv->aclk) {
212
213
214
215
216 rate = clk_get_rate(priv->aclk);
217 if (!rate) {
218 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
219 return -EINVAL;
220 }
221
222 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
223 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
224 presc = stm32h7_adc_ckmodes_spec[i].presc;
225 div = stm32h7_adc_ckmodes_spec[i].div;
226
227 if (ckmode)
228 continue;
229
230 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
231 goto out;
232 }
233 }
234
235
236 rate = clk_get_rate(priv->bclk);
237 if (!rate) {
238 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
239 return -EINVAL;
240 }
241
242 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
243 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
244 presc = stm32h7_adc_ckmodes_spec[i].presc;
245 div = stm32h7_adc_ckmodes_spec[i].div;
246
247 if (!ckmode)
248 continue;
249
250 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
251 goto out;
252 }
253
254 dev_err(&pdev->dev, "adc clk selection failed\n");
255 return -EINVAL;
256
257out:
258
259 priv->common.rate = rate / div;
260
261
262 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
263 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
264 val |= ckmode << STM32H7_CKMODE_SHIFT;
265 val |= presc << STM32H7_PRESC_SHIFT;
266 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
267
268 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
269 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
270
271 return 0;
272}
273
274
275static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
276 .csr = STM32F4_ADC_CSR,
277 .ccr = STM32F4_ADC_CCR,
278 .eoc1_msk = STM32F4_EOC1,
279 .eoc2_msk = STM32F4_EOC2,
280 .eoc3_msk = STM32F4_EOC3,
281};
282
283
284static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
285 .csr = STM32H7_ADC_CSR,
286 .ccr = STM32H7_ADC_CCR,
287 .eoc1_msk = STM32H7_EOC_MST,
288 .eoc2_msk = STM32H7_EOC_SLV,
289};
290
291
292static void stm32_adc_irq_handler(struct irq_desc *desc)
293{
294 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
295 struct irq_chip *chip = irq_desc_get_chip(desc);
296 u32 status;
297
298 chained_irq_enter(chip, desc);
299 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
300
301 if (status & priv->cfg->regs->eoc1_msk)
302 generic_handle_irq(irq_find_mapping(priv->domain, 0));
303
304 if (status & priv->cfg->regs->eoc2_msk)
305 generic_handle_irq(irq_find_mapping(priv->domain, 1));
306
307 if (status & priv->cfg->regs->eoc3_msk)
308 generic_handle_irq(irq_find_mapping(priv->domain, 2));
309
310 chained_irq_exit(chip, desc);
311};
312
313static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
314 irq_hw_number_t hwirq)
315{
316 irq_set_chip_data(irq, d->host_data);
317 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
318
319 return 0;
320}
321
322static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
323{
324 irq_set_chip_and_handler(irq, NULL, NULL);
325 irq_set_chip_data(irq, NULL);
326}
327
328static const struct irq_domain_ops stm32_adc_domain_ops = {
329 .map = stm32_adc_domain_map,
330 .unmap = stm32_adc_domain_unmap,
331 .xlate = irq_domain_xlate_onecell,
332};
333
334static int stm32_adc_irq_probe(struct platform_device *pdev,
335 struct stm32_adc_priv *priv)
336{
337 struct device_node *np = pdev->dev.of_node;
338 unsigned int i;
339
340 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
341 priv->irq[i] = platform_get_irq(pdev, i);
342 if (priv->irq[i] < 0) {
343
344
345
346
347
348
349
350 if (i && priv->irq[i] == -ENXIO)
351 continue;
352 dev_err(&pdev->dev, "failed to get irq\n");
353
354 return priv->irq[i];
355 }
356 }
357
358 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
359 &stm32_adc_domain_ops,
360 priv);
361 if (!priv->domain) {
362 dev_err(&pdev->dev, "Failed to add irq domain\n");
363 return -ENOMEM;
364 }
365
366 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
367 if (priv->irq[i] < 0)
368 continue;
369 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
370 irq_set_handler_data(priv->irq[i], priv);
371 }
372
373 return 0;
374}
375
376static void stm32_adc_irq_remove(struct platform_device *pdev,
377 struct stm32_adc_priv *priv)
378{
379 int hwirq;
380 unsigned int i;
381
382 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
383 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
384 irq_domain_remove(priv->domain);
385
386 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
387 if (priv->irq[i] < 0)
388 continue;
389 irq_set_chained_handler(priv->irq[i], NULL);
390 }
391}
392
393static int stm32_adc_core_hw_start(struct device *dev)
394{
395 struct stm32_adc_common *common = dev_get_drvdata(dev);
396 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
397 int ret;
398
399 ret = regulator_enable(priv->vdda);
400 if (ret < 0) {
401 dev_err(dev, "vdda enable failed %d\n", ret);
402 return ret;
403 }
404
405 ret = regulator_enable(priv->vref);
406 if (ret < 0) {
407 dev_err(dev, "vref enable failed\n");
408 goto err_vdda_disable;
409 }
410
411 if (priv->bclk) {
412 ret = clk_prepare_enable(priv->bclk);
413 if (ret < 0) {
414 dev_err(dev, "bus clk enable failed\n");
415 goto err_regulator_disable;
416 }
417 }
418
419 if (priv->aclk) {
420 ret = clk_prepare_enable(priv->aclk);
421 if (ret < 0) {
422 dev_err(dev, "adc clk enable failed\n");
423 goto err_bclk_disable;
424 }
425 }
426
427 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
428
429 return 0;
430
431err_bclk_disable:
432 if (priv->bclk)
433 clk_disable_unprepare(priv->bclk);
434err_regulator_disable:
435 regulator_disable(priv->vref);
436err_vdda_disable:
437 regulator_disable(priv->vdda);
438
439 return ret;
440}
441
442static void stm32_adc_core_hw_stop(struct device *dev)
443{
444 struct stm32_adc_common *common = dev_get_drvdata(dev);
445 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
446
447
448 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
449 if (priv->aclk)
450 clk_disable_unprepare(priv->aclk);
451 if (priv->bclk)
452 clk_disable_unprepare(priv->bclk);
453 regulator_disable(priv->vref);
454 regulator_disable(priv->vdda);
455}
456
457static int stm32_adc_probe(struct platform_device *pdev)
458{
459 struct stm32_adc_priv *priv;
460 struct device *dev = &pdev->dev;
461 struct device_node *np = pdev->dev.of_node;
462 struct resource *res;
463 int ret;
464
465 if (!pdev->dev.of_node)
466 return -ENODEV;
467
468 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
469 if (!priv)
470 return -ENOMEM;
471 platform_set_drvdata(pdev, &priv->common);
472
473 priv->cfg = (const struct stm32_adc_priv_cfg *)
474 of_match_device(dev->driver->of_match_table, dev)->data;
475
476 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
478 if (IS_ERR(priv->common.base))
479 return PTR_ERR(priv->common.base);
480 priv->common.phys_base = res->start;
481
482 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
483 if (IS_ERR(priv->vdda)) {
484 ret = PTR_ERR(priv->vdda);
485 if (ret != -EPROBE_DEFER)
486 dev_err(&pdev->dev, "vdda get failed, %d\n", ret);
487 return ret;
488 }
489
490 priv->vref = devm_regulator_get(&pdev->dev, "vref");
491 if (IS_ERR(priv->vref)) {
492 ret = PTR_ERR(priv->vref);
493 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
494 return ret;
495 }
496
497 priv->aclk = devm_clk_get(&pdev->dev, "adc");
498 if (IS_ERR(priv->aclk)) {
499 ret = PTR_ERR(priv->aclk);
500 if (ret != -ENOENT) {
501 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
502 return ret;
503 }
504 priv->aclk = NULL;
505 }
506
507 priv->bclk = devm_clk_get(&pdev->dev, "bus");
508 if (IS_ERR(priv->bclk)) {
509 ret = PTR_ERR(priv->bclk);
510 if (ret != -ENOENT) {
511 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
512 return ret;
513 }
514 priv->bclk = NULL;
515 }
516
517 pm_runtime_get_noresume(dev);
518 pm_runtime_set_active(dev);
519 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
520 pm_runtime_use_autosuspend(dev);
521 pm_runtime_enable(dev);
522
523 ret = stm32_adc_core_hw_start(dev);
524 if (ret)
525 goto err_pm_stop;
526
527 ret = regulator_get_voltage(priv->vref);
528 if (ret < 0) {
529 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
530 goto err_hw_stop;
531 }
532 priv->common.vref_mv = ret / 1000;
533 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
534
535 ret = priv->cfg->clk_sel(pdev, priv);
536 if (ret < 0)
537 goto err_hw_stop;
538
539 ret = stm32_adc_irq_probe(pdev, priv);
540 if (ret < 0)
541 goto err_hw_stop;
542
543 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
544 if (ret < 0) {
545 dev_err(&pdev->dev, "failed to populate DT children\n");
546 goto err_irq_remove;
547 }
548
549 pm_runtime_mark_last_busy(dev);
550 pm_runtime_put_autosuspend(dev);
551
552 return 0;
553
554err_irq_remove:
555 stm32_adc_irq_remove(pdev, priv);
556err_hw_stop:
557 stm32_adc_core_hw_stop(dev);
558err_pm_stop:
559 pm_runtime_disable(dev);
560 pm_runtime_set_suspended(dev);
561 pm_runtime_put_noidle(dev);
562
563 return ret;
564}
565
566static int stm32_adc_remove(struct platform_device *pdev)
567{
568 struct stm32_adc_common *common = platform_get_drvdata(pdev);
569 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
570
571 pm_runtime_get_sync(&pdev->dev);
572 of_platform_depopulate(&pdev->dev);
573 stm32_adc_irq_remove(pdev, priv);
574 stm32_adc_core_hw_stop(&pdev->dev);
575 pm_runtime_disable(&pdev->dev);
576 pm_runtime_set_suspended(&pdev->dev);
577 pm_runtime_put_noidle(&pdev->dev);
578
579 return 0;
580}
581
582#if defined(CONFIG_PM)
583static int stm32_adc_core_runtime_suspend(struct device *dev)
584{
585 stm32_adc_core_hw_stop(dev);
586
587 return 0;
588}
589
590static int stm32_adc_core_runtime_resume(struct device *dev)
591{
592 return stm32_adc_core_hw_start(dev);
593}
594#endif
595
596static const struct dev_pm_ops stm32_adc_core_pm_ops = {
597 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
598 pm_runtime_force_resume)
599 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
600 stm32_adc_core_runtime_resume,
601 NULL)
602};
603
604static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
605 .regs = &stm32f4_adc_common_regs,
606 .clk_sel = stm32f4_adc_clk_sel,
607 .max_clk_rate_hz = 36000000,
608};
609
610static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
611 .regs = &stm32h7_adc_common_regs,
612 .clk_sel = stm32h7_adc_clk_sel,
613 .max_clk_rate_hz = 36000000,
614};
615
616static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
617 .regs = &stm32h7_adc_common_regs,
618 .clk_sel = stm32h7_adc_clk_sel,
619 .max_clk_rate_hz = 40000000,
620};
621
622static const struct of_device_id stm32_adc_of_match[] = {
623 {
624 .compatible = "st,stm32f4-adc-core",
625 .data = (void *)&stm32f4_adc_priv_cfg
626 }, {
627 .compatible = "st,stm32h7-adc-core",
628 .data = (void *)&stm32h7_adc_priv_cfg
629 }, {
630 .compatible = "st,stm32mp1-adc-core",
631 .data = (void *)&stm32mp1_adc_priv_cfg
632 }, {
633 },
634};
635MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
636
637static struct platform_driver stm32_adc_driver = {
638 .probe = stm32_adc_probe,
639 .remove = stm32_adc_remove,
640 .driver = {
641 .name = "stm32-adc-core",
642 .of_match_table = stm32_adc_of_match,
643 .pm = &stm32_adc_core_pm_ops,
644 },
645};
646module_platform_driver(stm32_adc_driver);
647
648MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
649MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
650MODULE_LICENSE("GPL v2");
651MODULE_ALIAS("platform:stm32-adc-core");
652