LXR linux/drivers/iio/imu/inv_mpu6050/inv_mpu

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3* Copyright (C) 2012 Invensense, Inc.
   4*/
   5#include <linux/i2c.h>
   6#include <linux/i2c-mux.h>
   7#include <linux/mutex.h>
   8#include <linux/iio/iio.h>
   9#include <linux/iio/buffer.h>
  10#include <linux/regmap.h>
  11#include <linux/iio/sysfs.h>
  12#include <linux/iio/kfifo_buf.h>
  13#include <linux/iio/trigger.h>
  14#include <linux/iio/triggered_buffer.h>
  15#include <linux/iio/trigger_consumer.h>
  16#include <linux/platform_data/invensense_mpu6050.h>
  17
  18/**
  19 *  struct inv_mpu6050_reg_map - Notable registers.
  20 *  @sample_rate_div:   Divider applied to gyro output rate.
  21 *  @lpf:               Configures internal low pass filter.
  22 *  @accel_lpf:         Configures accelerometer low pass filter.
  23 *  @user_ctrl:         Enables/resets the FIFO.
  24 *  @fifo_en:           Determines which data will appear in FIFO.
  25 *  @gyro_config:       gyro config register.
  26 *  @accl_config:       accel config register
  27 *  @fifo_count_h:      Upper byte of FIFO count.
  28 *  @fifo_r_w:          FIFO register.
  29 *  @raw_gyro:          Address of first gyro register.
  30 *  @raw_accl:          Address of first accel register.
  31 *  @temperature:       temperature register
  32 *  @int_enable:        Interrupt enable register.
  33 *  @int_status:        Interrupt status register.
  34 *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  35 *  @pwr_mgmt_2:        Controls power state of individual sensors.
  36 *  @int_pin_cfg;       Controls interrupt pin configuration.
  37 *  @accl_offset:       Controls the accelerometer calibration offset.
  38 *  @gyro_offset:       Controls the gyroscope calibration offset.
  39 *  @i2c_if:            Controls the i2c interface
  40 */
  41struct inv_mpu6050_reg_map {
  42        u8 sample_rate_div;
  43        u8 lpf;
  44        u8 accel_lpf;
  45        u8 user_ctrl;
  46        u8 fifo_en;
  47        u8 gyro_config;
  48        u8 accl_config;
  49        u8 fifo_count_h;
  50        u8 fifo_r_w;
  51        u8 raw_gyro;
  52        u8 raw_accl;
  53        u8 temperature;
  54        u8 int_enable;
  55        u8 int_status;
  56        u8 pwr_mgmt_1;
  57        u8 pwr_mgmt_2;
  58        u8 int_pin_cfg;
  59        u8 accl_offset;
  60        u8 gyro_offset;
  61        u8 i2c_if;
  62};
  63
  64/*device enum */
  65enum inv_devices {
  66        INV_MPU6050,
  67        INV_MPU6500,
  68        INV_MPU6515,
  69        INV_MPU6000,
  70        INV_MPU9150,
  71        INV_MPU9250,
  72        INV_MPU9255,
  73        INV_ICM20608,
  74        INV_ICM20602,
  75        INV_NUM_PARTS
  76};
  77
  78/**
  79 *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  80 *  @fsr:               Full scale range.
  81 *  @lpf:               Digital low pass filter frequency.
  82 *  @accl_fs:           accel full scale range.
  83 *  @accl_fifo_enable:  enable accel data output
  84 *  @gyro_fifo_enable:  enable gyro data output
  85 *  @divider:           chip sample rate divider (sample rate divider - 1)
  86 */
  87struct inv_mpu6050_chip_config {
  88        unsigned int fsr:2;
  89        unsigned int lpf:3;
  90        unsigned int accl_fs:2;
  91        unsigned int accl_fifo_enable:1;
  92        unsigned int gyro_fifo_enable:1;
  93        u8 divider;
  94        u8 user_ctrl;
  95};
  96
  97/**
  98 *  struct inv_mpu6050_hw - Other important hardware information.
  99 *  @whoami:    Self identification byte from WHO_AM_I register
 100 *  @name:      name of the chip.
 101 *  @reg:   register map of the chip.
 102 *  @config:    configuration of the chip.
 103 */
 104struct inv_mpu6050_hw {
 105        u8 whoami;
 106        u8 *name;
 107        const struct inv_mpu6050_reg_map *reg;
 108        const struct inv_mpu6050_chip_config *config;
 109};
 110
 111/*
 112 *  struct inv_mpu6050_state - Driver state variables.
 113 *  @lock:              Chip access lock.
 114 *  @trig:              IIO trigger.
 115 *  @chip_config:       Cached attribute information.
 116 *  @reg:               Map of important registers.
 117 *  @hw:                Other hardware-specific information.
 118 *  @chip_type:         chip type.
 119 *  @plat_data:         platform data (deprecated in favor of @orientation).
 120 *  @orientation:       sensor chip orientation relative to main hardware.
 121 *  @map                regmap pointer.
 122 *  @irq                interrupt number.
 123 *  @irq_mask           the int_pin_cfg mask to configure interrupt type.
 124 *  @chip_period:       chip internal period estimation (~1kHz).
 125 *  @it_timestamp:      timestamp from previous interrupt.
 126 *  @data_timestamp:    timestamp for next data sample.
 127 *  @vddio_supply       voltage regulator for the chip.
 128 */
 129struct inv_mpu6050_state {
 130        struct mutex lock;
 131        struct iio_trigger  *trig;
 132        struct inv_mpu6050_chip_config chip_config;
 133        const struct inv_mpu6050_reg_map *reg;
 134        const struct inv_mpu6050_hw *hw;
 135        enum   inv_devices chip_type;
 136        struct i2c_mux_core *muxc;
 137        struct i2c_client *mux_client;
 138        unsigned int powerup_count;
 139        struct inv_mpu6050_platform_data plat_data;
 140        struct iio_mount_matrix orientation;
 141        struct regmap *map;
 142        int irq;
 143        u8 irq_mask;
 144        unsigned skip_samples;
 145        s64 chip_period;
 146        s64 it_timestamp;
 147        s64 data_timestamp;
 148        struct regulator *vddio_supply;
 149};
 150
 151/*register and associated bit definition*/
 152#define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 153#define INV_MPU6050_REG_GYRO_OFFSET         0x13
 154
 155#define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 156#define INV_MPU6050_REG_CONFIG              0x1A
 157#define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 158#define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 159
 160#define INV_MPU6050_REG_FIFO_EN             0x23
 161#define INV_MPU6050_BIT_ACCEL_OUT           0x08
 162#define INV_MPU6050_BITS_GYRO_OUT           0x70
 163
 164#define INV_MPU6050_REG_INT_ENABLE          0x38
 165#define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 166#define INV_MPU6050_BIT_DMP_INT_EN          0x02
 167
 168#define INV_MPU6050_REG_RAW_ACCEL           0x3B
 169#define INV_MPU6050_REG_TEMPERATURE         0x41
 170#define INV_MPU6050_REG_RAW_GYRO            0x43
 171
 172#define INV_MPU6050_REG_INT_STATUS          0x3A
 173#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
 174#define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
 175
 176#define INV_MPU6050_REG_USER_CTRL           0x6A
 177#define INV_MPU6050_BIT_FIFO_RST            0x04
 178#define INV_MPU6050_BIT_DMP_RST             0x08
 179#define INV_MPU6050_BIT_I2C_MST_EN          0x20
 180#define INV_MPU6050_BIT_FIFO_EN             0x40
 181#define INV_MPU6050_BIT_DMP_EN              0x80
 182#define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 183
 184#define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 185#define INV_MPU6050_BIT_H_RESET             0x80
 186#define INV_MPU6050_BIT_SLEEP               0x40
 187#define INV_MPU6050_BIT_CLK_MASK            0x7
 188
 189#define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 190#define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 191#define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 192
 193/* ICM20602 register */
 194#define INV_ICM20602_REG_I2C_IF             0x70
 195#define INV_ICM20602_BIT_I2C_IF_DIS         0x40
 196
 197#define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 198#define INV_MPU6050_REG_FIFO_R_W            0x74
 199
 200#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 201#define INV_MPU6050_FIFO_COUNT_BYTE          2
 202
 203/* ICM20602 FIFO samples include temperature readings */
 204#define INV_ICM20602_BYTES_PER_TEMP_SENSOR   2
 205
 206/* mpu6500 registers */
 207#define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 208#define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 209
 210/* delay time in milliseconds */
 211#define INV_MPU6050_POWER_UP_TIME            100
 212#define INV_MPU6050_TEMP_UP_TIME             100
 213#define INV_MPU6050_SENSOR_UP_TIME           30
 214
 215/* delay time in microseconds */
 216#define INV_MPU6050_REG_UP_TIME_MIN          5000
 217#define INV_MPU6050_REG_UP_TIME_MAX          10000
 218
 219#define INV_MPU6050_TEMP_OFFSET              12421
 220#define INV_MPU6050_TEMP_SCALE               2941
 221#define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 222#define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 223#define INV_MPU6050_THREE_AXIS               3
 224#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 225#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 226
 227#define INV_ICM20602_TEMP_OFFSET             8170
 228#define INV_ICM20602_TEMP_SCALE              3060
 229
 230/* 6 + 6 round up and plus 8 */
 231#define INV_MPU6050_OUTPUT_DATA_SIZE         24
 232
 233#define INV_MPU6050_REG_INT_PIN_CFG     0x37
 234#define INV_MPU6050_ACTIVE_HIGH         0x00
 235#define INV_MPU6050_ACTIVE_LOW          0x80
 236/* enable level triggering */
 237#define INV_MPU6050_LATCH_INT_EN        0x20
 238#define INV_MPU6050_BIT_BYPASS_EN       0x2
 239
 240/* Allowed timestamp period jitter in percent */
 241#define INV_MPU6050_TS_PERIOD_JITTER    4
 242
 243/* init parameters */
 244#define INV_MPU6050_INIT_FIFO_RATE           50
 245#define INV_MPU6050_MAX_FIFO_RATE            1000
 246#define INV_MPU6050_MIN_FIFO_RATE            4
 247
 248/* chip internal frequency: 1KHz */
 249#define INV_MPU6050_INTERNAL_FREQ_HZ            1000
 250/* return the frequency divider (chip sample rate divider + 1) */
 251#define INV_MPU6050_FREQ_DIVIDER(st)                                    \
 252        ((st)->chip_config.divider + 1)
 253/* chip sample rate divider to fifo rate */
 254#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)                     \
 255        ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
 256#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)                       \
 257        (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
 258
 259#define INV_MPU6050_REG_WHOAMI                  117
 260
 261#define INV_MPU6000_WHOAMI_VALUE                0x68
 262#define INV_MPU6050_WHOAMI_VALUE                0x68
 263#define INV_MPU6500_WHOAMI_VALUE                0x70
 264#define INV_MPU9150_WHOAMI_VALUE                0x68
 265#define INV_MPU9250_WHOAMI_VALUE                0x71
 266#define INV_MPU9255_WHOAMI_VALUE                0x73
 267#define INV_MPU6515_WHOAMI_VALUE                0x74
 268#define INV_ICM20608_WHOAMI_VALUE               0xAF
 269#define INV_ICM20602_WHOAMI_VALUE               0x12
 270
 271/* scan element definition for generic MPU6xxx devices */
 272enum inv_mpu6050_scan {
 273        INV_MPU6050_SCAN_ACCL_X,
 274        INV_MPU6050_SCAN_ACCL_Y,
 275        INV_MPU6050_SCAN_ACCL_Z,
 276        INV_MPU6050_SCAN_GYRO_X,
 277        INV_MPU6050_SCAN_GYRO_Y,
 278        INV_MPU6050_SCAN_GYRO_Z,
 279        INV_MPU6050_SCAN_TIMESTAMP,
 280};
 281
 282/* scan element definition for ICM20602, which includes temperature */
 283enum inv_icm20602_scan {
 284        INV_ICM20602_SCAN_ACCL_X,
 285        INV_ICM20602_SCAN_ACCL_Y,
 286        INV_ICM20602_SCAN_ACCL_Z,
 287        INV_ICM20602_SCAN_TEMP,
 288        INV_ICM20602_SCAN_GYRO_X,
 289        INV_ICM20602_SCAN_GYRO_Y,
 290        INV_ICM20602_SCAN_GYRO_Z,
 291        INV_ICM20602_SCAN_TIMESTAMP,
 292};
 293
 294enum inv_mpu6050_filter_e {
 295        INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 296        INV_MPU6050_FILTER_188HZ,
 297        INV_MPU6050_FILTER_98HZ,
 298        INV_MPU6050_FILTER_42HZ,
 299        INV_MPU6050_FILTER_20HZ,
 300        INV_MPU6050_FILTER_10HZ,
 301        INV_MPU6050_FILTER_5HZ,
 302        INV_MPU6050_FILTER_2100HZ_NOLPF,
 303        NUM_MPU6050_FILTER
 304};
 305
 306/* IIO attribute address */
 307enum INV_MPU6050_IIO_ATTR_ADDR {
 308        ATTR_GYRO_MATRIX,
 309        ATTR_ACCL_MATRIX,
 310};
 311
 312enum inv_mpu6050_accl_fs_e {
 313        INV_MPU6050_FS_02G = 0,
 314        INV_MPU6050_FS_04G,
 315        INV_MPU6050_FS_08G,
 316        INV_MPU6050_FS_16G,
 317        NUM_ACCL_FSR
 318};
 319
 320enum inv_mpu6050_fsr_e {
 321        INV_MPU6050_FSR_250DPS = 0,
 322        INV_MPU6050_FSR_500DPS,
 323        INV_MPU6050_FSR_1000DPS,
 324        INV_MPU6050_FSR_2000DPS,
 325        NUM_MPU6050_FSR
 326};
 327
 328enum inv_mpu6050_clock_sel_e {
 329        INV_CLK_INTERNAL = 0,
 330        INV_CLK_PLL,
 331        NUM_CLK
 332};
 333
 334irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 335int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
 336int inv_reset_fifo(struct iio_dev *indio_dev);
 337int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 338int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 339int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 340int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 341void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 342int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 343                int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 344extern const struct dev_pm_ops inv_mpu_pmops;
 345