1#ifndef _HFI1_KERNEL_H
2#define _HFI1_KERNEL_H
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50#include <linux/interrupt.h>
51#include <linux/pci.h>
52#include <linux/dma-mapping.h>
53#include <linux/mutex.h>
54#include <linux/list.h>
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/io.h>
58#include <linux/fs.h>
59#include <linux/completion.h>
60#include <linux/kref.h>
61#include <linux/sched.h>
62#include <linux/cdev.h>
63#include <linux/delay.h>
64#include <linux/kthread.h>
65#include <linux/i2c.h>
66#include <linux/i2c-algo-bit.h>
67#include <linux/xarray.h>
68#include <rdma/ib_hdrs.h>
69#include <rdma/opa_addr.h>
70#include <linux/rhashtable.h>
71#include <linux/netdevice.h>
72#include <rdma/rdma_vt.h>
73
74#include "chip_registers.h"
75#include "common.h"
76#include "opfn.h"
77#include "verbs.h"
78#include "pio.h"
79#include "chip.h"
80#include "mad.h"
81#include "qsfp.h"
82#include "platform.h"
83#include "affinity.h"
84#include "msix.h"
85
86
87#define HFI1_CHIP_VERS_MAJ 3U
88
89
90#define HFI1_CHIP_VERS_MIN 0U
91
92
93#define HFI1_OUI 0x001175
94#define HFI1_OUI_LSB 40
95
96#define DROP_PACKET_OFF 0
97#define DROP_PACKET_ON 1
98
99#define NEIGHBOR_TYPE_HFI 0
100#define NEIGHBOR_TYPE_SWITCH 1
101
102#define HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES 5
103
104extern unsigned long hfi1_cap_mask;
105#define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
106#define HFI1_CAP_UGET_MASK(mask, cap) \
107 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
108#define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
109#define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
110#define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
111#define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
112#define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
113 HFI1_CAP_MISC_MASK)
114
115#define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
116
117
118
119
120
121#define HFI1_CTRL_CTXT 0
122
123
124
125
126
127#define NUM_CCE_ERR_STATUS_COUNTERS 41
128#define NUM_RCV_ERR_STATUS_COUNTERS 64
129#define NUM_MISC_ERR_STATUS_COUNTERS 13
130#define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
131#define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
132#define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
133#define NUM_SEND_ERR_STATUS_COUNTERS 3
134#define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
135#define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
136
137
138
139
140
141
142
143
144
145struct hfi1_ib_stats {
146 __u64 sps_ints;
147 __u64 sps_errints;
148 __u64 sps_txerrs;
149 __u64 sps_rcverrs;
150 __u64 sps_hwerrs;
151 __u64 sps_nopiobufs;
152 __u64 sps_ctxts;
153 __u64 sps_lenerrs;
154 __u64 sps_buffull;
155 __u64 sps_hdrfull;
156};
157
158extern struct hfi1_ib_stats hfi1_stats;
159extern const struct pci_error_handlers hfi1_pci_err_handler;
160
161extern int num_driver_cntrs;
162
163
164
165
166
167
168
169#define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
170
171
172
173
174
175struct hfi1_opcode_stats_perctx;
176
177struct ctxt_eager_bufs {
178 struct eager_buffer {
179 void *addr;
180 dma_addr_t dma;
181 ssize_t len;
182 } *buffers;
183 struct {
184 void *addr;
185 dma_addr_t dma;
186 } *rcvtids;
187 u32 size;
188 u32 rcvtid_size;
189 u16 count;
190 u16 numbufs;
191 u16 alloced;
192 u16 threshold;
193};
194
195struct exp_tid_set {
196 struct list_head list;
197 u32 count;
198};
199
200typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
201
202struct tid_queue {
203 struct list_head queue_head;
204
205 u32 enqueue;
206 u32 dequeue;
207};
208
209struct hfi1_ctxtdata {
210
211 void *rcvhdrq;
212
213 volatile __le64 *rcvhdrtail_kvaddr;
214
215 struct hfi1_pportdata *ppd;
216
217 struct hfi1_devdata *dd;
218
219 struct send_context *sc;
220
221 const rhf_rcv_function_ptr *rhf_rcv_function_map;
222
223
224
225
226
227
228
229 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
230
231 struct hfi1_opcode_stats_perctx *opstats;
232
233 u64 imask;
234
235 u32 head;
236
237 u16 rcvhdrq_cnt;
238 u8 ireg;
239
240 u8 seq_cnt;
241
242 u8 rcvhdrqentsize;
243
244 u8 rhf_offset;
245
246 u8 rcvavail_timeout;
247
248 bool is_vnic;
249
250 u8 vnic_q_idx;
251
252 bool aspm_intr_supported;
253
254 bool aspm_enabled;
255
256 bool aspm_intr_enable;
257 struct ctxt_eager_bufs egrbufs;
258
259 struct list_head qp_wait_list;
260
261 struct exp_tid_set tid_group_list;
262 struct exp_tid_set tid_used_list;
263 struct exp_tid_set tid_full_list;
264
265
266 struct timer_list aspm_timer;
267
268 unsigned long flags;
269
270 struct tid_group *groups;
271
272 dma_addr_t rcvhdrq_dma;
273 dma_addr_t rcvhdrqtailaddr_dma;
274
275 ktime_t aspm_ts_last_intr;
276
277 ktime_t aspm_ts_timer_sched;
278
279 spinlock_t aspm_lock;
280
281 struct kref kref;
282
283 int numa_id;
284
285 s16 msix_intr;
286
287 u16 jkey;
288
289 u16 rcv_array_groups;
290
291 u16 eager_base;
292
293 u16 expected_count;
294
295 u16 expected_base;
296
297 u8 ctxt;
298
299
300
301 struct mutex exp_mutex;
302
303 spinlock_t exp_lock;
304
305 struct tid_queue flow_queue;
306
307 struct tid_queue rarr_queue;
308
309 wait_queue_head_t wait;
310
311 u8 uuid[16];
312
313 char comm[TASK_COMM_LEN];
314
315 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
316
317 unsigned long event_flags;
318
319 void *subctxt_uregbase;
320
321 void *subctxt_rcvegrbuf;
322
323 void *subctxt_rcvhdr_base;
324
325 u32 urgent;
326
327 u32 urgent_poll;
328
329 u16 poll_type;
330
331 u16 subctxt_id;
332
333 u32 userversion;
334
335
336
337
338 u8 subctxt_cnt;
339
340
341 unsigned long flow_mask;
342 struct tid_flow_state flows[RXE_NUM_TID_FLOWS];
343};
344
345
346
347
348
349
350
351
352static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd)
353{
354 return PAGE_ALIGN(rcd->rcvhdrq_cnt *
355 rcd->rcvhdrqentsize * sizeof(u32));
356}
357
358
359
360
361
362
363
364
365struct hfi1_packet {
366 void *ebuf;
367 void *hdr;
368 void *payload;
369 struct hfi1_ctxtdata *rcd;
370 __le32 *rhf_addr;
371 struct rvt_qp *qp;
372 struct ib_other_headers *ohdr;
373 struct ib_grh *grh;
374 struct opa_16b_mgmt *mgmt;
375 u64 rhf;
376 u32 maxcnt;
377 u32 rhqoff;
378 u32 dlid;
379 u32 slid;
380 u16 tlen;
381 s16 etail;
382 u16 pkey;
383 u8 hlen;
384 u8 numpkt;
385 u8 rsize;
386 u8 updegr;
387 u8 etype;
388 u8 extra_byte;
389 u8 pad;
390 u8 sc;
391 u8 sl;
392 u8 opcode;
393 bool migrated;
394};
395
396
397#define HFI1_PKT_TYPE_9B 0
398#define HFI1_PKT_TYPE_16B 1
399
400
401
402
403#define OPA_16B_L4_MASK 0xFFull
404#define OPA_16B_SC_MASK 0x1F00000ull
405#define OPA_16B_SC_SHIFT 20
406#define OPA_16B_LID_MASK 0xFFFFFull
407#define OPA_16B_DLID_MASK 0xF000ull
408#define OPA_16B_DLID_SHIFT 20
409#define OPA_16B_DLID_HIGH_SHIFT 12
410#define OPA_16B_SLID_MASK 0xF00ull
411#define OPA_16B_SLID_SHIFT 20
412#define OPA_16B_SLID_HIGH_SHIFT 8
413#define OPA_16B_BECN_MASK 0x80000000ull
414#define OPA_16B_BECN_SHIFT 31
415#define OPA_16B_FECN_MASK 0x10000000ull
416#define OPA_16B_FECN_SHIFT 28
417#define OPA_16B_L2_MASK 0x60000000ull
418#define OPA_16B_L2_SHIFT 29
419#define OPA_16B_PKEY_MASK 0xFFFF0000ull
420#define OPA_16B_PKEY_SHIFT 16
421#define OPA_16B_LEN_MASK 0x7FF00000ull
422#define OPA_16B_LEN_SHIFT 20
423#define OPA_16B_RC_MASK 0xE000000ull
424#define OPA_16B_RC_SHIFT 25
425#define OPA_16B_AGE_MASK 0xFF0000ull
426#define OPA_16B_AGE_SHIFT 16
427#define OPA_16B_ENTROPY_MASK 0xFFFFull
428
429
430
431
432#define OPA_16B_L4_9B 0x00
433#define OPA_16B_L2_TYPE 0x02
434#define OPA_16B_L4_FM 0x08
435#define OPA_16B_L4_IB_LOCAL 0x09
436#define OPA_16B_L4_IB_GLOBAL 0x0A
437#define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
438
439
440
441
442#define OPA_16B_L4_FM_PAD 3
443#define OPA_16B_L4_FM_HLEN 24
444
445static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
446{
447 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
448}
449
450static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
451{
452 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
453}
454
455static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
456{
457 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
458 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
459 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
460}
461
462static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
463{
464 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
465 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
466 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
467}
468
469static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
470{
471 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
472}
473
474static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
475{
476 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
477}
478
479static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
480{
481 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
482}
483
484static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
485{
486 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
487}
488
489static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
490{
491 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
492}
493
494static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
495{
496 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
497}
498
499static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
500{
501 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
502}
503
504static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
505{
506 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
507}
508
509#define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
510
511
512
513
514#define OPA_16B_BTH_PAD_MASK 7
515static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
516{
517 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
518 OPA_16B_BTH_PAD_MASK);
519}
520
521
522
523
524#define OPA_16B_MGMT_QPN_MASK 0xFFFFFF
525static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
526{
527 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
528}
529
530static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
531{
532 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
533}
534
535static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
536 u32 dest_qp, u32 src_qp)
537{
538 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
539 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
540}
541
542
543
544
545
546static inline struct ib_other_headers *
547hfi1_get_rc_ohdr(struct hfi1_opa_header *opah)
548{
549 struct ib_other_headers *ohdr;
550 struct ib_header *hdr = NULL;
551 struct hfi1_16b_header *hdr_16b = NULL;
552
553
554 if (opah->hdr_type == HFI1_PKT_TYPE_9B) {
555 hdr = &opah->ibh;
556 if (ib_get_lnh(hdr) == HFI1_LRH_BTH)
557 ohdr = &hdr->u.oth;
558 else
559 ohdr = &hdr->u.l.oth;
560 } else {
561 u8 l4;
562
563 hdr_16b = &opah->opah;
564 l4 = hfi1_16B_get_l4(hdr_16b);
565 if (l4 == OPA_16B_L4_IB_LOCAL)
566 ohdr = &hdr_16b->u.oth;
567 else
568 ohdr = &hdr_16b->u.l.oth;
569 }
570 return ohdr;
571}
572
573struct rvt_sge_state;
574
575
576
577
578
579
580#define HFI1_IB_CFG_LIDLMC 0
581#define HFI1_IB_CFG_LWID_DG_ENB 1
582#define HFI1_IB_CFG_LWID_ENB 2
583#define HFI1_IB_CFG_LWID 3
584#define HFI1_IB_CFG_SPD_ENB 4
585#define HFI1_IB_CFG_SPD 5
586#define HFI1_IB_CFG_RXPOL_ENB 6
587#define HFI1_IB_CFG_LREV_ENB 7
588#define HFI1_IB_CFG_LINKLATENCY 8
589#define HFI1_IB_CFG_HRTBT 9
590#define HFI1_IB_CFG_OP_VLS 10
591#define HFI1_IB_CFG_VL_HIGH_CAP 11
592#define HFI1_IB_CFG_VL_LOW_CAP 12
593#define HFI1_IB_CFG_OVERRUN_THRESH 13
594#define HFI1_IB_CFG_PHYERR_THRESH 14
595#define HFI1_IB_CFG_LINKDEFAULT 15
596#define HFI1_IB_CFG_PKEYS 16
597#define HFI1_IB_CFG_MTU 17
598#define HFI1_IB_CFG_VL_HIGH_LIMIT 19
599#define HFI1_IB_CFG_PMA_TICKS 20
600#define HFI1_IB_CFG_PORT 21
601
602
603
604
605
606
607
608
609
610#define __HLS_UP_INIT_BP 0
611#define __HLS_UP_ARMED_BP 1
612#define __HLS_UP_ACTIVE_BP 2
613#define __HLS_DN_DOWNDEF_BP 3
614#define __HLS_DN_POLL_BP 4
615#define __HLS_DN_DISABLE_BP 5
616#define __HLS_DN_OFFLINE_BP 6
617#define __HLS_VERIFY_CAP_BP 7
618#define __HLS_GOING_UP_BP 8
619#define __HLS_GOING_OFFLINE_BP 9
620#define __HLS_LINK_COOLDOWN_BP 10
621
622#define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
623#define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
624#define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
625#define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP)
626#define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
627#define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
628#define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
629#define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
630#define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
631#define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
632#define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
633
634#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
635#define HLS_DOWN ~(HLS_UP)
636
637#define HLS_DEFAULT HLS_DN_POLL
638
639
640#define HFI1_DEFAULT_ACTIVE_MTU 10240
641
642#define HFI1_DEFAULT_MAX_MTU 10240
643
644#define DEFAULT_PKEY 0xffff
645
646
647
648
649#define FM_TBL_VL_HIGH_ARB 1
650#define FM_TBL_VL_LOW_ARB 2
651#define FM_TBL_BUFFER_CONTROL 3
652#define FM_TBL_SC2VLNT 4
653#define FM_TBL_VL_PREEMPT_ELEMS 5
654#define FM_TBL_VL_PREEMPT_MATRIX 6
655
656
657
658
659
660
661#define HFI1_RCVCTRL_TAILUPD_ENB 0x01
662#define HFI1_RCVCTRL_TAILUPD_DIS 0x02
663#define HFI1_RCVCTRL_CTXT_ENB 0x04
664#define HFI1_RCVCTRL_CTXT_DIS 0x08
665#define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
666#define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
667#define HFI1_RCVCTRL_PKEY_ENB 0x40
668#define HFI1_RCVCTRL_PKEY_DIS 0x80
669#define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
670#define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
671#define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
672#define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
673#define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
674#define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
675#define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
676#define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
677#define HFI1_RCVCTRL_URGENT_ENB 0x40000
678#define HFI1_RCVCTRL_URGENT_DIS 0x80000
679
680
681#define HFI1_PART_ENFORCE_IN 0x1
682#define HFI1_PART_ENFORCE_OUT 0x2
683
684
685#define SYNTH_CNT_TIME 3
686
687
688#define CNTR_NORMAL 0x0
689#define CNTR_SYNTH 0x1
690#define CNTR_DISABLED 0x2
691#define CNTR_32BIT 0x4
692#define CNTR_VL 0x8
693#define CNTR_SDMA 0x10
694#define CNTR_INVALID_VL -1
695#define CNTR_MODE_W 0x0
696#define CNTR_MODE_R 0x1
697
698
699#define HFI1_MIN_VLS_SUPPORTED 1
700#define HFI1_MAX_VLS_SUPPORTED 8
701
702#define HFI1_GUIDS_PER_PORT 5
703#define HFI1_PORT_GUID_INDEX 0
704
705static inline void incr_cntr64(u64 *cntr)
706{
707 if (*cntr < (u64)-1LL)
708 (*cntr)++;
709}
710
711static inline void incr_cntr32(u32 *cntr)
712{
713 if (*cntr < (u32)-1LL)
714 (*cntr)++;
715}
716
717#define MAX_NAME_SIZE 64
718struct hfi1_msix_entry {
719 enum irq_type type;
720 int irq;
721 void *arg;
722 cpumask_t mask;
723 struct irq_affinity_notify notify;
724};
725
726struct hfi1_msix_info {
727
728 spinlock_t msix_lock;
729 DECLARE_BITMAP(in_use_msix, CCE_NUM_MSIX_VECTORS);
730 struct hfi1_msix_entry *msix_entries;
731 u16 max_requested;
732};
733
734
735struct cca_timer {
736 struct hrtimer hrtimer;
737 struct hfi1_pportdata *ppd;
738 int sl;
739 u16 ccti;
740};
741
742struct link_down_reason {
743
744
745
746
747 u8 sma;
748 u8 latest;
749};
750
751enum {
752 LO_PRIO_TABLE,
753 HI_PRIO_TABLE,
754 MAX_PRIO_TABLE
755};
756
757struct vl_arb_cache {
758
759 spinlock_t lock;
760 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
761};
762
763
764
765
766
767
768
769struct hfi1_pportdata {
770 struct hfi1_ibport ibport_data;
771
772 struct hfi1_devdata *dd;
773 struct kobject pport_cc_kobj;
774 struct kobject sc2vl_kobj;
775 struct kobject sl2sc_kobj;
776 struct kobject vl2mtu_kobj;
777
778
779 struct qsfp_data qsfp_info;
780
781 u32 port_type;
782 u32 tx_preset_eq;
783 u32 tx_preset_noeq;
784 u32 rx_preset;
785 u8 local_atten;
786 u8 remote_atten;
787 u8 default_atten;
788 u8 max_power_class;
789
790
791 bool config_from_scratch;
792
793
794 u64 guids[HFI1_GUIDS_PER_PORT];
795
796
797 u64 neighbor_guid;
798
799
800 u32 linkup;
801
802
803
804
805
806 u64 *statusp;
807
808
809
810 struct workqueue_struct *hfi1_wq;
811 struct workqueue_struct *link_wq;
812
813
814 struct work_struct link_vc_work;
815 struct work_struct link_up_work;
816 struct work_struct link_down_work;
817 struct work_struct sma_message_work;
818 struct work_struct freeze_work;
819 struct work_struct link_downgrade_work;
820 struct work_struct link_bounce_work;
821 struct delayed_work start_link_work;
822
823 struct mutex hls_lock;
824 u32 host_link_state;
825
826
827
828 u32 ibmtu;
829
830
831
832
833 u32 ibmaxlen;
834 u32 current_egress_rate;
835
836 u32 lid;
837
838 u16 pkeys[MAX_PKEY_VALUES];
839 u16 link_width_supported;
840 u16 link_width_downgrade_supported;
841 u16 link_speed_supported;
842 u16 link_width_enabled;
843 u16 link_width_downgrade_enabled;
844 u16 link_speed_enabled;
845 u16 link_width_active;
846 u16 link_width_downgrade_tx_active;
847 u16 link_width_downgrade_rx_active;
848 u16 link_speed_active;
849 u8 vls_supported;
850 u8 vls_operational;
851 u8 actual_vls_operational;
852
853 u8 lmc;
854
855 u8 rx_pol_inv;
856
857 u8 hw_pidx;
858 u8 port;
859
860 u8 neighbor_type;
861 u8 neighbor_normal;
862 u8 neighbor_fm_security;
863 u8 neighbor_port_number;
864 u8 is_sm_config_started;
865 u8 offline_disabled_reason;
866 u8 is_active_optimize_enabled;
867 u8 driver_link_ready;
868 u8 link_enabled;
869 u8 linkinit_reason;
870 u8 local_tx_rate;
871 u8 qsfp_retry_count;
872
873
874 u8 overrun_threshold;
875 u8 phy_error_threshold;
876 unsigned int is_link_down_queued;
877
878
879
880
881
882
883 unsigned long led_override_vals[2];
884 u8 led_override_phase;
885 atomic_t led_override_timer_active;
886
887 struct timer_list led_override_timer;
888
889 u32 sm_trap_qp;
890 u32 sa_qp;
891
892
893
894
895
896 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
897 struct cca_timer cca_timer[OPA_MAX_SLS];
898
899
900 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
901
902
903 struct opa_congestion_setting_entry_shadow
904 congestion_entries[OPA_MAX_SLS];
905
906
907
908
909
910 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
911
912 struct cc_state __rcu *cc_state;
913
914
915 u16 total_cct_entry;
916
917
918 u32 cc_sl_control_map;
919
920
921 u8 cc_max_table_entries;
922
923
924
925
926
927 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
928 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
929 u16 threshold_event_counter;
930 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
931 int cc_log_idx;
932 int cc_mad_idx;
933
934
935 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
936
937
938 u64 *cntrs;
939
940 u64 *scntrs;
941
942 u64 port_xmit_discards;
943 u64 port_xmit_discards_vl[C_VL_COUNT];
944 u64 port_xmit_constraint_errors;
945 u64 port_rcv_constraint_errors;
946
947 u64 link_downed;
948
949 u64 link_up;
950
951 u64 unknown_frame_count;
952
953 u16 port_ltp_crc_mode;
954
955 u8 port_crc_mode_enabled;
956
957 u8 mgmt_allowed;
958 u8 part_enforce;
959 struct link_down_reason local_link_down_reason;
960 struct link_down_reason neigh_link_down_reason;
961
962 u8 remote_link_down_reason;
963
964 u32 port_error_action;
965 struct work_struct linkstate_active_work;
966
967 bool cc_prescan;
968
969
970
971
972 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
973 u16 prev_link_width;
974 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
975};
976
977typedef void (*opcode_handler)(struct hfi1_packet *packet);
978typedef void (*hfi1_make_req)(struct rvt_qp *qp,
979 struct hfi1_pkt_state *ps,
980 struct rvt_swqe *wqe);
981extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[];
982
983
984
985#define RHF_RCV_CONTINUE 0
986#define RHF_RCV_DONE 1
987#define RHF_RCV_REPROCESS 2
988
989struct rcv_array_data {
990 u16 ngroups;
991 u16 nctxt_extra;
992 u8 group_size;
993};
994
995struct per_vl_data {
996 u16 mtu;
997 struct send_context *sc;
998};
999
1000
1001#define PER_VL_SEND_CONTEXTS 16
1002
1003struct err_info_rcvport {
1004 u8 status_and_code;
1005 u64 packet_flit1;
1006 u64 packet_flit2;
1007};
1008
1009struct err_info_constraint {
1010 u8 status;
1011 u16 pkey;
1012 u32 slid;
1013};
1014
1015struct hfi1_temp {
1016 unsigned int curr;
1017 unsigned int lo_lim;
1018 unsigned int hi_lim;
1019 unsigned int crit_lim;
1020 u8 triggers;
1021};
1022
1023struct hfi1_i2c_bus {
1024 struct hfi1_devdata *controlling_dd;
1025 struct i2c_adapter adapter;
1026 struct i2c_algo_bit_data algo;
1027 int num;
1028};
1029
1030
1031struct hfi1_asic_data {
1032 struct hfi1_devdata *dds[2];
1033 struct mutex asic_resource_mutex;
1034 struct hfi1_i2c_bus *i2c_bus0;
1035 struct hfi1_i2c_bus *i2c_bus1;
1036};
1037
1038
1039#define NUM_MAP_ENTRIES 256
1040#define NUM_MAP_REGS 32
1041
1042
1043
1044
1045
1046#define HFI1_NUM_VNIC_CTXT 8
1047
1048
1049#define NUM_VNIC_MAP_ENTRIES 8
1050
1051
1052struct hfi1_vnic_data {
1053 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
1054 struct kmem_cache *txreq_cache;
1055 struct xarray vesws;
1056 u8 num_vports;
1057 u8 rmt_start;
1058 u8 num_ctxt;
1059};
1060
1061struct hfi1_vnic_vport_info;
1062
1063
1064
1065
1066struct sdma_engine;
1067struct sdma_vl_map;
1068
1069#define BOARD_VERS_MAX 96
1070#define SERIAL_MAX 16
1071
1072typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
1073struct hfi1_devdata {
1074 struct hfi1_ibdev verbs_dev;
1075
1076
1077 struct pci_dev *pcidev;
1078 struct cdev user_cdev;
1079 struct cdev diag_cdev;
1080 struct cdev ui_cdev;
1081 struct device *user_device;
1082 struct device *diag_device;
1083 struct device *ui_device;
1084
1085
1086 u8 __iomem *kregbase1;
1087 resource_size_t physaddr;
1088
1089
1090 u8 __iomem *kregbase2;
1091
1092 u32 base2_start;
1093
1094
1095 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
1096
1097 struct send_context_info *send_contexts;
1098
1099 u8 *hw_to_sw;
1100
1101 spinlock_t sc_lock;
1102
1103 spinlock_t pio_map_lock;
1104
1105 spinlock_t sc_init_lock;
1106
1107 spinlock_t sde_map_lock;
1108
1109 struct send_context **kernel_send_context;
1110
1111 struct pio_vl_map __rcu *pio_map;
1112
1113 u64 default_desc1;
1114
1115
1116
1117 volatile __le64 *sdma_heads_dma;
1118 dma_addr_t sdma_heads_phys;
1119 void *sdma_pad_dma;
1120 dma_addr_t sdma_pad_phys;
1121
1122 size_t sdma_heads_size;
1123
1124 u32 num_sdma;
1125
1126 struct sdma_engine *per_sdma;
1127
1128 struct sdma_vl_map __rcu *sdma_map;
1129
1130 wait_queue_head_t sdma_unfreeze_wq;
1131 atomic_t sdma_unfreeze_count;
1132
1133 u32 lcb_access_count;
1134
1135
1136 struct hfi1_asic_data *asic_data;
1137
1138
1139 void __iomem *piobase;
1140
1141
1142
1143
1144 void __iomem *rcvarray_wc;
1145
1146
1147
1148
1149 struct credit_return_base *cr_base;
1150
1151
1152 struct sc_config_sizes sc_sizes[SC_MAX];
1153
1154 char *boardname;
1155
1156
1157 u64 z_int_counter;
1158 u64 z_rcv_limit;
1159 u64 z_send_schedule;
1160
1161 u64 __percpu *send_schedule;
1162
1163 u16 num_vnic_contexts;
1164
1165 u32 num_rcv_contexts;
1166
1167 u32 num_send_contexts;
1168
1169
1170
1171 u32 freectxts;
1172
1173 u32 num_user_contexts;
1174
1175 u32 rcv_intr_timeout_csr;
1176
1177 spinlock_t sendctrl_lock;
1178 spinlock_t rcvctrl_lock;
1179 spinlock_t uctxt_lock;
1180 struct mutex dc8051_lock;
1181 struct workqueue_struct *update_cntr_wq;
1182 struct work_struct update_cntr_work;
1183
1184 spinlock_t dc8051_memlock;
1185 int dc8051_timed_out;
1186
1187
1188
1189
1190 unsigned long *events;
1191
1192
1193
1194
1195
1196 struct hfi1_status *status;
1197
1198
1199 u64 revision;
1200
1201 u64 base_guid;
1202
1203
1204 u8 link_gen3_capable;
1205 u8 dc_shutdown;
1206
1207 u32 lbus_width;
1208
1209 u32 lbus_speed;
1210 int unit;
1211 int node;
1212
1213
1214 u32 pcibar0;
1215 u32 pcibar1;
1216 u32 pci_rom;
1217 u16 pci_command;
1218 u16 pcie_devctl;
1219 u16 pcie_lnkctl;
1220 u16 pcie_devctl2;
1221 u32 pci_msix0;
1222 u32 pci_tph2;
1223
1224
1225
1226
1227
1228 u8 serial[SERIAL_MAX];
1229
1230 u8 boardversion[BOARD_VERS_MAX];
1231 u8 lbus_info[32];
1232
1233 u8 majrev;
1234
1235 u8 minrev;
1236
1237 u8 hfi1_id;
1238
1239 u8 icode;
1240
1241 u8 vau;
1242
1243 u8 vcu;
1244
1245 u16 link_credits;
1246
1247 u16 vl15_init;
1248
1249
1250
1251
1252
1253
1254
1255 u16 vl15buf_cached;
1256
1257
1258 u8 n_krcv_queues;
1259 u8 qos_shift;
1260
1261 u16 irev;
1262 u32 dc8051_ver;
1263
1264 spinlock_t hfi1_diag_trans_lock;
1265 struct platform_config platform_config;
1266 struct platform_config_cache pcfg_cache;
1267
1268 struct diag_client *diag_client;
1269
1270
1271 u64 gi_mask[CCE_NUM_INT_CSRS];
1272
1273 struct rcv_array_data rcv_entries;
1274
1275
1276 u16 psxmitwait_check_rate;
1277
1278
1279
1280
1281 struct timer_list synth_stats_timer;
1282
1283
1284 struct hfi1_msix_info msix_info;
1285
1286
1287
1288
1289 char *cntrnames;
1290 size_t cntrnameslen;
1291 size_t ndevcntrs;
1292 u64 *cntrs;
1293 u64 *scntrs;
1294
1295
1296
1297
1298 u64 last_tx;
1299 u64 last_rx;
1300
1301
1302
1303
1304 size_t nportcntrs;
1305 char *portcntrnames;
1306 size_t portcntrnameslen;
1307
1308 struct err_info_rcvport err_info_rcvport;
1309 struct err_info_constraint err_info_rcv_constraint;
1310 struct err_info_constraint err_info_xmit_constraint;
1311
1312 atomic_t drop_packet;
1313 u8 do_drop;
1314 u8 err_info_uncorrectable;
1315 u8 err_info_fmconfig;
1316
1317
1318
1319
1320
1321 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1322 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1323 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1324 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1325 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1326 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1327 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1328
1329
1330 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1331
1332 u64 sw_send_dma_eng_err_status_cnt[
1333 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1334
1335 u64 sw_cce_err_status_aggregate;
1336
1337 u64 sw_rcv_bypass_packet_errors;
1338
1339
1340 u64 lcb_err_en;
1341 struct cpu_mask_set *comp_vect;
1342 int *comp_vect_mappings;
1343 u32 comp_vect_possible_cpus;
1344
1345
1346
1347
1348
1349 send_routine process_pio_send ____cacheline_aligned_in_smp;
1350 send_routine process_dma_send;
1351 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1352 u64 pbc, const void *from, size_t count);
1353 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1354 struct hfi1_vnic_vport_info *vinfo,
1355 struct sk_buff *skb, u64 pbc, u8 plen);
1356
1357
1358
1359 struct hfi1_pportdata *pport;
1360
1361 struct hfi1_ctxtdata **rcd;
1362 u64 __percpu *int_counter;
1363
1364 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1365
1366 u16 flags;
1367
1368 u8 num_pports;
1369
1370 u8 first_dyn_alloc_ctxt;
1371
1372
1373
1374 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1375 u64 sc2vl[4];
1376 u64 __percpu *rcv_limit;
1377
1378
1379
1380 u8 oui1;
1381 u8 oui2;
1382 u8 oui3;
1383
1384
1385 struct timer_list rcverr_timer;
1386
1387 wait_queue_head_t event_queue;
1388
1389
1390 __le64 *rcvhdrtail_dummy_kvaddr;
1391 dma_addr_t rcvhdrtail_dummy_dma;
1392
1393 u32 rcv_ovfl_cnt;
1394
1395 spinlock_t aspm_lock;
1396
1397 atomic_t aspm_disabled_cnt;
1398
1399 atomic_t user_refcount;
1400
1401 struct completion user_comp;
1402
1403 bool eprom_available;
1404 bool aspm_supported;
1405 bool aspm_enabled;
1406 struct rhashtable *sdma_rht;
1407
1408 struct kobject kobj;
1409
1410
1411 struct hfi1_vnic_data vnic;
1412
1413 spinlock_t irq_src_lock;
1414};
1415
1416static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1417{
1418 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1419}
1420
1421
1422#define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1423#define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1424#define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1425#define dc8051_ver_patch(a) ((a) & 0x0000ff)
1426
1427
1428#define PT_EXPECTED 0
1429#define PT_EAGER 1
1430#define PT_INVALID_FLUSH 2
1431#define PT_INVALID 3
1432
1433struct tid_rb_node;
1434struct mmu_rb_node;
1435struct mmu_rb_handler;
1436
1437
1438struct hfi1_filedata {
1439 struct hfi1_devdata *dd;
1440 struct hfi1_ctxtdata *uctxt;
1441 struct hfi1_user_sdma_comp_q *cq;
1442 struct hfi1_user_sdma_pkt_q *pq;
1443 u16 subctxt;
1444
1445 int rec_cpu_num;
1446 u32 tid_n_pinned;
1447 struct mmu_rb_handler *handler;
1448 struct tid_rb_node **entry_to_rb;
1449 spinlock_t tid_lock;
1450 u32 tid_limit;
1451 u32 tid_used;
1452 u32 *invalid_tids;
1453 u32 invalid_tid_idx;
1454
1455 spinlock_t invalid_lock;
1456 struct mm_struct *mm;
1457};
1458
1459extern struct xarray hfi1_dev_table;
1460struct hfi1_devdata *hfi1_lookup(int unit);
1461
1462static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1463{
1464 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1465 HFI1_MAX_SHARED_CTXTS;
1466}
1467
1468int hfi1_init(struct hfi1_devdata *dd, int reinit);
1469int hfi1_count_active_units(void);
1470
1471int hfi1_diag_add(struct hfi1_devdata *dd);
1472void hfi1_diag_remove(struct hfi1_devdata *dd);
1473void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1474
1475void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1476
1477int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1478int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1479int hfi1_create_kctxts(struct hfi1_devdata *dd);
1480int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1481 struct hfi1_ctxtdata **rcd);
1482void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1483void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1484 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1485void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1486int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1487int hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1488struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1489 u16 ctxt);
1490struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1491int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1492int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1493int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1494void set_all_slowpath(struct hfi1_devdata *dd);
1495
1496extern const struct pci_device_id hfi1_pci_tbl[];
1497void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1498 struct hfi1_pkt_state *ps,
1499 struct rvt_swqe *wqe);
1500
1501void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1502 struct hfi1_pkt_state *ps,
1503 struct rvt_swqe *wqe);
1504
1505
1506#define RCV_PKT_OK 0x0
1507#define RCV_PKT_LIMIT 0x1
1508#define RCV_PKT_DONE 0x2
1509
1510
1511static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1512{
1513 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset;
1514}
1515
1516int hfi1_reset_device(int);
1517
1518void receive_interrupt_work(struct work_struct *work);
1519
1520
1521static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1522{
1523 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1524}
1525
1526#define HFI1_JKEY_WIDTH 16
1527#define HFI1_JKEY_MASK (BIT(16) - 1)
1528#define HFI1_ADMIN_JKEY_RANGE 32
1529
1530
1531
1532
1533
1534
1535
1536static inline u16 generate_jkey(kuid_t uid)
1537{
1538 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1539
1540 if (capable(CAP_SYS_ADMIN))
1541 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1542 else if (jkey < 64)
1543 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1544
1545 return jkey;
1546}
1547
1548
1549
1550
1551
1552
1553static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1554{
1555 u16 link_speed = ppd->link_speed_active;
1556 u16 link_width = ppd->link_width_active;
1557 u32 egress_rate;
1558
1559 if (link_speed == OPA_LINK_SPEED_25G)
1560 egress_rate = 25000;
1561 else
1562 egress_rate = 12500;
1563
1564 switch (link_width) {
1565 case OPA_LINK_WIDTH_4X:
1566 egress_rate *= 4;
1567 break;
1568 case OPA_LINK_WIDTH_3X:
1569 egress_rate *= 3;
1570 break;
1571 case OPA_LINK_WIDTH_2X:
1572 egress_rate *= 2;
1573 break;
1574 default:
1575
1576 break;
1577 }
1578
1579 return egress_rate;
1580}
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590static inline u32 egress_cycles(u32 len, u32 rate)
1591{
1592 u32 cycles;
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602 cycles = len * 8;
1603 cycles *= 805;
1604 cycles /= rate;
1605
1606 return cycles;
1607}
1608
1609void set_link_ipg(struct hfi1_pportdata *ppd);
1610void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1611 u32 rqpn, u8 svc_type);
1612void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1613 u16 pkey, u32 slid, u32 dlid, u8 sc5,
1614 const struct ib_grh *old_grh);
1615void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1616 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1617 u8 sc5, const struct ib_grh *old_grh);
1618typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1619 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1620 u8 sc5, const struct ib_grh *old_grh);
1621
1622#define PKEY_CHECK_INVALID -1
1623int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1624 u8 sc5, int8_t s_pkey_index);
1625
1626#define PACKET_EGRESS_TIMEOUT 350
1627static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1628{
1629
1630 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1631
1632 udelay(usec ? usec : 1);
1633}
1634
1635
1636
1637
1638
1639
1640static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1641{
1642 unsigned seq;
1643 u8 rval;
1644
1645 if (sc5 >= OPA_MAX_SCS)
1646 return (u8)(0xff);
1647
1648 do {
1649 seq = read_seqbegin(&dd->sc2vl_lock);
1650 rval = *(((u8 *)dd->sc2vl) + sc5);
1651 } while (read_seqretry(&dd->sc2vl_lock, seq));
1652
1653 return rval;
1654}
1655
1656#define PKEY_MEMBER_MASK 0x8000
1657#define PKEY_LOW_15_MASK 0x7fff
1658
1659
1660
1661
1662
1663
1664
1665static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1666{
1667 u16 mkey = pkey & PKEY_LOW_15_MASK;
1668 u16 ment = ent & PKEY_LOW_15_MASK;
1669
1670 if (mkey == ment) {
1671
1672
1673
1674
1675
1676 if (!(pkey & PKEY_MEMBER_MASK))
1677 return !!(ent & PKEY_MEMBER_MASK);
1678 return 1;
1679 }
1680 return 0;
1681}
1682
1683
1684
1685
1686
1687
1688static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1689{
1690 int i;
1691
1692 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1693 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1694 return 0;
1695 }
1696 return 1;
1697}
1698
1699
1700
1701
1702
1703
1704static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1705 u32 slid)
1706{
1707 struct hfi1_devdata *dd = ppd->dd;
1708
1709 incr_cntr64(&ppd->port_rcv_constraint_errors);
1710 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1711 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1712 dd->err_info_rcv_constraint.slid = slid;
1713 dd->err_info_rcv_constraint.pkey = pkey;
1714 }
1715}
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1726 u8 sc5, u8 idx, u32 slid, bool force)
1727{
1728 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1729 return 0;
1730
1731
1732 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1733 goto bad;
1734
1735
1736 if ((pkey & PKEY_LOW_15_MASK) == 0)
1737 goto bad;
1738
1739
1740 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1741 return 0;
1742
1743
1744 if (!ingress_pkey_table_search(ppd, pkey))
1745 return 0;
1746
1747bad:
1748 ingress_pkey_table_fail(ppd, pkey, slid);
1749 return 1;
1750}
1751
1752
1753
1754
1755
1756
1757
1758static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1759 u8 sc5, u16 slid)
1760{
1761 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1762 return 0;
1763
1764
1765 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1766 goto bad;
1767
1768 return 0;
1769bad:
1770 ingress_pkey_table_fail(ppd, pkey, slid);
1771 return 1;
1772}
1773
1774
1775
1776
1777#define OPA_MTU_0 0
1778#define OPA_MTU_256 1
1779#define OPA_MTU_512 2
1780#define OPA_MTU_1024 3
1781#define OPA_MTU_2048 4
1782#define OPA_MTU_4096 5
1783
1784u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1785int mtu_to_enum(u32 mtu, int default_if_bad);
1786u16 enum_to_mtu(int mtu);
1787static inline int valid_ib_mtu(unsigned int mtu)
1788{
1789 return mtu == 256 || mtu == 512 ||
1790 mtu == 1024 || mtu == 2048 ||
1791 mtu == 4096;
1792}
1793
1794static inline int valid_opa_max_mtu(unsigned int mtu)
1795{
1796 return mtu >= 2048 &&
1797 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1798}
1799
1800int set_mtu(struct hfi1_pportdata *ppd);
1801
1802int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1803void hfi1_disable_after_error(struct hfi1_devdata *dd);
1804int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1805int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1806
1807int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1808int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1809
1810void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1811void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1812void reset_link_credits(struct hfi1_devdata *dd);
1813void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1814
1815int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1816
1817static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1818{
1819 return ppd->dd;
1820}
1821
1822static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1823{
1824 return container_of(dev, struct hfi1_devdata, verbs_dev);
1825}
1826
1827static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1828{
1829 return dd_from_dev(to_idev(ibdev));
1830}
1831
1832static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1833{
1834 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1835}
1836
1837static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1838{
1839 return container_of(rdi, struct hfi1_ibdev, rdi);
1840}
1841
1842static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1843{
1844 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1845 unsigned pidx = port - 1;
1846
1847 WARN_ON(pidx >= dd->num_pports);
1848 return &dd->pport[pidx].ibport_data;
1849}
1850
1851static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1852{
1853 return &rcd->ppd->ibport_data;
1854}
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867static inline bool hfi1_may_ecn(struct hfi1_packet *pkt)
1868{
1869 bool fecn, becn;
1870
1871 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1872 fecn = hfi1_16B_get_fecn(pkt->hdr);
1873 becn = hfi1_16B_get_becn(pkt->hdr);
1874 } else {
1875 fecn = ib_bth_get_fecn(pkt->ohdr);
1876 becn = ib_bth_get_becn(pkt->ohdr);
1877 }
1878 return fecn || becn;
1879}
1880
1881bool hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1882 bool prescan);
1883static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt)
1884{
1885 bool do_work;
1886
1887 do_work = hfi1_may_ecn(pkt);
1888 if (unlikely(do_work))
1889 return hfi1_process_ecn_slowpath(qp, pkt, false);
1890 return false;
1891}
1892
1893
1894
1895
1896static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1897{
1898 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1899 u16 ret;
1900
1901 if (index >= ARRAY_SIZE(ppd->pkeys))
1902 ret = 0;
1903 else
1904 ret = ppd->pkeys[index];
1905
1906 return ret;
1907}
1908
1909
1910
1911
1912static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1913{
1914 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1915
1916 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1917 return cpu_to_be64(ppd->guids[index]);
1918}
1919
1920
1921
1922
1923static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1924{
1925 return rcu_dereference(ppd->cc_state);
1926}
1927
1928
1929
1930
1931static inline
1932struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1933{
1934 return rcu_dereference_protected(ppd->cc_state,
1935 lockdep_is_held(&ppd->cc_state_lock));
1936}
1937
1938
1939
1940
1941#define HFI1_INITTED 0x1
1942#define HFI1_PRESENT 0x2
1943#define HFI1_FROZEN 0x4
1944#define HFI1_HAS_SDMA_TIMEOUT 0x8
1945#define HFI1_HAS_SEND_DMA 0x10
1946#define HFI1_FORCED_FREEZE 0x80
1947#define HFI1_SHUTDOWN 0x100
1948
1949
1950#define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1951
1952
1953
1954#define HFI1_CTXT_BASE_UNINIT 1
1955
1956#define HFI1_CTXT_BASE_FAILED 2
1957
1958#define HFI1_CTXT_WAITING_RCV 3
1959
1960#define HFI1_CTXT_WAITING_URG 4
1961
1962
1963int hfi1_init_dd(struct hfi1_devdata *dd);
1964void hfi1_free_devdata(struct hfi1_devdata *dd);
1965
1966
1967void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1968 unsigned int timeoff);
1969void shutdown_led_override(struct hfi1_pportdata *ppd);
1970
1971#define HFI1_CREDIT_RETURN_RATE (100)
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992#define DEFAULT_RCVHDRSIZE 9
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009#define DEFAULT_RCVHDR_ENTSIZE 32
2010
2011bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
2012 u32 nlocked, u32 npages);
2013int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
2014 size_t npages, bool writable, struct page **pages);
2015void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
2016 size_t npages, bool dirty);
2017
2018static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
2019{
2020 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
2021}
2022
2023static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
2024{
2025
2026
2027
2028
2029 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
2030}
2031
2032
2033
2034
2035
2036extern const char ib_hfi1_version[];
2037extern const struct attribute_group ib_hfi1_attr_group;
2038
2039int hfi1_device_create(struct hfi1_devdata *dd);
2040void hfi1_device_remove(struct hfi1_devdata *dd);
2041
2042int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
2043 struct kobject *kobj);
2044int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
2045void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
2046
2047int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
2048
2049int hfi1_pcie_init(struct hfi1_devdata *dd);
2050void hfi1_pcie_cleanup(struct pci_dev *pdev);
2051int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
2052void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
2053int pcie_speeds(struct hfi1_devdata *dd);
2054int restore_pci_variables(struct hfi1_devdata *dd);
2055int save_pci_variables(struct hfi1_devdata *dd);
2056int do_pcie_gen3_transition(struct hfi1_devdata *dd);
2057void tune_pcie_caps(struct hfi1_devdata *dd);
2058int parse_platform_config(struct hfi1_devdata *dd);
2059int get_platform_config_field(struct hfi1_devdata *dd,
2060 enum platform_config_table_type_encoding
2061 table_type, int table_index, int field_index,
2062 u32 *data, u32 len);
2063
2064struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
2065
2066
2067
2068
2069
2070static inline void flush_wc(void)
2071{
2072 asm volatile("sfence" : : : "memory");
2073}
2074
2075void handle_eflags(struct hfi1_packet *packet);
2076void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2077
2078
2079extern unsigned int hfi1_max_mtu;
2080extern unsigned int hfi1_cu;
2081extern unsigned int user_credit_return_threshold;
2082extern int num_user_contexts;
2083extern unsigned long n_krcvqs;
2084extern uint krcvqs[];
2085extern int krcvqsset;
2086extern uint kdeth_qp;
2087extern uint loopback;
2088extern uint quick_linkup;
2089extern uint rcv_intr_timeout;
2090extern uint rcv_intr_count;
2091extern uint rcv_intr_dynamic;
2092extern ushort link_crc_mask;
2093
2094extern struct mutex hfi1_mutex;
2095
2096
2097#define STATUS_TIMEOUT 60
2098
2099#define DRIVER_NAME "hfi1"
2100#define HFI1_USER_MINOR_BASE 0
2101#define HFI1_TRACE_MINOR 127
2102#define HFI1_NMINORS 255
2103
2104#define PCI_VENDOR_ID_INTEL 0x8086
2105#define PCI_DEVICE_ID_INTEL0 0x24f0
2106#define PCI_DEVICE_ID_INTEL1 0x24f1
2107
2108#define HFI1_PKT_USER_SC_INTEGRITY \
2109 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2110 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2111 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2112 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2113
2114#define HFI1_PKT_KERNEL_SC_INTEGRITY \
2115 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2116
2117static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2118 u16 ctxt_type)
2119{
2120 u64 base_sc_integrity;
2121
2122
2123 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2124 return 0;
2125
2126 base_sc_integrity =
2127 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2128 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2129 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2130 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2131 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2132#ifndef CONFIG_FAULT_INJECTION
2133 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2134#endif
2135 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2136 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2137 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2138 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2139 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2140 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2141 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2142 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2143 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2144 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2145
2146 if (ctxt_type == SC_USER)
2147 base_sc_integrity |=
2148#ifndef CONFIG_FAULT_INJECTION
2149 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2150#endif
2151 HFI1_PKT_USER_SC_INTEGRITY;
2152 else if (ctxt_type != SC_KERNEL)
2153 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2154
2155
2156 if (!is_ax(dd))
2157 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2158
2159 return base_sc_integrity;
2160}
2161
2162static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2163{
2164 u64 base_sdma_integrity;
2165
2166
2167 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2168 return 0;
2169
2170 base_sdma_integrity =
2171 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2172 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2173 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2174 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2175 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2176 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2177 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2178 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2179 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2180 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2181 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2182 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2183 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2184 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2185
2186 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2187 base_sdma_integrity |=
2188 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2189
2190
2191 if (!is_ax(dd))
2192 base_sdma_integrity |=
2193 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2194
2195 return base_sdma_integrity;
2196}
2197
2198#define dd_dev_emerg(dd, fmt, ...) \
2199 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2200 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2201
2202#define dd_dev_err(dd, fmt, ...) \
2203 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2204 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2205
2206#define dd_dev_err_ratelimited(dd, fmt, ...) \
2207 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2208 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2209 ##__VA_ARGS__)
2210
2211#define dd_dev_warn(dd, fmt, ...) \
2212 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2213 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2214
2215#define dd_dev_warn_ratelimited(dd, fmt, ...) \
2216 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2217 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2218 ##__VA_ARGS__)
2219
2220#define dd_dev_info(dd, fmt, ...) \
2221 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2222 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2223
2224#define dd_dev_info_ratelimited(dd, fmt, ...) \
2225 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2226 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2227 ##__VA_ARGS__)
2228
2229#define dd_dev_dbg(dd, fmt, ...) \
2230 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2231 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2232
2233#define hfi1_dev_porterr(dd, port, fmt, ...) \
2234 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2235 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2236
2237
2238
2239
2240struct hfi1_hwerror_msgs {
2241 u64 mask;
2242 const char *msg;
2243 size_t sz;
2244};
2245
2246
2247void hfi1_format_hwerrors(u64 hwerrs,
2248 const struct hfi1_hwerror_msgs *hwerrmsgs,
2249 size_t nhwerrmsgs, char *msg, size_t lmsg);
2250
2251#define USER_OPCODE_CHECK_VAL 0xC0
2252#define USER_OPCODE_CHECK_MASK 0xC0
2253#define OPCODE_CHECK_VAL_DISABLED 0x0
2254#define OPCODE_CHECK_MASK_DISABLED 0x0
2255
2256static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2257{
2258 struct hfi1_pportdata *ppd;
2259 int i;
2260
2261 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2262 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2263 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2264
2265 ppd = (struct hfi1_pportdata *)(dd + 1);
2266 for (i = 0; i < dd->num_pports; i++, ppd++) {
2267 ppd->ibport_data.rvp.z_rc_acks =
2268 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2269 ppd->ibport_data.rvp.z_rc_qacks =
2270 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2271 }
2272}
2273
2274
2275static inline void setextled(struct hfi1_devdata *dd, u32 on)
2276{
2277 if (on)
2278 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2279 else
2280 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2281}
2282
2283
2284static inline u32 i2c_target(u32 target)
2285{
2286 return target ? CR_I2C2 : CR_I2C1;
2287}
2288
2289
2290static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2291{
2292 return i2c_target(dd->hfi1_id);
2293}
2294
2295
2296static inline bool is_integrated(struct hfi1_devdata *dd)
2297{
2298 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2299}
2300
2301int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2302
2303#define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2304#define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2305
2306static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2307 struct rdma_ah_attr *attr)
2308{
2309 struct hfi1_pportdata *ppd;
2310 struct hfi1_ibport *ibp;
2311 u32 dlid = rdma_ah_get_dlid(attr);
2312
2313
2314
2315
2316
2317 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2318 ppd = ppd_from_ibp(ibp);
2319 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2320 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2321 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2322 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2323 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2324 (rdma_ah_get_make_grd(attr))) {
2325 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2326 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2327 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2328 }
2329}
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339static inline bool hfi1_check_mcast(u32 lid)
2340{
2341 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2342 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2343}
2344
2345#define opa_get_lid(lid, format) \
2346 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2347
2348
2349static inline u32 __opa_get_lid(u32 lid, u8 format)
2350{
2351 bool is_mcast = hfi1_check_mcast(lid);
2352
2353 switch (format) {
2354 case OPA_PORT_PACKET_FORMAT_8B:
2355 case OPA_PORT_PACKET_FORMAT_10B:
2356 if (is_mcast)
2357 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2358 0xF0000);
2359 return lid & 0xFFFFF;
2360 case OPA_PORT_PACKET_FORMAT_16B:
2361 if (is_mcast)
2362 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2363 0xF00000);
2364 return lid & 0xFFFFFF;
2365 case OPA_PORT_PACKET_FORMAT_9B:
2366 if (is_mcast)
2367 return (lid -
2368 opa_get_mcast_base(OPA_MCAST_NR) +
2369 be16_to_cpu(IB_MULTICAST_LID_BASE));
2370 else
2371 return lid & 0xFFFF;
2372 default:
2373 return lid;
2374 }
2375}
2376
2377
2378static inline bool hfi1_is_16B_mcast(u32 lid)
2379{
2380 return ((lid >=
2381 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2382 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2383}
2384
2385static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2386{
2387 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2388 u32 dlid = rdma_ah_get_dlid(attr);
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398 if (ib_is_opa_gid(&grh->dgid))
2399 dlid = opa_get_lid_from_gid(&grh->dgid);
2400 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2401 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2402 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2403 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2404 opa_get_mcast_base(OPA_MCAST_NR);
2405 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2406 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2407
2408 rdma_ah_set_dlid(attr, dlid);
2409}
2410
2411static inline u8 hfi1_get_packet_type(u32 lid)
2412{
2413
2414 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2415 return HFI1_PKT_TYPE_9B;
2416
2417
2418 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2419 return HFI1_PKT_TYPE_16B;
2420
2421 return HFI1_PKT_TYPE_9B;
2422}
2423
2424static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2425{
2426
2427
2428
2429
2430
2431
2432
2433 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2434 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2435 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2436
2437
2438
2439
2440
2441 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2442 return HFI1_PKT_TYPE_16B;
2443
2444 return hfi1_get_packet_type(lid);
2445}
2446
2447static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2448 struct ib_grh *grh, u32 slid,
2449 u32 dlid)
2450{
2451 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2452 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2453
2454 if (!ibp)
2455 return;
2456
2457 grh->hop_limit = 1;
2458 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2459 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2460 grh->sgid.global.interface_id =
2461 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2462 else
2463 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2464
2465
2466
2467
2468
2469
2470
2471
2472 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2473 grh->dgid.global.interface_id =
2474 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2475}
2476
2477static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2478{
2479 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2480 SIZE_OF_LT) & 0x7;
2481}
2482
2483static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2484 u16 lrh0, u16 len,
2485 u16 dlid, u16 slid)
2486{
2487 hdr->lrh[0] = cpu_to_be16(lrh0);
2488 hdr->lrh[1] = cpu_to_be16(dlid);
2489 hdr->lrh[2] = cpu_to_be16(len);
2490 hdr->lrh[3] = cpu_to_be16(slid);
2491}
2492
2493static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2494 u32 slid, u32 dlid,
2495 u16 len, u16 pkey,
2496 bool becn, bool fecn, u8 l4,
2497 u8 sc)
2498{
2499 u32 lrh0 = 0;
2500 u32 lrh1 = 0x40000000;
2501 u32 lrh2 = 0;
2502 u32 lrh3 = 0;
2503
2504 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2505 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2506 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2507 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2508 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2509 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2510 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2511 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2512 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2513 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2514 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2515 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2516
2517 hdr->lrh[0] = lrh0;
2518 hdr->lrh[1] = lrh1;
2519 hdr->lrh[2] = lrh2;
2520 hdr->lrh[3] = lrh3;
2521}
2522#endif
2523