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33#ifndef MLX5_IB_H
34#define MLX5_IB_H
35
36#include <linux/kernel.h>
37#include <linux/sched.h>
38#include <rdma/ib_verbs.h>
39#include <rdma/ib_umem.h>
40#include <rdma/ib_smi.h>
41#include <linux/mlx5/driver.h>
42#include <linux/mlx5/cq.h>
43#include <linux/mlx5/fs.h>
44#include <linux/mlx5/qp.h>
45#include <linux/types.h>
46#include <linux/mlx5/transobj.h>
47#include <rdma/ib_user_verbs.h>
48#include <rdma/mlx5-abi.h>
49#include <rdma/uverbs_ioctl.h>
50#include <rdma/mlx5_user_ioctl_cmds.h>
51#include <rdma/mlx5_user_ioctl_verbs.h>
52
53#include "srq.h"
54
55#define mlx5_ib_dbg(_dev, format, arg...) \
56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
57 __LINE__, current->pid, ##arg)
58
59#define mlx5_ib_err(_dev, format, arg...) \
60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
61 __LINE__, current->pid, ##arg)
62
63#define mlx5_ib_warn(_dev, format, arg...) \
64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
65 __LINE__, current->pid, ##arg)
66
67#define field_avail(type, fld, sz) (offsetof(type, fld) + \
68 sizeof(((type *)0)->fld) <= (sz))
69#define MLX5_IB_DEFAULT_UIDX 0xffffff
70#define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
71
72#define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
73
74enum {
75 MLX5_IB_MMAP_CMD_SHIFT = 8,
76 MLX5_IB_MMAP_CMD_MASK = 0xff,
77};
78
79enum {
80 MLX5_RES_SCAT_DATA32_CQE = 0x1,
81 MLX5_RES_SCAT_DATA64_CQE = 0x2,
82 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
83 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
84};
85
86enum mlx5_ib_mad_ifc_flags {
87 MLX5_MAD_IFC_IGNORE_MKEY = 1,
88 MLX5_MAD_IFC_IGNORE_BKEY = 2,
89 MLX5_MAD_IFC_NET_VIEW = 4,
90};
91
92enum {
93 MLX5_CROSS_CHANNEL_BFREG = 0,
94};
95
96enum {
97 MLX5_CQE_VERSION_V0,
98 MLX5_CQE_VERSION_V1,
99};
100
101enum {
102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
103 MLX5_TM_MAX_SGE = 1,
104};
105
106enum {
107 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
108 MLX5_IB_INVALID_BFREG = BIT(31),
109};
110
111enum {
112 MLX5_MAX_MEMIC_PAGES = 0x100,
113 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
114};
115
116enum {
117 MLX5_MEMIC_BASE_ALIGN = 6,
118 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
119};
120
121#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \
122 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
123#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
124
125struct mlx5_ib_ucontext {
126 struct ib_ucontext ibucontext;
127 struct list_head db_page_list;
128
129
130
131 struct mutex db_page_mutex;
132 struct mlx5_bfreg_info bfregi;
133 u8 cqe_version;
134
135 u32 tdn;
136
137 u64 lib_caps;
138 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
139 u16 devx_uid;
140
141 atomic_t tx_port_affinity;
142};
143
144static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
145{
146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
147}
148
149struct mlx5_ib_pd {
150 struct ib_pd ibpd;
151 u32 pdn;
152 u16 uid;
153};
154
155enum {
156 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
157 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
158 MLX5_IB_FLOW_ACTION_DECAP,
159};
160
161#define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
162#define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
163#if (MLX5_IB_FLOW_LAST_PRIO <= 0)
164#error "Invalid number of bypass priorities"
165#endif
166#define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
167
168#define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
169#define MLX5_IB_NUM_SNIFFER_FTS 2
170#define MLX5_IB_NUM_EGRESS_FTS 1
171struct mlx5_ib_flow_prio {
172 struct mlx5_flow_table *flow_table;
173 unsigned int refcount;
174};
175
176struct mlx5_ib_flow_handler {
177 struct list_head list;
178 struct ib_flow ibflow;
179 struct mlx5_ib_flow_prio *prio;
180 struct mlx5_flow_handle *rule;
181 struct ib_counters *ibcounters;
182 struct mlx5_ib_dev *dev;
183 struct mlx5_ib_flow_matcher *flow_matcher;
184};
185
186struct mlx5_ib_flow_matcher {
187 struct mlx5_ib_match_params matcher_mask;
188 int mask_len;
189 enum mlx5_ib_flow_type flow_type;
190 enum mlx5_flow_namespace_type ns_type;
191 u16 priority;
192 struct mlx5_core_dev *mdev;
193 atomic_t usecnt;
194 u8 match_criteria_enable;
195};
196
197struct mlx5_ib_flow_db {
198 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
199 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
200 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
201 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
202 struct mlx5_ib_flow_prio fdb;
203 struct mlx5_flow_table *lag_demux_ft;
204
205
206
207
208
209 struct mutex lock;
210};
211
212
213
214
215
216#define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
217#define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
218#define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
219#define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
220#define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
221#define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
222
223#define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
224
225
226
227
228#define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
229#define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
230#define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
231#define MLX5_IB_WR_UMR IB_WR_RESERVED1
232
233#define MLX5_IB_UMR_OCTOWORD 16
234#define MLX5_IB_UMR_XLT_ALIGNMENT 64
235
236#define MLX5_IB_UPD_XLT_ZAP BIT(0)
237#define MLX5_IB_UPD_XLT_ENABLE BIT(1)
238#define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
239#define MLX5_IB_UPD_XLT_ADDR BIT(3)
240#define MLX5_IB_UPD_XLT_PD BIT(4)
241#define MLX5_IB_UPD_XLT_ACCESS BIT(5)
242#define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
243
244
245
246
247
248
249
250
251static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
252{
253 return IB_QP_CREATE_RESERVED_START;
254}
255
256struct wr_list {
257 u16 opcode;
258 u16 next;
259};
260
261enum mlx5_ib_rq_flags {
262 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
263 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
264};
265
266struct mlx5_ib_wq {
267 struct mlx5_frag_buf_ctrl fbc;
268 u64 *wrid;
269 u32 *wr_data;
270 struct wr_list *w_list;
271 unsigned *wqe_head;
272 u16 unsig_count;
273
274
275
276 spinlock_t lock;
277 int wqe_cnt;
278 int max_post;
279 int max_gs;
280 int offset;
281 int wqe_shift;
282 unsigned head;
283 unsigned tail;
284 u16 cur_post;
285 void *cur_edge;
286};
287
288enum mlx5_ib_wq_flags {
289 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
290 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
291};
292
293#define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
294#define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
295#define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
296#define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
297
298struct mlx5_ib_rwq {
299 struct ib_wq ibwq;
300 struct mlx5_core_qp core_qp;
301 u32 rq_num_pas;
302 u32 log_rq_stride;
303 u32 log_rq_size;
304 u32 rq_page_offset;
305 u32 log_page_size;
306 u32 log_num_strides;
307 u32 two_byte_shift_en;
308 u32 single_stride_log_num_of_bytes;
309 struct ib_umem *umem;
310 size_t buf_size;
311 unsigned int page_shift;
312 int create_type;
313 struct mlx5_db db;
314 u32 user_index;
315 u32 wqe_count;
316 u32 wqe_shift;
317 int wq_sig;
318 u32 create_flags;
319};
320
321enum {
322 MLX5_QP_USER,
323 MLX5_QP_KERNEL,
324 MLX5_QP_EMPTY
325};
326
327enum {
328 MLX5_WQ_USER,
329 MLX5_WQ_KERNEL
330};
331
332struct mlx5_ib_rwq_ind_table {
333 struct ib_rwq_ind_table ib_rwq_ind_tbl;
334 u32 rqtn;
335 u16 uid;
336};
337
338struct mlx5_ib_ubuffer {
339 struct ib_umem *umem;
340 int buf_size;
341 u64 buf_addr;
342};
343
344struct mlx5_ib_qp_base {
345 struct mlx5_ib_qp *container_mibqp;
346 struct mlx5_core_qp mqp;
347 struct mlx5_ib_ubuffer ubuffer;
348};
349
350struct mlx5_ib_qp_trans {
351 struct mlx5_ib_qp_base base;
352 u16 xrcdn;
353 u8 alt_port;
354 u8 atomic_rd_en;
355 u8 resp_depth;
356};
357
358struct mlx5_ib_rss_qp {
359 u32 tirn;
360};
361
362struct mlx5_ib_rq {
363 struct mlx5_ib_qp_base base;
364 struct mlx5_ib_wq *rq;
365 struct mlx5_ib_ubuffer ubuffer;
366 struct mlx5_db *doorbell;
367 u32 tirn;
368 u8 state;
369 u32 flags;
370};
371
372struct mlx5_ib_sq {
373 struct mlx5_ib_qp_base base;
374 struct mlx5_ib_wq *sq;
375 struct mlx5_ib_ubuffer ubuffer;
376 struct mlx5_db *doorbell;
377 struct mlx5_flow_handle *flow_rule;
378 u32 tisn;
379 u8 state;
380};
381
382struct mlx5_ib_raw_packet_qp {
383 struct mlx5_ib_sq sq;
384 struct mlx5_ib_rq rq;
385};
386
387struct mlx5_bf {
388 int buf_size;
389 unsigned long offset;
390 struct mlx5_sq_bfreg *bfreg;
391};
392
393struct mlx5_ib_dct {
394 struct mlx5_core_dct mdct;
395 u32 *in;
396};
397
398struct mlx5_ib_qp {
399 struct ib_qp ibqp;
400 union {
401 struct mlx5_ib_qp_trans trans_qp;
402 struct mlx5_ib_raw_packet_qp raw_packet_qp;
403 struct mlx5_ib_rss_qp rss_qp;
404 struct mlx5_ib_dct dct;
405 };
406 struct mlx5_frag_buf buf;
407
408 struct mlx5_db db;
409 struct mlx5_ib_wq rq;
410
411 u8 sq_signal_bits;
412 u8 next_fence;
413 struct mlx5_ib_wq sq;
414
415
416
417 struct mutex mutex;
418 u32 flags;
419 u8 port;
420 u8 state;
421 int wq_sig;
422 int scat_cqe;
423 int max_inline_data;
424 struct mlx5_bf bf;
425 int has_rq;
426
427
428
429
430 int bfregn;
431
432 int create_type;
433
434 struct list_head qps_list;
435 struct list_head cq_recv_list;
436 struct list_head cq_send_list;
437 struct mlx5_rate_limit rl;
438 u32 underlay_qpn;
439 u32 flags_en;
440
441 enum ib_qp_type qp_sub_type;
442
443
444
445 u32 counter_pending;
446};
447
448struct mlx5_ib_cq_buf {
449 struct mlx5_frag_buf_ctrl fbc;
450 struct mlx5_frag_buf frag_buf;
451 struct ib_umem *umem;
452 int cqe_size;
453 int nent;
454};
455
456enum mlx5_ib_qp_flags {
457 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
458 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
459 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
460 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
461 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
462 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
463
464 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
465 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
466 MLX5_IB_QP_RSS = 1 << 8,
467 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
468 MLX5_IB_QP_UNDERLAY = 1 << 10,
469 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
470 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
471 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13,
472};
473
474struct mlx5_umr_wr {
475 struct ib_send_wr wr;
476 u64 virt_addr;
477 u64 offset;
478 struct ib_pd *pd;
479 unsigned int page_shift;
480 unsigned int xlt_size;
481 u64 length;
482 int access_flags;
483 u32 mkey;
484 u8 ignore_free_state:1;
485};
486
487static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
488{
489 return container_of(wr, struct mlx5_umr_wr, wr);
490}
491
492struct mlx5_shared_mr_info {
493 int mr_id;
494 struct ib_umem *umem;
495};
496
497enum mlx5_ib_cq_pr_flags {
498 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
499};
500
501struct mlx5_ib_cq {
502 struct ib_cq ibcq;
503 struct mlx5_core_cq mcq;
504 struct mlx5_ib_cq_buf buf;
505 struct mlx5_db db;
506
507
508
509 spinlock_t lock;
510
511
512
513 struct mutex resize_mutex;
514 struct mlx5_ib_cq_buf *resize_buf;
515 struct ib_umem *resize_umem;
516 int cqe_size;
517 struct list_head list_send_qp;
518 struct list_head list_recv_qp;
519 u32 create_flags;
520 struct list_head wc_list;
521 enum ib_cq_notify_flags notify_flags;
522 struct work_struct notify_work;
523 u16 private_flags;
524};
525
526struct mlx5_ib_wc {
527 struct ib_wc wc;
528 struct list_head list;
529};
530
531struct mlx5_ib_srq {
532 struct ib_srq ibsrq;
533 struct mlx5_core_srq msrq;
534 struct mlx5_frag_buf buf;
535 struct mlx5_db db;
536 struct mlx5_frag_buf_ctrl fbc;
537 u64 *wrid;
538
539
540 spinlock_t lock;
541 int head;
542 int tail;
543 u16 wqe_ctr;
544 struct ib_umem *umem;
545
546
547 struct mutex mutex;
548 int wq_sig;
549};
550
551struct mlx5_ib_xrcd {
552 struct ib_xrcd ibxrcd;
553 u32 xrcdn;
554};
555
556enum mlx5_ib_mtt_access_flags {
557 MLX5_IB_MTT_READ = (1 << 0),
558 MLX5_IB_MTT_WRITE = (1 << 1),
559};
560
561struct mlx5_ib_dm {
562 struct ib_dm ibdm;
563 phys_addr_t dev_addr;
564 u32 type;
565 size_t size;
566 union {
567 struct {
568 u32 obj_id;
569 } icm_dm;
570
571 };
572};
573
574#define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
575
576#define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
577 IB_ACCESS_REMOTE_WRITE |\
578 IB_ACCESS_REMOTE_READ |\
579 IB_ACCESS_REMOTE_ATOMIC |\
580 IB_ZERO_BASED)
581
582#define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
583 IB_ACCESS_REMOTE_WRITE |\
584 IB_ACCESS_REMOTE_READ |\
585 IB_ZERO_BASED)
586
587struct mlx5_ib_mr {
588 struct ib_mr ibmr;
589 void *descs;
590 dma_addr_t desc_map;
591 int ndescs;
592 int data_length;
593 int meta_ndescs;
594 int meta_length;
595 int max_descs;
596 int desc_size;
597 int access_mode;
598 struct mlx5_core_mkey mmkey;
599 struct ib_umem *umem;
600 struct mlx5_shared_mr_info *smr_info;
601 struct list_head list;
602 int order;
603 bool allocated_from_cache;
604 int npages;
605 struct mlx5_ib_dev *dev;
606 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
607 struct mlx5_core_sig_ctx *sig;
608 int live;
609 void *descs_alloc;
610 int access_flags;
611
612 struct mlx5_ib_mr *parent;
613
614 struct mlx5_ib_mr *pi_mr;
615 struct mlx5_ib_mr *klm_mr;
616 struct mlx5_ib_mr *mtt_mr;
617 u64 data_iova;
618 u64 pi_iova;
619
620 atomic_t num_leaf_free;
621 wait_queue_head_t q_leaf_free;
622 struct mlx5_async_work cb_work;
623 atomic_t num_pending_prefetch;
624};
625
626static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
627{
628 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
629 mr->umem->is_odp;
630}
631
632struct mlx5_ib_mw {
633 struct ib_mw ibmw;
634 struct mlx5_core_mkey mmkey;
635 int ndescs;
636};
637
638struct mlx5_ib_devx_mr {
639 struct mlx5_core_mkey mmkey;
640 int ndescs;
641 struct rcu_head rcu;
642};
643
644struct mlx5_ib_umr_context {
645 struct ib_cqe cqe;
646 enum ib_wc_status status;
647 struct completion done;
648};
649
650struct umr_common {
651 struct ib_pd *pd;
652 struct ib_cq *cq;
653 struct ib_qp *qp;
654
655
656 struct semaphore sem;
657};
658
659enum {
660 MLX5_FMR_INVALID,
661 MLX5_FMR_VALID,
662 MLX5_FMR_BUSY,
663};
664
665struct mlx5_cache_ent {
666 struct list_head head;
667
668
669 spinlock_t lock;
670
671
672 char name[4];
673 u32 order;
674 u32 xlt;
675 u32 access_mode;
676 u32 page;
677
678 u32 size;
679 u32 cur;
680 u32 miss;
681 u32 limit;
682
683 struct mlx5_ib_dev *dev;
684 struct work_struct work;
685 struct delayed_work dwork;
686 int pending;
687 struct completion compl;
688};
689
690struct mlx5_mr_cache {
691 struct workqueue_struct *wq;
692 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
693 int stopped;
694 struct dentry *root;
695 unsigned long last_add;
696};
697
698struct mlx5_ib_gsi_qp;
699
700struct mlx5_ib_port_resources {
701 struct mlx5_ib_resources *devr;
702 struct mlx5_ib_gsi_qp *gsi;
703 struct work_struct pkey_change_work;
704};
705
706struct mlx5_ib_resources {
707 struct ib_cq *c0;
708 struct ib_xrcd *x0;
709 struct ib_xrcd *x1;
710 struct ib_pd *p0;
711 struct ib_srq *s0;
712 struct ib_srq *s1;
713 struct mlx5_ib_port_resources ports[2];
714
715 struct mutex mutex;
716};
717
718struct mlx5_ib_counters {
719 const char **names;
720 size_t *offsets;
721 u32 num_q_counters;
722 u32 num_cong_counters;
723 u32 num_ext_ppcnt_counters;
724 u16 set_id;
725 bool set_id_valid;
726};
727
728struct mlx5_ib_multiport_info;
729
730struct mlx5_ib_multiport {
731 struct mlx5_ib_multiport_info *mpi;
732
733 spinlock_t mpi_lock;
734};
735
736struct mlx5_roce {
737
738
739
740 rwlock_t netdev_lock;
741 struct net_device *netdev;
742 struct notifier_block nb;
743 atomic_t tx_port_affinity;
744 enum ib_port_state last_port_state;
745 struct mlx5_ib_dev *dev;
746 u8 native_port_num;
747};
748
749struct mlx5_ib_port {
750 struct mlx5_ib_counters cnts;
751 struct mlx5_ib_multiport mp;
752 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
753 struct mlx5_roce roce;
754 struct mlx5_eswitch_rep *rep;
755};
756
757struct mlx5_ib_dbg_param {
758 int offset;
759 struct mlx5_ib_dev *dev;
760 struct dentry *dentry;
761 u8 port_num;
762};
763
764enum mlx5_ib_dbg_cc_types {
765 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
766 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
767 MLX5_IB_DBG_CC_RP_TIME_RESET,
768 MLX5_IB_DBG_CC_RP_BYTE_RESET,
769 MLX5_IB_DBG_CC_RP_THRESHOLD,
770 MLX5_IB_DBG_CC_RP_AI_RATE,
771 MLX5_IB_DBG_CC_RP_HAI_RATE,
772 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
773 MLX5_IB_DBG_CC_RP_MIN_RATE,
774 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
775 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
776 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
777 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
778 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
779 MLX5_IB_DBG_CC_RP_GD,
780 MLX5_IB_DBG_CC_NP_CNP_DSCP,
781 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
782 MLX5_IB_DBG_CC_NP_CNP_PRIO,
783 MLX5_IB_DBG_CC_MAX,
784};
785
786struct mlx5_ib_dbg_cc_params {
787 struct dentry *root;
788 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
789};
790
791enum {
792 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
793};
794
795struct mlx5_ib_dbg_delay_drop {
796 struct dentry *dir_debugfs;
797 struct dentry *rqs_cnt_debugfs;
798 struct dentry *events_cnt_debugfs;
799 struct dentry *timeout_debugfs;
800};
801
802struct mlx5_ib_delay_drop {
803 struct mlx5_ib_dev *dev;
804 struct work_struct delay_drop_work;
805
806 struct mutex lock;
807 u32 timeout;
808 bool activate;
809 atomic_t events_cnt;
810 atomic_t rqs_cnt;
811 struct mlx5_ib_dbg_delay_drop *dbg;
812};
813
814enum mlx5_ib_stages {
815 MLX5_IB_STAGE_INIT,
816 MLX5_IB_STAGE_FLOW_DB,
817 MLX5_IB_STAGE_CAPS,
818 MLX5_IB_STAGE_NON_DEFAULT_CB,
819 MLX5_IB_STAGE_ROCE,
820 MLX5_IB_STAGE_SRQ,
821 MLX5_IB_STAGE_DEVICE_RESOURCES,
822 MLX5_IB_STAGE_DEVICE_NOTIFIER,
823 MLX5_IB_STAGE_ODP,
824 MLX5_IB_STAGE_COUNTERS,
825 MLX5_IB_STAGE_CONG_DEBUGFS,
826 MLX5_IB_STAGE_UAR,
827 MLX5_IB_STAGE_BFREG,
828 MLX5_IB_STAGE_PRE_IB_REG_UMR,
829 MLX5_IB_STAGE_WHITELIST_UID,
830 MLX5_IB_STAGE_IB_REG,
831 MLX5_IB_STAGE_POST_IB_REG_UMR,
832 MLX5_IB_STAGE_DELAY_DROP,
833 MLX5_IB_STAGE_CLASS_ATTR,
834 MLX5_IB_STAGE_MAX,
835};
836
837struct mlx5_ib_stage {
838 int (*init)(struct mlx5_ib_dev *dev);
839 void (*cleanup)(struct mlx5_ib_dev *dev);
840};
841
842#define STAGE_CREATE(_stage, _init, _cleanup) \
843 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
844
845struct mlx5_ib_profile {
846 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
847};
848
849struct mlx5_ib_multiport_info {
850 struct list_head list;
851 struct mlx5_ib_dev *ibdev;
852 struct mlx5_core_dev *mdev;
853 struct notifier_block mdev_events;
854 struct completion unref_comp;
855 u64 sys_image_guid;
856 u32 mdev_refcnt;
857 bool is_master;
858 bool unaffiliate;
859};
860
861struct mlx5_ib_flow_action {
862 struct ib_flow_action ib_action;
863 union {
864 struct {
865 u64 ib_flags;
866 struct mlx5_accel_esp_xfrm *ctx;
867 } esp_aes_gcm;
868 struct {
869 struct mlx5_ib_dev *dev;
870 u32 sub_type;
871 u32 action_id;
872 } flow_action_raw;
873 };
874};
875
876struct mlx5_dm {
877 struct mlx5_core_dev *dev;
878
879
880
881
882 spinlock_t lock;
883 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
884 unsigned long *steering_sw_icm_alloc_blocks;
885 unsigned long *header_modify_sw_icm_alloc_blocks;
886};
887
888struct mlx5_read_counters_attr {
889 struct mlx5_fc *hw_cntrs_hndl;
890 u64 *out;
891 u32 flags;
892};
893
894enum mlx5_ib_counters_type {
895 MLX5_IB_COUNTERS_FLOW,
896};
897
898struct mlx5_ib_mcounters {
899 struct ib_counters ibcntrs;
900 enum mlx5_ib_counters_type type;
901
902 u32 counters_num;
903 struct mlx5_fc *hw_cntrs_hndl;
904
905 int (*read_counters)(struct ib_device *ibdev,
906 struct mlx5_read_counters_attr *read_attr);
907
908 u32 cntrs_max_index;
909
910 u32 ncounters;
911
912 struct mlx5_ib_flow_counters_desc *counters_data;
913
914 struct mutex mcntrs_mutex;
915};
916
917static inline struct mlx5_ib_mcounters *
918to_mcounters(struct ib_counters *ibcntrs)
919{
920 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
921}
922
923int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
924 bool is_egress,
925 struct mlx5_flow_act *action);
926struct mlx5_ib_lb_state {
927
928 struct mutex mutex;
929 u32 user_td;
930 int qps;
931 bool enabled;
932};
933
934struct mlx5_ib_pf_eq {
935 struct notifier_block irq_nb;
936 struct mlx5_ib_dev *dev;
937 struct mlx5_eq *core;
938 struct work_struct work;
939 spinlock_t lock;
940 struct workqueue_struct *wq;
941 mempool_t *pool;
942};
943
944struct mlx5_devx_event_table {
945 struct mlx5_nb devx_nb;
946
947 struct mutex event_xa_lock;
948 struct xarray event_xa;
949};
950
951struct mlx5_ib_dev {
952 struct ib_device ib_dev;
953 struct mlx5_core_dev *mdev;
954 struct notifier_block mdev_events;
955 int num_ports;
956
957
958 struct mutex cap_mask_mutex;
959 bool ib_active;
960 struct umr_common umrc;
961
962
963 struct mlx5_ib_resources devr;
964 struct mlx5_mr_cache cache;
965 struct timer_list delay_timer;
966
967 struct mutex slow_path_mutex;
968 int fill_delay;
969 struct ib_odp_caps odp_caps;
970 u64 odp_max_size;
971 struct mlx5_ib_pf_eq odp_pf_eq;
972
973
974
975
976
977 struct srcu_struct mr_srcu;
978 u32 null_mkey;
979 struct mlx5_ib_flow_db *flow_db;
980
981 spinlock_t reset_flow_resource_lock;
982 struct list_head qp_list;
983
984 struct mlx5_ib_port *port;
985 struct mlx5_sq_bfreg bfreg;
986 struct mlx5_sq_bfreg fp_bfreg;
987 struct mlx5_ib_delay_drop delay_drop;
988 const struct mlx5_ib_profile *profile;
989 bool is_rep;
990 int lag_active;
991
992 struct mlx5_ib_lb_state lb;
993 u8 umr_fence;
994 struct list_head ib_dev_list;
995 u64 sys_image_guid;
996 struct mlx5_dm dm;
997 u16 devx_whitelist_uid;
998 struct mlx5_srq_table srq_table;
999 struct mlx5_async_ctx async_ctx;
1000 struct mlx5_devx_event_table devx_event_table;
1001};
1002
1003static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1004{
1005 return container_of(mcq, struct mlx5_ib_cq, mcq);
1006}
1007
1008static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1009{
1010 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1011}
1012
1013static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1014{
1015 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1016}
1017
1018static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1019{
1020 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1021 udata, struct mlx5_ib_ucontext, ibucontext);
1022
1023 return to_mdev(context->ibucontext.device);
1024}
1025
1026static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1027{
1028 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1029}
1030
1031static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1032{
1033 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1034}
1035
1036static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1037{
1038 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1039}
1040
1041static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
1042{
1043 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
1044}
1045
1046static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1047{
1048 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1049}
1050
1051static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1052{
1053 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1054}
1055
1056static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1057{
1058 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1059}
1060
1061static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1062{
1063 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1064}
1065
1066static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1067{
1068 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1069}
1070
1071static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1072{
1073 return container_of(msrq, struct mlx5_ib_srq, msrq);
1074}
1075
1076static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
1077{
1078 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
1079}
1080
1081static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1082{
1083 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1084}
1085
1086static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1087{
1088 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1089}
1090
1091static inline struct mlx5_ib_flow_action *
1092to_mflow_act(struct ib_flow_action *ibact)
1093{
1094 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1095}
1096
1097int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1098 struct ib_udata *udata, unsigned long virt,
1099 struct mlx5_db *db);
1100void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1101void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1102void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1103void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1104int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags,
1105 struct ib_udata *udata);
1106int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1107void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags);
1108int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1109 struct ib_udata *udata);
1110int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1111 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1112int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1113void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1114int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1115 const struct ib_recv_wr **bad_wr);
1116int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1117void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1118struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1119 struct ib_qp_init_attr *init_attr,
1120 struct ib_udata *udata);
1121int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1122 int attr_mask, struct ib_udata *udata);
1123int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1124 struct ib_qp_init_attr *qp_init_attr);
1125int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1126void mlx5_ib_drain_sq(struct ib_qp *qp);
1127void mlx5_ib_drain_rq(struct ib_qp *qp);
1128int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1129 const struct ib_send_wr **bad_wr);
1130int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1131 const struct ib_recv_wr **bad_wr);
1132int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1133 int buflen, size_t *bc);
1134int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1135 int buflen, size_t *bc);
1136int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
1137 void *buffer, int buflen, size_t *bc);
1138int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1139 struct ib_udata *udata);
1140void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1141int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1142int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1143int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1144int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1145struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1146struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1147 u64 virt_addr, int access_flags,
1148 struct ib_udata *udata);
1149int mlx5_ib_advise_mr(struct ib_pd *pd,
1150 enum ib_uverbs_advise_mr_advice advice,
1151 u32 flags,
1152 struct ib_sge *sg_list,
1153 u32 num_sge,
1154 struct uverbs_attr_bundle *attrs);
1155struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1156 struct ib_udata *udata);
1157int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1158int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1159 int page_shift, int flags);
1160struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1161 struct ib_udata *udata,
1162 int access_flags);
1163void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1164int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1165 u64 length, u64 virt_addr, int access_flags,
1166 struct ib_pd *pd, struct ib_udata *udata);
1167int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1168struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1169 u32 max_num_sg, struct ib_udata *udata);
1170struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1171 u32 max_num_sg,
1172 u32 max_num_meta_sg);
1173int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1174 unsigned int *sg_offset);
1175int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1176 int data_sg_nents, unsigned int *data_sg_offset,
1177 struct scatterlist *meta_sg, int meta_sg_nents,
1178 unsigned int *meta_sg_offset);
1179int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1180 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1181 const struct ib_mad_hdr *in, size_t in_mad_size,
1182 struct ib_mad_hdr *out, size_t *out_mad_size,
1183 u16 *out_mad_pkey_index);
1184struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1185 struct ib_udata *udata);
1186int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1187int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1188int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1189int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1190 struct ib_smp *out_mad);
1191int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1192 __be64 *sys_image_guid);
1193int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1194 u16 *max_pkeys);
1195int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1196 u32 *vendor_id);
1197int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1198int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1199int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1200 u16 *pkey);
1201int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1202 union ib_gid *gid);
1203int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1204 struct ib_port_attr *props);
1205int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1206 struct ib_port_attr *props);
1207int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1208void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1209void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1210 unsigned long max_page_shift,
1211 int *count, int *shift,
1212 int *ncont, int *order);
1213void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1214 int page_shift, size_t offset, size_t num_pages,
1215 __be64 *pas, int access_flags);
1216void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1217 int page_shift, __be64 *pas, int access_flags);
1218void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1219int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1220int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1221int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1222
1223struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1224void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1225int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1226 struct ib_mr_status *mr_status);
1227struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1228 struct ib_wq_init_attr *init_attr,
1229 struct ib_udata *udata);
1230void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1231int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1232 u32 wq_attr_mask, struct ib_udata *udata);
1233struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1234 struct ib_rwq_ind_table_init_attr *init_attr,
1235 struct ib_udata *udata);
1236int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1237bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1238struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1239 struct ib_ucontext *context,
1240 struct ib_dm_alloc_attr *attr,
1241 struct uverbs_attr_bundle *attrs);
1242int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs);
1243struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1244 struct ib_dm_mr_attr *attr,
1245 struct uverbs_attr_bundle *attrs);
1246
1247#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1248void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1249int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1250void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1251int __init mlx5_ib_odp_init(void);
1252void mlx5_ib_odp_cleanup(void);
1253void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start,
1254 unsigned long end);
1255void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1256void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1257 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1258
1259int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1260 enum ib_uverbs_advise_mr_advice advice,
1261 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1262#else
1263static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1264{
1265 return;
1266}
1267
1268static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1269static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1270static inline int mlx5_ib_odp_init(void) { return 0; }
1271static inline void mlx5_ib_odp_cleanup(void) {}
1272static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1273static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1274 size_t nentries, struct mlx5_ib_mr *mr,
1275 int flags) {}
1276
1277static inline int
1278mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1279 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1280 struct ib_sge *sg_list, u32 num_sge)
1281{
1282 return -EOPNOTSUPP;
1283}
1284static inline void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp,
1285 unsigned long start,
1286 unsigned long end){};
1287#endif
1288
1289
1290void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1291 const struct mlx5_ib_profile *profile,
1292 int stage);
1293void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1294 const struct mlx5_ib_profile *profile);
1295
1296int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1297 u8 port, struct ifla_vf_info *info);
1298int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1299 u8 port, int state);
1300int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1301 u8 port, struct ifla_vf_stats *stats);
1302int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1303 u64 guid, int type);
1304
1305__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1306 const struct ib_gid_attr *attr);
1307
1308void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1309void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1310
1311
1312struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1313 struct ib_qp_init_attr *init_attr);
1314int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1315int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1316 int attr_mask);
1317int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1318 int qp_attr_mask,
1319 struct ib_qp_init_attr *qp_init_attr);
1320int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1321 const struct ib_send_wr **bad_wr);
1322int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1323 const struct ib_recv_wr **bad_wr);
1324void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1325
1326int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1327
1328void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1329 int bfregn);
1330struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1331struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1332 u8 ib_port_num,
1333 u8 *native_port_num);
1334void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1335 u8 port_num);
1336
1337#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1338int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user);
1339void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid);
1340void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev);
1341void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev);
1342const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void);
1343extern const struct uapi_definition mlx5_ib_devx_defs[];
1344extern const struct uapi_definition mlx5_ib_flow_defs[];
1345struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1346 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1347 struct mlx5_flow_context *flow_context,
1348 struct mlx5_flow_act *flow_act, u32 counter_id,
1349 void *cmd_in, int inlen, int dest_id, int dest_type);
1350bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1351bool mlx5_ib_devx_is_flow_counter(void *obj, u32 *counter_id);
1352int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root);
1353void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction);
1354#else
1355static inline int
1356mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1357 bool is_user) { return -EOPNOTSUPP; }
1358static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {}
1359static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {}
1360static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {}
1361static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1362 int *dest_type)
1363{
1364 return false;
1365}
1366static inline void
1367mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction)
1368{
1369 return;
1370};
1371#endif
1372static inline void init_query_mad(struct ib_smp *mad)
1373{
1374 mad->base_version = 1;
1375 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1376 mad->class_version = 1;
1377 mad->method = IB_MGMT_METHOD_GET;
1378}
1379
1380static inline u8 convert_access(int acc)
1381{
1382 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1383 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1384 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1385 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1386 MLX5_PERM_LOCAL_READ;
1387}
1388
1389static inline int is_qp1(enum ib_qp_type qp_type)
1390{
1391 return qp_type == MLX5_IB_QPT_HW_GSI;
1392}
1393
1394#define MLX5_MAX_UMR_SHIFT 16
1395#define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1396
1397static inline u32 check_cq_create_flags(u32 flags)
1398{
1399
1400
1401
1402
1403 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1404 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1405}
1406
1407static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1408 u32 *user_index)
1409{
1410 if (cqe_version) {
1411 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1412 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1413 return -EINVAL;
1414 *user_index = cmd_uidx;
1415 } else {
1416 *user_index = MLX5_IB_DEFAULT_UIDX;
1417 }
1418
1419 return 0;
1420}
1421
1422static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1423 struct mlx5_ib_create_qp *ucmd,
1424 int inlen,
1425 u32 *user_index)
1426{
1427 u8 cqe_version = ucontext->cqe_version;
1428
1429 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1430 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1431 return 0;
1432
1433 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1434 !!cqe_version))
1435 return -EINVAL;
1436
1437 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1438}
1439
1440static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1441 struct mlx5_ib_create_srq *ucmd,
1442 int inlen,
1443 u32 *user_index)
1444{
1445 u8 cqe_version = ucontext->cqe_version;
1446
1447 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1448 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1449 return 0;
1450
1451 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1452 !!cqe_version))
1453 return -EINVAL;
1454
1455 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1456}
1457
1458static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1459{
1460 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1461 MLX5_UARS_IN_PAGE : 1;
1462}
1463
1464static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1465 struct mlx5_bfreg_info *bfregi)
1466{
1467 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1468}
1469
1470unsigned long mlx5_ib_get_xlt_emergency_page(void);
1471void mlx5_ib_put_xlt_emergency_page(void);
1472
1473int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1474 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1475 bool dyn_bfreg);
1476
1477int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter);
1478
1479static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev,
1480 bool do_modify_atomic)
1481{
1482 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1483 return false;
1484
1485 if (do_modify_atomic &&
1486 MLX5_CAP_GEN(dev->mdev, atomic) &&
1487 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1488 return false;
1489
1490 return true;
1491}
1492#endif
1493