/*
 * Copyright (c) 2012 - 2017 Intel Corporation.  All rights reserved.
 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/*
 * This file contains all of the code that is specific to the
 * InfiniPath 7322 chip
 */

#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_smi.h>
#ifdef CONFIG_INFINIBAND_QIB_DCA
#include <linux/dca.h>
#endif

#include "qib.h"
#include "qib_7322_regs.h"
#include "qib_qsfp.h"

#include "qib_mad.h"
#include "qib_verbs.h"

#undef pr_fmt
#define pr_fmt(fmt) QIB_DRV_NAME " " fmt

static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
static irqreturn_t qib_7322intr(int irq, void *data);
static irqreturn_t qib_7322bufavail(int irq, void *data);
static irqreturn_t sdma_intr(int irq, void *data);
static irqreturn_t sdma_idle_intr(int irq, void *data);
static irqreturn_t sdma_progress_intr(int irq, void *data);
static irqreturn_t sdma_cleanup_intr(int irq, void *data);
static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
                                  struct qib_ctxtdata *rcd);
static u8 qib_7322_phys_portstate(u64);
static u32 qib_7322_iblink_state(u64);
static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
                                   u16 linitcmd);
static void force_h1(struct qib_pportdata *);
static void adj_tx_serdes(struct qib_pportdata *);
static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
static void qib_7322_mini_pcs_reset(struct qib_pportdata *);

static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
static void serdes_7322_los_enable(struct qib_pportdata *, int);
static int serdes_7322_init_old(struct qib_pportdata *);
static int serdes_7322_init_new(struct qib_pportdata *);
static void dump_sdma_7322_state(struct qib_pportdata *);

#define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))

/* LE2 serdes values for different cases */
#define LE2_DEFAULT 5
#define LE2_5m 4
#define LE2_QME 0

/* Below is special-purpose, so only really works for the IB SerDes blocks. */
#define IBSD(hw_pidx) (hw_pidx + 2)

/* these are variables for documentation and experimentation purposes */
static const unsigned rcv_int_timeout = 375;
static const unsigned rcv_int_count = 16;
static const unsigned sdma_idle_cnt = 64;

/* Time to stop altering Rx Equalization parameters, after link up. */
#define RXEQ_DISABLE_MSECS 2500

/*
 * Number of VLs we are configured to use (to allow for more
 * credits per vl, etc.)
 */
ushort qib_num_cfg_vls = 2;
module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");

static ushort qib_chase = 1;
module_param_named(chase, qib_chase, ushort, S_IRUGO);
MODULE_PARM_DESC(chase, "Enable state chase handling");

static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
MODULE_PARM_DESC(long_attenuation,
                 "attenuation cutoff (dB) for long copper cable setup");

static ushort qib_singleport;
module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");

static ushort qib_krcvq01_no_msi;
module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");

/*
 * Receive header queue sizes
 */
static unsigned qib_rcvhdrcnt;
module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
MODULE_PARM_DESC(rcvhdrcnt, "receive header count");

static unsigned qib_rcvhdrsize;
module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");

static unsigned qib_rcvhdrentsize;
module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");

#define MAX_ATTEN_LEN 64 /* plenty for any real system */
/* for read back, default index is ~5m copper cable */
static char txselect_list[MAX_ATTEN_LEN] = "10";
static struct kparam_string kp_txselect = {
        .string = txselect_list,
        .maxlen = MAX_ATTEN_LEN
};
static int  setup_txselect(const char *, const struct kernel_param *);
module_param_call(txselect, setup_txselect, param_get_string,
                  &kp_txselect, S_IWUSR | S_IRUGO);
MODULE_PARM_DESC(txselect,
                 "Tx serdes indices (for no QSFP or invalid QSFP data)");

#define BOARD_QME7342 5
#define BOARD_QMH7342 6
#define BOARD_QMH7360 9
#define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
                    BOARD_QMH7342)
#define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
                    BOARD_QME7342)

#define KREG_IDX(regname)     (QIB_7322_##regname##_OFFS / sizeof(u64))

#define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))

#define MASK_ACROSS(lsb, msb) \
        (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))

#define SYM_RMASK(regname, fldname) ((u64)              \
        QIB_7322_##regname##_##fldname##_RMASK)

#define SYM_MASK(regname, fldname) ((u64)               \
        QIB_7322_##regname##_##fldname##_RMASK <<       \
         QIB_7322_##regname##_##fldname##_LSB)

#define SYM_FIELD(value, regname, fldname) ((u64)       \
        (((value) >> SYM_LSB(regname, fldname)) &       \
         SYM_RMASK(regname, fldname)))

/* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
#define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
        (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))

#define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
#define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
#define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
#define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
#define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
/* Below because most, but not all, fields of IntMask have that full suffix */
#define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)


#define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)

/*
 * the size bits give us 2^N, in KB units.  0 marks as invalid,
 * and 7 is reserved.  We currently use only 2KB and 4KB
 */
#define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
#define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
#define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
#define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */

#define SendIBSLIDAssignMask \
        QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
#define SendIBSLMCMask \
        QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK

#define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
#define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
#define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
#define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
#define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
#define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)

#define _QIB_GPIO_SDA_NUM 1
#define _QIB_GPIO_SCL_NUM 0
#define QIB_EEPROM_WEN_NUM 14
#define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */

/* HW counter clock is at 4nsec */
#define QIB_7322_PSXMITWAIT_CHECK_RATE 4000

/* full speed IB port 1 only */
#define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
#define PORT_SPD_CAP_SHIFT 3

/* full speed featuremask, both ports */
#define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))

/*
 * This file contains almost all the chip-specific register information and
 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
 */

/* Use defines to tie machine-generated names to lower-case names */
#define kr_contextcnt KREG_IDX(ContextCnt)
#define kr_control KREG_IDX(Control)
#define kr_counterregbase KREG_IDX(CntrRegBase)
#define kr_errclear KREG_IDX(ErrClear)
#define kr_errmask KREG_IDX(ErrMask)
#define kr_errstatus KREG_IDX(ErrStatus)
#define kr_extctrl KREG_IDX(EXTCtrl)
#define kr_extstatus KREG_IDX(EXTStatus)
#define kr_gpio_clear KREG_IDX(GPIOClear)
#define kr_gpio_mask KREG_IDX(GPIOMask)
#define kr_gpio_out KREG_IDX(GPIOOut)
#define kr_gpio_status KREG_IDX(GPIOStatus)
#define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
#define kr_debugportval KREG_IDX(DebugPortValueReg)
#define kr_fmask KREG_IDX(feature_mask)
#define kr_act_fmask KREG_IDX(active_feature_mask)
#define kr_hwerrclear KREG_IDX(HwErrClear)
#define kr_hwerrmask KREG_IDX(HwErrMask)
#define kr_hwerrstatus KREG_IDX(HwErrStatus)
#define kr_intclear KREG_IDX(IntClear)
#define kr_intmask KREG_IDX(IntMask)
#define kr_intredirect KREG_IDX(IntRedirect0)
#define kr_intstatus KREG_IDX(IntStatus)
#define kr_pagealign KREG_IDX(PageAlign)
#define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
#define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
#define kr_rcvegrbase KREG_IDX(RcvEgrBase)
#define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
#define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
#define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
#define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
#define kr_rcvtidbase KREG_IDX(RcvTIDBase)
#define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
#define kr_revision KREG_IDX(Revision)
#define kr_scratch KREG_IDX(Scratch)
#define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
#define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
#define kr_sendctrl KREG_IDX(SendCtrl)
#define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
#define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
#define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
#define kr_sendpiobufbase KREG_IDX(SendBufBase)
#define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
#define kr_sendpiosize KREG_IDX(SendBufSize)
#define kr_sendregbase KREG_IDX(SendRegBase)
#define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
#define kr_userregbase KREG_IDX(UserRegBase)
#define kr_intgranted KREG_IDX(Int_Granted)
#define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
#define kr_intblocked KREG_IDX(IntBlocked)
#define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)

/*
 * per-port kernel registers.  Access only with qib_read_kreg_port()
 * or qib_write_kreg_port()
 */
#define krp_errclear KREG_IBPORT_IDX(ErrClear)
#define krp_errmask KREG_IBPORT_IDX(ErrMask)
#define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
#define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
#define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
#define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
#define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
#define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
#define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
#define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
#define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
#define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
#define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
#define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
#define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
#define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
#define krp_psinterval KREG_IBPORT_IDX(PSInterval)
#define krp_psstart KREG_IBPORT_IDX(PSStart)
#define krp_psstat KREG_IBPORT_IDX(PSStat)
#define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
#define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
#define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
#define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
#define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
#define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
#define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
#define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
#define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
#define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
#define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
#define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
#define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
#define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
#define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
#define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
#define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
#define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
#define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
#define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
#define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
#define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
#define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
#define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
#define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
#define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
#define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
#define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
#define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
#define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
#define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)

/*
 * Per-context kernel registers.  Access only with qib_read_kreg_ctxt()
 * or qib_write_kreg_ctxt()
 */
#define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
#define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)

/*
 * TID Flow table, per context.  Reduces
 * number of hdrq updates to one per flow (or on errors).
 * context 0 and 1 share same memory, but have distinct
 * addresses.  Since for now, we never use expected sends
 * on kernel contexts, we don't worry about that (we initialize
 * those entries for ctxt 0/1 on driver load twice, for example).
 */
#define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
#define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))

/* these are the error bits in the tid flows, and are W1C */
#define TIDFLOW_ERRBITS  ( \
        (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
        SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
        (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
        SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))

/* Most (not all) Counters are per-IBport.
 * Requires LBIntCnt is at offset 0 in the group
 */
#define CREG_IDX(regname) \
((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))

#define crp_badformat CREG_IDX(RxVersionErrCnt)
#define crp_err_rlen CREG_IDX(RxLenErrCnt)
#define crp_erricrc CREG_IDX(RxICRCErrCnt)
#define crp_errlink CREG_IDX(RxLinkMalformCnt)
#define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
#define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
#define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
#define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
#define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
#define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
#define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
#define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
#define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
#define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
#define crp_pktrcv CREG_IDX(RxDataPktCnt)
#define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
#define crp_pktsend CREG_IDX(TxDataPktCnt)
#define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
#define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
#define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
#define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
#define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
#define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
#define crp_rcvebp CREG_IDX(RxEBPCnt)
#define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
#define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
#define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
#define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
#define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
#define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
#define crp_rxvlerr CREG_IDX(RxVlErrCnt)
#define crp_sendstall CREG_IDX(TxFlowStallCnt)
#define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
#define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
#define crp_txlenerr CREG_IDX(TxLenErrCnt)
#define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
#define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
#define crp_txunderrun CREG_IDX(TxUnderrunCnt)
#define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
#define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
#define crp_wordrcv CREG_IDX(RxDwordCnt)
#define crp_wordsend CREG_IDX(TxDwordCnt)
#define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)

/* these are the (few) counters that are not port-specific */
#define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
                        QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
#define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
#define cr_lbint CREG_DEVIDX(LBIntCnt)
#define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
#define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
#define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
#define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
#define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)

/* no chip register for # of IB ports supported, so define */
#define NUM_IB_PORTS 2

/* 1 VL15 buffer per hardware IB port, no register for this, so define */
#define NUM_VL15_BUFS NUM_IB_PORTS

/*
 * context 0 and 1 are special, and there is no chip register that
 * defines this value, so we have to define it here.
 * These are all allocated to either 0 or 1 for single port
 * hardware configuration, otherwise each gets half
 */
#define KCTXT0_EGRCNT 2048

/* values for vl and port fields in PBC, 7322-specific */
#define PBC_PORT_SEL_LSB 26
#define PBC_PORT_SEL_RMASK 1
#define PBC_VL_NUM_LSB 27
#define PBC_VL_NUM_RMASK 7
#define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
#define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */

static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
        [IB_RATE_2_5_GBPS] = 16,
        [IB_RATE_5_GBPS] = 8,
        [IB_RATE_10_GBPS] = 4,
        [IB_RATE_20_GBPS] = 2,
        [IB_RATE_30_GBPS] = 2,
        [IB_RATE_40_GBPS] = 1
};

static const char * const qib_sdma_state_names[] = {
        [qib_sdma_state_s00_hw_down]          = "s00_HwDown",
        [qib_sdma_state_s10_hw_start_up_wait] = "s10_HwStartUpWait",
        [qib_sdma_state_s20_idle]             = "s20_Idle",
        [qib_sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
        [qib_sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
        [qib_sdma_state_s50_hw_halt_wait]     = "s50_HwHaltWait",
        [qib_sdma_state_s99_running]          = "s99_Running",
};

#define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
#define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)

/* link training states, from IBC */
#define IB_7322_LT_STATE_DISABLED        0x00
#define IB_7322_LT_STATE_LINKUP          0x01
#define IB_7322_LT_STATE_POLLACTIVE      0x02
#define IB_7322_LT_STATE_POLLQUIET       0x03
#define IB_7322_LT_STATE_SLEEPDELAY      0x04
#define IB_7322_LT_STATE_SLEEPQUIET      0x05
#define IB_7322_LT_STATE_CFGDEBOUNCE     0x08
#define IB_7322_LT_STATE_CFGRCVFCFG      0x09
#define IB_7322_LT_STATE_CFGWAITRMT      0x0a
#define IB_7322_LT_STATE_CFGIDLE         0x0b
#define IB_7322_LT_STATE_RECOVERRETRAIN  0x0c
#define IB_7322_LT_STATE_TXREVLANES      0x0d
#define IB_7322_LT_STATE_RECOVERWAITRMT  0x0e
#define IB_7322_LT_STATE_RECOVERIDLE     0x0f
#define IB_7322_LT_STATE_CFGENH          0x10
#define IB_7322_LT_STATE_CFGTEST         0x11
#define IB_7322_LT_STATE_CFGWAITRMTTEST  0x12
#define IB_7322_LT_STATE_CFGWAITENH      0x13

/* link state machine states from IBC */
#define IB_7322_L_STATE_DOWN             0x0
#define IB_7322_L_STATE_INIT             0x1
#define IB_7322_L_STATE_ARM              0x2
#define IB_7322_L_STATE_ACTIVE           0x3
#define IB_7322_L_STATE_ACT_DEFER        0x4

static const u8 qib_7322_physportstate[0x20] = {
        [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
        [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
        [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
        [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
        [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
        [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
        [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
        [IB_7322_LT_STATE_CFGRCVFCFG] =
                IB_PHYSPORTSTATE_CFG_TRAIN,
        [IB_7322_LT_STATE_CFGWAITRMT] =
                IB_PHYSPORTSTATE_CFG_TRAIN,
        [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
        [IB_7322_LT_STATE_RECOVERRETRAIN] =
                IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
        [IB_7322_LT_STATE_RECOVERWAITRMT] =
                IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
        [IB_7322_LT_STATE_RECOVERIDLE] =
                IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
        [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
        [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
        [IB_7322_LT_STATE_CFGWAITRMTTEST] =
                IB_PHYSPORTSTATE_CFG_TRAIN,
        [IB_7322_LT_STATE_CFGWAITENH] =
                IB_PHYSPORTSTATE_CFG_WAIT_ENH,
        [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
        [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
        [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
        [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
};

#ifdef CONFIG_INFINIBAND_QIB_DCA
struct qib_irq_notify {
        int rcv;
        void *arg;
        struct irq_affinity_notify notify;
};
#endif

struct qib_chip_specific {
        u64 __iomem *cregbase;
        u64 *cntrs;
        spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
        spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
        u64 main_int_mask;      /* clear bits which have dedicated handlers */
        u64 int_enable_mask;  /* for per port interrupts in single port mode */
        u64 errormask;
        u64 hwerrmask;
        u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
        u64 gpio_mask; /* shadow the gpio mask register */
        u64 extctrl; /* shadow the gpio output enable, etc... */
        u32 ncntrs;
        u32 nportcntrs;
        u32 cntrnamelen;
        u32 portcntrnamelen;
        u32 numctxts;
        u32 rcvegrcnt;
        u32 updthresh; /* current AvailUpdThld */
        u32 updthresh_dflt; /* default AvailUpdThld */
        u32 r1;
        u32 num_msix_entries;
        u32 sdmabufcnt;
        u32 lastbuf_for_pio;
        u32 stay_in_freeze;
        u32 recovery_ports_initted;
#ifdef CONFIG_INFINIBAND_QIB_DCA
        u32 dca_ctrl;
        int rhdr_cpu[18];
        int sdma_cpu[2];
        u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
#endif
        struct qib_msix_entry *msix_entries;
        unsigned long *sendchkenable;
        unsigned long *sendgrhchk;
        unsigned long *sendibchk;
        u32 rcvavail_timeout[18];
        char emsgbuf[128]; /* for device error interrupt msg buffer */
};

/* Table of entries in "human readable" form Tx Emphasis. */
struct txdds_ent {
        u8 amp;
        u8 pre;
        u8 main;
        u8 post;
};

struct vendor_txdds_ent {
        u8 oui[QSFP_VOUI_LEN];
        u8 *partnum;
        struct txdds_ent sdr;
        struct txdds_ent ddr;
        struct txdds_ent qdr;
};

static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);

#define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
#define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */
#define TXDDS_MFG_SZ 2    /* number of mfg tx settings entries */
#define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */

#define H1_FORCE_VAL 8
#define H1_FORCE_QME 1 /*  may be overridden via setup_txselect() */
#define H1_FORCE_QMH 7 /*  may be overridden via setup_txselect() */

/* The static and dynamic registers are paired, and the pairs indexed by spd */
#define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
        + ((spd) * 2))

#define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
#define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
#define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
#define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
#define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */

struct qib_chippport_specific {
        u64 __iomem *kpregbase;
        u64 __iomem *cpregbase;
        u64 *portcntrs;
        struct qib_pportdata *ppd;
        wait_queue_head_t autoneg_wait;
        struct delayed_work autoneg_work;
        struct delayed_work ipg_work;
        struct timer_list chase_timer;
        /*
         * these 5 fields are used to establish deltas for IB symbol
         * errors and linkrecovery errors.  They can be reported on
         * some chips during link negotiation prior to INIT, and with
         * DDR when faking DDR negotiations with non-IBTA switches.
         * The chip counters are adjusted at driver unload if there is
         * a non-zero delta.
         */
        u64 ibdeltainprog;
        u64 ibsymdelta;
        u64 ibsymsnap;
        u64 iblnkerrdelta;
        u64 iblnkerrsnap;
        u64 iblnkdownsnap;
        u64 iblnkdowndelta;
        u64 ibmalfdelta;
        u64 ibmalfsnap;
        u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
        u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
        unsigned long qdr_dfe_time;
        unsigned long chase_end;
        u32 autoneg_tries;
        u32 recovery_init;
        u32 qdr_dfe_on;
        u32 qdr_reforce;
        /*
         * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
         * entry zero is unused, to simplify indexing
         */
        u8 h1_val;
        u8 no_eep;  /* txselect table index to use if no qsfp info */
        u8 ipg_tries;
        u8 ibmalfusesnap;
        struct qib_qsfp_data qsfp_data;
        char epmsgbuf[192]; /* for port error interrupt msg buffer */
        char sdmamsgbuf[192]; /* for per-port sdma error messages */
};

static struct {
        const char *name;
        irq_handler_t handler;
        int lsb;
        int port; /* 0 if not port-specific, else port # */
        int dca;
} irq_table[] = {
        { "", qib_7322intr, -1, 0, 0 },
        { " (buf avail)", qib_7322bufavail,
                SYM_LSB(IntStatus, SendBufAvail), 0, 0},
        { " (sdma 0)", sdma_intr,
                SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
        { " (sdma 1)", sdma_intr,
                SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
        { " (sdmaI 0)", sdma_idle_intr,
                SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
        { " (sdmaI 1)", sdma_idle_intr,
                SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
        { " (sdmaP 0)", sdma_progress_intr,
                SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
        { " (sdmaP 1)", sdma_progress_intr,
                SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
        { " (sdmaC 0)", sdma_cleanup_intr,
                SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
        { " (sdmaC 1)", sdma_cleanup_intr,
                SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
};

#ifdef CONFIG_INFINIBAND_QIB_DCA

static const struct dca_reg_map {
        int     shadow_inx;
        int     lsb;
        u64     mask;
        u16     regno;
} dca_rcvhdr_reg_map[] = {
        { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
           ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
        { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
           ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
        { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
           ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
        { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
           ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
        { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
           ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
        { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
           ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
        { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
           ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
        { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
           ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
        { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
           ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
        { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
           ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
        { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
           ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
        { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
           ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
        { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
           ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
        { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
           ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
        { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
           ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
        { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
           ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
        { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
           ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
        { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
           ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
};
#endif

/* ibcctrl bits */
#define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
/* cycle through TS1/TS2 till OK */
#define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
/* wait for TS1, then go on */
#define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
#define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16

#define QLOGIC_IB_IBCC_LINKCMD_DOWN 1           /* move to 0x11 */
#define QLOGIC_IB_IBCC_LINKCMD_ARMED 2          /* move to 0x21 */
#define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */

#define BLOB_7322_IBCHG 0x101

static inline void qib_write_kreg(const struct qib_devdata *dd,
                                  const u32 regno, u64 value);
static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
static void write_7322_initregs(struct qib_devdata *);
static void write_7322_init_portregs(struct qib_pportdata *);
static void setup_7322_link_recovery(struct qib_pportdata *, u32);
static void check_7322_rxe_status(struct qib_pportdata *);
static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
#ifdef CONFIG_INFINIBAND_QIB_DCA
static void qib_setup_dca(struct qib_devdata *dd);
static void setup_dca_notifier(struct qib_devdata *dd, int msixnum);
static void reset_dca_notifier(struct qib_devdata *dd, int msixnum);
#endif

/**
 * qib_read_ureg32 - read 32-bit virtualized per-context register
 * @dd: device
 * @regno: register number
 * @ctxt: context number
 *
 * Return the contents of a register that is virtualized to be per context.
 * Returns -1 on errors (not distinguishable from valid contents at
 * runtime; we may add a separate error variable at some point).
 */
static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
                                  enum qib_ureg regno, int ctxt)
{
        if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
                return 0;
        return readl(regno + (u64 __iomem *)(
                (dd->ureg_align * ctxt) + (dd->userbase ?
                 (char __iomem *)dd->userbase :
                 (char __iomem *)dd->kregbase + dd->uregbase)));
}

/**
 * qib_read_ureg - read virtualized per-context register
 * @dd: device
 * @regno: register number
 * @ctxt: context number
 *
 * Return the contents of a register that is virtualized to be per context.
 * Returns -1 on errors (not distinguishable from valid contents at
 * runtime; we may add a separate error variable at some point).
 */
static inline u64 qib_read_ureg(const struct qib_devdata *dd,
                                enum qib_ureg regno, int ctxt)
{

        if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
                return 0;
        return readq(regno + (u64 __iomem *)(
                (dd->ureg_align * ctxt) + (dd->userbase ?
                 (char __iomem *)dd->userbase :
                 (char __iomem *)dd->kregbase + dd->uregbase)));
}

/**
 * qib_write_ureg - write virtualized per-context register
 * @dd: device
 * @regno: register number
 * @value: value
 * @ctxt: context
 *
 * Write the contents of a register that is virtualized to be per context.
 */
static inline void qib_write_ureg(const struct qib_devdata *dd,
                                  enum qib_ureg regno, u64 value, int ctxt)
{
        u64 __iomem *ubase;

        if (dd->userbase)
                ubase = (u64 __iomem *)
                        ((char __iomem *) dd->userbase +
                         dd->ureg_align * ctxt);
        else
                ubase = (u64 __iomem *)
                        (dd->uregbase +
                         (char __iomem *) dd->kregbase +
                         dd->ureg_align * ctxt);

        if (dd->kregbase && (dd->flags & QIB_PRESENT))
                writeq(value, &ubase[regno]);
}

static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
                                  const u32 regno)
{
        if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
                return -1;
        return readl((u32 __iomem *) &dd->kregbase[regno]);
}

static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
                                  const u32 regno)
{
        if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
                return -1;
        return readq(&dd->kregbase[regno]);
}

static inline void qib_write_kreg(const struct qib_devdata *dd,
                                  const u32 regno, u64 value)
{
        if (dd->kregbase && (dd->flags & QIB_PRESENT))
                writeq(value, &dd->kregbase[regno]);
}

/*
 * not many sanity checks for the port-specific kernel register routines,
 * since they are only used when it's known to be safe.
*/
static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
                                     const u16 regno)
{
        if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
                return 0ULL;
        return readq(&ppd->cpspec->kpregbase[regno]);
}

static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
                                       const u16 regno, u64 value)
{
        if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
            (ppd->dd->flags & QIB_PRESENT))
                writeq(value, &ppd->cpspec->kpregbase[regno]);
}

/**
 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
 * @dd: the qlogic_ib device
 * @regno: the register number to write
 * @ctxt: the context containing the register
 * @value: the value to write
 */
static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
                                       const u16 regno, unsigned ctxt,
                                       u64 value)
{
        qib_write_kreg(dd, regno + ctxt, value);
}

static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
{
        if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
                return 0;
        return readq(&dd->cspec->cregbase[regno]);


}

static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
{
        if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
                return 0;
        return readl(&dd->cspec->cregbase[regno]);


}

static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
                                        u16 regno, u64 value)
{
        if (ppd->cpspec && ppd->cpspec->cpregbase &&
            (ppd->dd->flags & QIB_PRESENT))
                writeq(value, &ppd->cpspec->cpregbase[regno]);
}

static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
                                      u16 regno)
{
        if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
            !(ppd->dd->flags & QIB_PRESENT))
                return 0;
        return readq(&ppd->cpspec->cpregbase[regno]);
}

static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
                                        u16 regno)
{
        if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
            !(ppd->dd->flags & QIB_PRESENT))
                return 0;
        return readl(&ppd->cpspec->cpregbase[regno]);
}

/* bits in Control register */
#define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
#define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)

/* bits in general interrupt regs */
#define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
#define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
#define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
#define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
#define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
#define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
#define QIB_I_C_ERROR INT_MASK(Err)

#define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
#define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
#define QIB_I_GPIO INT_MASK(AssertGPIO)
#define QIB_I_P_SDMAINT(pidx) \
        (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
         INT_MASK_P(SDmaProgress, pidx) | \
         INT_MASK_PM(SDmaCleanupDone, pidx))

/* Interrupt bits that are "per port" */
#define QIB_I_P_BITSEXTANT(pidx) \
        (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
        INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
        INT_MASK_P(SDmaProgress, pidx) | \
        INT_MASK_PM(SDmaCleanupDone, pidx))

/* Interrupt bits that are common to a device */
/* currently unused: QIB_I_SPIOSENT */
#define QIB_I_C_BITSEXTANT \
        (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
        QIB_I_SPIOSENT | \
        QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)

#define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
        QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))

/*
 * Error bits that are "per port".
 */
#define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
#define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
#define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
#define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
#define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
#define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
#define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
#define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
#define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
#define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
#define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
#define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
#define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
#define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
#define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
#define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)

#define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
#define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
#define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
#define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
#define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
#define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
#define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
#define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
#define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
#define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
#define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
#define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)

#define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
#define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
#define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
#define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
#define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
#define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
#define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
#define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
#define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
#define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
#define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)

/* Error bits that are common to a device */
#define QIB_E_RESET ERR_MASK(ResetNegated)
#define QIB_E_HARDWARE ERR_MASK(HardwareErr)
#define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)


/*
 * Per chip (rather than per-port) errors.  Most either do
 * nothing but trigger a print (because they self-recover, or
 * always occur in tandem with other errors that handle the
 * issue), or because they indicate errors with no recovery,
 * but we want to know that they happened.
 */
#define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
#define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
#define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
#define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
#define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
#define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
#define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
#define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)

/* SDMA chip errors (not per port)
 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
 * the SDMAHALT error immediately, so we just print the dup error via the
 * E_AUTO mechanism.  This is true of most of the per-port fatal errors
 * as well, but since this is port-independent, by definition, it's
 * handled a bit differently.  SDMA_VL15 and SDMA_WRONG_PORT are per
 * packet send errors, and so are handled in the same manner as other
 * per-packet errors.
 */
#define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
#define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
#define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)

/*
 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
 * it is used to print "common" packet errors.
 */
#define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
        QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
        QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
        QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
        QIB_E_P_REBP)

/* Error Bits that Packet-related (Receive, per-port) */
#define QIB_E_P_RPKTERRS (\
        QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
        QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
        QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
        QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
        QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
        QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)

/*
 * Error bits that are Send-related (per port)
 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
 * All of these potentially need to have a buffer disarmed
 */
#define QIB_E_P_SPKTERRS (\
        QIB_E_P_SUNEXP_PKTNUM |\
        QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
        QIB_E_P_SMAXPKTLEN |\
        QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
        QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
        QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)

#define QIB_E_SPKTERRS ( \
                QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
                ERR_MASK_N(SendUnsupportedVLErr) |                      \
                QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)

#define QIB_E_P_SDMAERRS ( \
        QIB_E_P_SDMAHALT | \
        QIB_E_P_SDMADESCADDRMISALIGN | \
        QIB_E_P_SDMAUNEXPDATA | \
        QIB_E_P_SDMAMISSINGDW | \
        QIB_E_P_SDMADWEN | \
        QIB_E_P_SDMARPYTAG | \
        QIB_E_P_SDMA1STDESC | \
        QIB_E_P_SDMABASE | \
        QIB_E_P_SDMATAILOUTOFBOUND | \
        QIB_E_P_SDMAOUTOFBOUND | \
        QIB_E_P_SDMAGENMISMATCH)

/*
 * This sets some bits more than once, but makes it more obvious which
 * bits are not handled under other categories, and the repeat definition
 * is not a problem.
 */
#define QIB_E_P_BITSEXTANT ( \
        QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
        QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
        QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
        QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
        )

/*
 * These are errors that can occur when the link
 * changes state while a packet is being sent or received.  This doesn't
 * cover things like EBP or VCRC that can be the result of a sending
 * having the link change state, so we receive a "known bad" packet.
 * All of these are "per port", so renamed:
 */
#define QIB_E_P_LINK_PKTERRS (\
        QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
        QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
        QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
        QIB_E_P_RUNEXPCHAR)

/*
 * This sets some bits more than once, but makes it more obvious which
 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
 * and the repeat definition is not a problem.
 */
#define QIB_E_C_BITSEXTANT (\
        QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
        QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
        QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)

/* Likewise Neuter E_SPKT_ERRS_IGNORE */
#define E_SPKT_ERRS_IGNORE 0

#define QIB_EXTS_MEMBIST_DISABLED \
        SYM_MASK(EXTStatus, MemBISTDisabled)
#define QIB_EXTS_MEMBIST_ENDTEST \
        SYM_MASK(EXTStatus, MemBISTEndTest)

#define QIB_E_SPIOARMLAUNCH \
        ERR_MASK(SendArmLaunchErr)

#define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
#define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)

/*
 * IBTA_1_2 is set when multiple speeds are enabled (normal),
 * and also if forced QDR (only QDR enabled).  It's enabled for the
 * forced QDR case so that scrambling will be enabled by the TS3
 * exchange, when supported by both sides of the link.
 */
#define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
#define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
#define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
#define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
#define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
#define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
        SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
#define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)

#define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
#define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)

#define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
#define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
#define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))

#define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
#define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
#define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
        SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
#define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
        SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
#define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)

#define IBA7322_REDIRECT_VEC_PER_REG 12

#define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
#define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
#define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
#define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
#define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)

#define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */

#define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
        .msg = #fldname , .sz = sizeof(#fldname) }
#define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
        fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
        HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
        HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
        HWE_AUTO(PCIESerdesPClkNotDetect),
        HWE_AUTO(PowerOnBISTFailed),
        HWE_AUTO(TempsenseTholdReached),
        HWE_AUTO(MemoryErr),
        HWE_AUTO(PCIeBusParityErr),
        HWE_AUTO(PcieCplTimeout),
        HWE_AUTO(PciePoisonedTLP),
        HWE_AUTO_P(SDmaMemReadErr, 1),
        HWE_AUTO_P(SDmaMemReadErr, 0),
        HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
        HWE_AUTO_P(IBCBusToSPCParityErr, 1),
        HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
        HWE_AUTO(statusValidNoEop),
        HWE_AUTO(LATriggered),
        { .mask = 0, .sz = 0 }
};

#define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
        .msg = #fldname, .sz = sizeof(#fldname) }
#define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
        .msg = #fldname, .sz = sizeof(#fldname) }
static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
        E_AUTO(RcvEgrFullErr),
        E_AUTO(RcvHdrFullErr),
        E_AUTO(ResetNegated),
        E_AUTO(HardwareErr),
        E_AUTO(InvalidAddrErr),
        E_AUTO(SDmaVL15Err),
        E_AUTO(SBufVL15MisUseErr),
        E_AUTO(InvalidEEPCmd),
        E_AUTO(RcvContextShareErr),
        E_AUTO(SendVLMismatchErr),
        E_AUTO(SendArmLaunchErr),
        E_AUTO(SendSpecialTriggerErr),
        E_AUTO(SDmaWrongPortErr),
        E_AUTO(SDmaBufMaskDuplicateErr),
        { .mask = 0, .sz = 0 }
};

static const struct  qib_hwerror_msgs qib_7322p_error_msgs[] = {
        E_P_AUTO(IBStatusChanged),
        E_P_AUTO(SHeadersErr),
        E_P_AUTO(VL15BufMisuseErr),
        /*
         * SDmaHaltErr is not really an error, make it clearer;
         */
        {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
                .sz = 11},
        E_P_AUTO(SDmaDescAddrMisalignErr),
        E_P_AUTO(SDmaUnexpDataErr),
        E_P_AUTO(SDmaMissingDwErr),
        E_P_AUTO(SDmaDwEnErr),
        E_P_AUTO(SDmaRpyTagErr),
        E_P_AUTO(SDma1stDescErr),
        E_P_AUTO(SDmaBaseErr),
        E_P_AUTO(SDmaTailOutOfBoundErr),
        E_P_AUTO(SDmaOutOfBoundErr),
        E_P_AUTO(SDmaGenMismatchErr),
        E_P_AUTO(SendBufMisuseErr),
        E_P_AUTO(SendUnsupportedVLErr),
        E_P_AUTO(SendUnexpectedPktNumErr),
        E_P_AUTO(SendDroppedDataPktErr),
        E_P_AUTO(SendDroppedSmpPktErr),
        E_P_AUTO(SendPktLenErr),
        E_P_AUTO(SendUnderRunErr),
        E_P_AUTO(SendMaxPktLenErr),
        E_P_AUTO(SendMinPktLenErr),
        E_P_AUTO(RcvIBLostLinkErr),
        E_P_AUTO(RcvHdrErr),
        E_P_AUTO(RcvHdrLenErr),
        E_P_AUTO(RcvBadTidErr),
        E_P_AUTO(RcvBadVersionErr),
        E_P_AUTO(RcvIBFlowErr),
        E_P_AUTO(RcvEBPErr),
        E_P_AUTO(RcvUnsupportedVLErr),
        E_P_AUTO(RcvUnexpectedCharErr),
        E_P_AUTO(RcvShortPktLenErr),
        E_P_AUTO(RcvLongPktLenErr),
        E_P_AUTO(RcvMaxPktLenErr),
        E_P_AUTO(RcvMinPktLenErr),
        E_P_AUTO(RcvICRCErr),
        E_P_AUTO(RcvVCRCErr),
        E_P_AUTO(RcvFormatErr),
        { .mask = 0, .sz = 0 }
};

/*
 * Below generates "auto-message" for interrupts not specific to any port or
 * context
 */
#define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
        .msg = #fldname, .sz = sizeof(#fldname) }
/* Below generates "auto-message" for interrupts specific to a port */
#define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
        SYM_LSB(IntMask, fldname##Mask##_0), \
        SYM_LSB(IntMask, fldname##Mask##_1)), \
        .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
/* For some reason, the SerDesTrimDone bits are reversed */
#define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
        SYM_LSB(IntMask, fldname##Mask##_1), \
        SYM_LSB(IntMask, fldname##Mask##_0)), \
        .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
/*
 * Below generates "auto-message" for interrupts specific to a context,
 * with ctxt-number appended
 */
#define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
        SYM_LSB(IntMask, fldname##0IntMask), \
        SYM_LSB(IntMask, fldname##17IntMask)), \
        .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }

#define TXSYMPTOM_AUTO_P(fldname) \
        { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
        .msg = #fldname, .sz = sizeof(#fldname) }
static const struct  qib_hwerror_msgs hdrchk_msgs[] = {
        TXSYMPTOM_AUTO_P(NonKeyPacket),
        TXSYMPTOM_AUTO_P(GRHFail),
        TXSYMPTOM_AUTO_P(PkeyFail),
        TXSYMPTOM_AUTO_P(QPFail),
        TXSYMPTOM_AUTO_P(SLIDFail),
        TXSYMPTOM_AUTO_P(RawIPV6),
        TXSYMPTOM_AUTO_P(PacketTooSmall),
        { .mask = 0, .sz = 0 }
};

#define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */

/*
 * Called when we might have an error that is specific to a particular
 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
 * because we don't need to force the update of pioavail
 */
static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
{
        struct qib_devdata *dd = ppd->dd;
        u32 i;
        int any;
        u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
        u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
        unsigned long sbuf[4];

        /*
         * It's possible that sendbuffererror could have bits set; might
         * have already done this as a result of hardware error handling.
         */
        any = 0;
        for (i = 0; i < regcnt; ++i) {
                sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
                if (sbuf[i]) {
                        any = 1;
                        qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
                }
        }

        if (any)
                qib_disarm_piobufs_set(dd, sbuf, piobcnt);
}

/* No txe_recover yet, if ever */

/* No decode__errors yet */
static void err_decode(char *msg, size_t len, u64 errs,
                       const struct qib_hwerror_msgs *msp)
{
        u64 these, lmask;
        int took, multi, n = 0;

        while (errs && msp && msp->mask) {
                multi = (msp->mask & (msp->mask - 1));
                while (errs & msp->mask) {
                        these = (errs & msp->mask);
                        lmask = (these & (these - 1)) ^ these;
                        if (len) {
                                if (n++) {
                                        /* separate the strings */
                                        *msg++ = ',';
                                        len--;
                                }
                                /* msp->sz counts the nul */
                                took = min_t(size_t, msp->sz - (size_t)1, len);
                                memcpy(msg,  msp->msg, took);
                                len -= took;
                                msg += took;
                                if (len)
                                        *msg = '\0';
                        }
                        errs &= ~lmask;
                        if (len && multi) {
                                /* More than one bit this mask */
                                int idx = -1;

                                while (lmask & msp->mask) {
                                        ++idx;
                                        lmask >>= 1;
                                }
                                took = scnprintf(msg, len, "_%d", idx);
                                len -= took;
                                msg += took;
                        }
                }
                ++msp;
        }
        /* If some bits are left, show in hex. */
        if (len && errs)
                snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
                        (unsigned long long) errs);
}

/* only called if r1 set */
static void flush_fifo(struct qib_pportdata *ppd)
{
        struct qib_devdata *dd = ppd->dd;
        u32 __iomem *piobuf;
        u32 bufn;
        u32 *hdr;
        u64 pbc;
        const unsigned hdrwords = 7;
        static struct ib_header ibhdr = {
                .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
                .lrh[1] = IB_LID_PERMISSIVE,
                .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
                .lrh[3] = IB_LID_PERMISSIVE,
                .u.oth.bth[0] = cpu_to_be32(
                        (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
                .u.oth.bth[1] = cpu_to_be32(0),
                .u.oth.bth[2] = cpu_to_be32(0),
                .u.oth.u.ud.deth[0] = cpu_to_be32(0),
                .u.oth.u.ud.deth[1] = cpu_to_be32(0),
        };

        /*
         * Send a dummy VL15 packet to flush the launch FIFO.
         * This will not actually be sent since the TxeBypassIbc bit is set.
         */
        pbc = PBC_7322_VL15_SEND |
                (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
                (hdrwords + SIZE_OF_CRC);
        piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
        if (!piobuf)
                return;
        writeq(pbc, piobuf);
        hdr = (u32 *) &ibhdr;
        if (dd->flags & QIB_PIO_FLUSH_WC) {
                qib_flush_wc();
                qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
                qib_flush_wc();
                __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
                qib_flush_wc();
        } else
                qib_pio_copy(piobuf + 2, hdr, hdrwords);
        qib_sendbuf_done(dd, bufn);
}

/*
 * This is called with interrupts disabled and sdma_lock held.
 */
static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
{
        struct qib_devdata *dd = ppd->dd;
        u64 set_sendctrl = 0;
        u64 clr_sendctrl = 0;

        if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
                set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
        else
                clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);

        if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
                set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
        else
                clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);

        if (op & QIB_SDMA_SENDCTRL_OP_HALT)
                set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
        else
                clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);

        if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
                set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
                                SYM_MASK(SendCtrl_0, TxeAbortIbc) |
                                SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
        else
                clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
                                SYM_MASK(SendCtrl_0, TxeAbortIbc) |
                                SYM_MASK(SendCtrl_0, TxeDrainRmFifo);

        spin_lock(&dd->sendctrl_lock);

        /* If we are draining everything, block sends first */
        if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
                ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
                qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
                qib_write_kreg(dd, kr_scratch, 0);
        }

        ppd->p_sendctrl |= set_sendctrl;
        ppd->p_sendctrl &= ~clr_sendctrl;

        if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
                qib_write_kreg_port(ppd, krp_sendctrl,
                                    ppd->p_sendctrl |
                                    SYM_MASK(SendCtrl_0, SDmaCleanup));
        else
                qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
        qib_write_kreg(dd, kr_scratch, 0);

        if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
                ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
                qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
                qib_write_kreg(dd, kr_scratch, 0);
        }

        spin_unlock(&dd->sendctrl_lock);

        if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
                flush_fifo(ppd);
}

static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
{
        __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
}

static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
{
        /*
         * Set SendDmaLenGen and clear and set
         * the MSB of the generation count to enable generation checking
         * and load the internal generation counter.
         */
        qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
        qib_write_kreg_port(ppd, krp_senddmalengen,
                            ppd->sdma_descq_cnt |
                            (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
}

/*
 * Must be called with sdma_lock held, or before init finished.
 */
static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
{
        /* Commit writes to memory and advance the tail on the chip */
        wmb();
        ppd->sdma_descq_tail = tail;
        qib_write_kreg_port(ppd, krp_senddmatail, tail);
}

/*
 * This is called with interrupts disabled and sdma_lock held.
 */
static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
{
        /*
         * Drain all FIFOs.
         * The hardware doesn't require this but we do it so that verbs
         * and user applications don't wait for link active to send stale
         * data.
         */
        sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);

        qib_sdma_7322_setlengen(ppd);
        qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
        ppd->sdma_head_dma[0] = 0;
        qib_7322_sdma_sendctrl(ppd,
                ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
}

#define DISABLES_SDMA ( \
        QIB_E_P_SDMAHALT | \
        QIB_E_P_SDMADESCADDRMISALIGN | \
        QIB_E_P_SDMAMISSINGDW | \
        QIB_E_P_SDMADWEN | \
        QIB_E_P_SDMARPYTAG | \
        QIB_E_P_SDMA1STDESC | \
        QIB_E_P_SDMABASE | \
        QIB_E_P_SDMATAILOUTOFBOUND | \
        QIB_E_P_SDMAOUTOFBOUND | \
        QIB_E_P_SDMAGENMISMATCH)

static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
{
        unsigned long flags;
        struct qib_devdata *dd = ppd->dd;

        errs &= QIB_E_P_SDMAERRS;
        err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf),
                   errs, qib_7322p_error_msgs);

        if (errs & QIB_E_P_SDMAUNEXPDATA)
                qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
                            ppd->port);

        spin_lock_irqsave(&ppd->sdma_lock, flags);

        if (errs != QIB_E_P_SDMAHALT) {
                /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */
                qib_dev_porterr(dd, ppd->port,
                        "SDMA %s 0x%016llx %s\n",
                        qib_sdma_state_names[ppd->sdma_state.current_state],
                        errs, ppd->cpspec->sdmamsgbuf);
                dump_sdma_7322_state(ppd);
        }

        switch (ppd->sdma_state.current_state) {
        case qib_sdma_state_s00_hw_down:
                break;

        case qib_sdma_state_s10_hw_start_up_wait:
                if (errs & QIB_E_P_SDMAHALT)
                        __qib_sdma_process_event(ppd,
                                qib_sdma_event_e20_hw_started);
                break;

        case qib_sdma_state_s20_idle:
                break;

        case qib_sdma_state_s30_sw_clean_up_wait:
                break;

        case qib_sdma_state_s40_hw_clean_up_wait:
                if (errs & QIB_E_P_SDMAHALT)
                        __qib_sdma_process_event(ppd,
                                qib_sdma_event_e50_hw_cleaned);
                break;

        case qib_sdma_state_s50_hw_halt_wait:
                if (errs & QIB_E_P_SDMAHALT)
                        __qib_sdma_process_event(ppd,
                                qib_sdma_event_e60_hw_halted);
                break;

        case qib_sdma_state_s99_running:
                __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
                __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
                break;
        }

        spin_unlock_irqrestore(&ppd->sdma_lock, flags);
}

/*
 * handle per-device errors (not per-port errors)
 */
static noinline void handle_7322_errors(struct qib_devdata *dd)
{
        char *msg;
        u64 iserr = 0;
        u64 errs;
        u64 mask;

        qib_stats.sps_errints++;
        errs = qib_read_kreg64(dd, kr_errstatus);
        if (!errs) {
                qib_devinfo(dd->pcidev,
                        "device error interrupt, but no error bits set!\n");
                goto done;
        }

        /* don't report errors that are masked */
        errs &= dd->cspec->errormask;
        msg = dd->cspec->emsgbuf;

        /* do these first, they are most important */
        if (errs & QIB_E_HARDWARE) {
                *msg = '\0';
                qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
        }

        if (errs & QIB_E_SPKTERRS) {
                qib_disarm_7322_senderrbufs(dd->pport);
                qib_stats.sps_txerrs++;
        } else if (errs & QIB_E_INVALIDADDR)
                qib_stats.sps_txerrs++;
        else if (errs & QIB_E_ARMLAUNCH) {
                qib_stats.sps_txerrs++;
                qib_disarm_7322_senderrbufs(dd->pport);
        }
        qib_write_kreg(dd, kr_errclear, errs);

        /*
         * The ones we mask off are handled specially below
         * or above.  Also mask SDMADISABLED by default as it
         * is too chatty.
         */
        mask = QIB_E_HARDWARE;
        *msg = '\0';

        err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
                   qib_7322error_msgs);

        /*
         * Getting reset is a tragedy for all ports. Mark the device
         * _and_ the ports as "offline" in way meaningful to each.
         */
        if (errs & QIB_E_RESET) {
                int pidx;

                qib_dev_err(dd,
                        "Got reset, requires re-init (unload and reload driver)\n");
                dd->flags &= ~QIB_INITTED;  /* needs re-init */
                /* mark as having had error */
                *dd->devstatusp |= QIB_STATUS_HWERROR;
                for (pidx = 0; pidx < dd->num_pports; ++pidx)
                        if (dd->pport[pidx].link_speed_supported)
                                *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
        }

        if (*msg && iserr)
                qib_dev_err(dd, "%s error\n", msg);

        /*
         * If there were hdrq or egrfull errors, wake up any processes
         * waiting in poll.  We used to try to check which contexts had
         * the overflow, but given the cost of that and the chip reads
         * to support it, it's better to just wake everybody up if we
         * get an overflow; waiters can poll again if it's not them.
         */
        if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
                qib_handle_urcv(dd, ~0U);
                if (errs & ERR_MASK(RcvEgrFullErr))
                        qib_stats.sps_buffull++;
                else
                        qib_stats.sps_hdrfull++;
        }

done:
        return;
}

static void qib_error_tasklet(unsigned long data)
{
        struct qib_devdata *dd = (struct qib_devdata *)data;

        handle_7322_errors(dd);
        qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
}

static void reenable_chase(struct timer_list *t)
{
        struct qib_chippport_specific *cp = from_timer(cp, t, chase_timer);
        struct qib_pportdata *ppd = cp->ppd;

        ppd->cpspec->chase_timer.expires = 0;
        qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
                QLOGIC_IB_IBCC_LINKINITCMD_POLL);
}

static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
                u8 ibclt)
{
        ppd->cpspec->chase_end = 0;

        if (!qib_chase)
                return;

        qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
                QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
        ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
        add_timer(&ppd->cpspec->chase_timer);
}

static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
{
        u8 ibclt;
        unsigned long tnow;

        ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);

        /*
         * Detect and handle the state chase issue, where we can
         * get stuck if we are unlucky on timing on both sides of
         * the link.   If we are, we disable, set a timer, and
         * then re-enable.
         */
        switch (ibclt) {
        case IB_7322_LT_STATE_CFGRCVFCFG:
        case IB_7322_LT_STATE_CFGWAITRMT:
        case IB_7322_LT_STATE_TXREVLANES:
        case IB_7322_LT_STATE_CFGENH:
                tnow = jiffies;
                if (ppd->cpspec->chase_end &&
                     time_after(tnow, ppd->cpspec->chase_end))
                        disable_chase(ppd, tnow, ibclt);
                else if (!ppd->cpspec->chase_end)
                        ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
                break;
        default:
                ppd->cpspec->chase_end = 0;
                break;
        }

        if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
              ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
             ibclt == IB_7322_LT_STATE_LINKUP) &&
            (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
                force_h1(ppd);
                ppd->cpspec->qdr_reforce = 1;
                if (!ppd->dd->cspec->r1)
                        serdes_7322_los_enable(ppd, 0);
        } else if (ppd->cpspec->qdr_reforce &&
                (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
                 (ibclt == IB_7322_LT_STATE_CFGENH ||
                ibclt == IB_7322_LT_STATE_CFGIDLE ||
                ibclt == IB_7322_LT_STATE_LINKUP))
                force_h1(ppd);

        if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
            ppd->link_speed_enabled == QIB_IB_QDR &&
            (ibclt == IB_7322_LT_STATE_CFGTEST ||
             ibclt == IB_7322_LT_STATE_CFGENH ||
             (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
              ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
                adj_tx_serdes(ppd);

        if (ibclt != IB_7322_LT_STATE_LINKUP) {
                u8 ltstate = qib_7322_phys_portstate(ibcst);
                u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
                                          LinkTrainingState);
                if (!ppd->dd->cspec->r1 &&
                    pibclt == IB_7322_LT_STATE_LINKUP &&
                    ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
                    ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
                    ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
                    ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
                        /* If the link went down (but no into recovery,
                         * turn LOS back on */
                        serdes_7322_los_enable(ppd, 1);
                if (!ppd->cpspec->qdr_dfe_on &&
                    ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
                        ppd->cpspec->qdr_dfe_on = 1;
                        ppd->cpspec->qdr_dfe_time = 0;
                        /* On link down, reenable QDR adaptation */
                        qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
                                            ppd->dd->cspec->r1 ?
                                            QDR_STATIC_ADAPT_DOWN_R1 :
                                            QDR_STATIC_ADAPT_DOWN);
                        pr_info(
                                "IB%u:%u re-enabled QDR adaptation ibclt %x\n",
                                ppd->dd->unit, ppd->port, ibclt);
                }
        }
}

static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);

/*
 * This is per-pport error handling.
 * will likely get it's own MSIx interrupt (one for each port,
 * although just a single handler).
 */
static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
{
        char *msg;
        u64 ignore_this_time = 0, iserr = 0, errs, fmask;
        struct qib_devdata *dd = ppd->dd;

        /* do this as soon as possible */
        fmask = qib_read_kreg64(dd, kr_act_fmask);
        if (!fmask)
                check_7322_rxe_status(ppd);

        errs = qib_read_kreg_port(ppd, krp_errstatus);
        if (!errs)
                qib_devinfo(dd->pcidev,
                         "Port%d error interrupt, but no error bits set!\n",
                         ppd->port);
        if (!fmask)
                errs &= ~QIB_E_P_IBSTATUSCHANGED;
        if (!errs)
                goto done;

        msg = ppd->cpspec->epmsgbuf;
        *msg = '\0';

        if (errs & ~QIB_E_P_BITSEXTANT) {
                err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
                           errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
                if (!*msg)
                        snprintf(msg, sizeof(ppd->cpspec->epmsgbuf),
                                 "no others");
                qib_dev_porterr(dd, ppd->port,
                        "error interrupt with unknown errors 0x%016Lx set (and %s)\n",
                        (errs & ~QIB_E_P_BITSEXTANT), msg);
                *msg = '\0';
        }

        if (errs & QIB_E_P_SHDR) {
                u64 symptom;

                /* determine cause, then write to clear */
                symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
                qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
                err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom,
                           hdrchk_msgs);
                *msg = '\0';
                /* senderrbuf cleared in SPKTERRS below */
        }

        if (errs & QIB_E_P_SPKTERRS) {
                if ((errs & QIB_E_P_LINK_PKTERRS) &&
                    !(ppd->lflags & QIBL_LINKACTIVE)) {
                        /*
                         * This can happen when trying to bring the link
                         * up, but the IB link changes state at the "wrong"
                         * time. The IB logic then complains that the packet
                         * isn't valid.  We don't want to confuse people, so
                         * we just don't print them, except at debug
                         */
                        err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
                                   (errs & QIB_E_P_LINK_PKTERRS),
                                   qib_7322p_error_msgs);
                        *msg = '\0';
                        ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
                }
                qib_disarm_7322_senderrbufs(ppd);
        } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
                   !(ppd->lflags & QIBL_LINKACTIVE)) {
                /*
                 * This can happen when SMA is trying to bring the link
                 * up, but the IB link changes state at the "wrong" time.
                 * The IB logic then complains that the packet isn't
                 * valid.  We don't want to confuse people, so we just
                 * don't print them, except at debug
                 */
                err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs,
                           qib_7322p_error_msgs);
                ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
                *msg = '\0';
        }

        qib_write_kreg_port(ppd, krp_errclear, errs);

        errs &= ~ignore_this_time;
        if (!errs)
                goto done;

        if (errs & QIB_E_P_RPKTERRS)
                qib_stats.sps_rcverrs++;
        if (errs & QIB_E_P_SPKTERRS)
                qib_stats.sps_txerrs++;

        iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);

        if (errs & QIB_E_P_SDMAERRS)
                sdma_7322_p_errors(ppd, errs);

        if (errs & QIB_E_P_IBSTATUSCHANGED) {
                u64 ibcs;
                u8 ltstate;

                ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
                ltstate = qib_7322_phys_portstate(ibcs);

                if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
                        handle_serdes_issues(ppd, ibcs);
                if (!(ppd->cpspec->ibcctrl_a &
                      SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
                        /*
                         * We got our interrupt, so init code should be
                         * happy and not try alternatives. Now squelch
                         * other "chatter" from link-negotiation (pre Init)
                         */
                        ppd->cpspec->ibcctrl_a |=
                                SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
                        qib_write_kreg_port(ppd, krp_ibcctrl_a,
                                            ppd->cpspec->ibcctrl_a);
                }

                /* Update our picture of width and speed from chip */
                ppd->link_width_active =
                        (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
                            IB_WIDTH_4X : IB_WIDTH_1X;
                ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
                        LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
                          SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
                                   QIB_IB_DDR : QIB_IB_SDR;

                if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
                    IB_PHYSPORTSTATE_DISABLED)
                        qib_set_ib_7322_lstate(ppd, 0,
                               QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
                else
                        /*
                         * Since going into a recovery state causes the link
                         * state to go down and since recovery is transitory,
                         * it is better if we "miss" ever seeing the link
                         * training state go into recovery (i.e., ignore this
                         * transition for link state special handling purposes)
                         * without updating lastibcstat.
                         */
                        if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
                            ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
                            ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
                            ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)

                                qib_handle_e_ibstatuschanged(ppd, ibcs);
        }
        if (*msg && iserr)
                qib_dev_porterr(dd, ppd->port, "%s error\n", msg);

        if (ppd->state_wanted & ppd->lflags)
                wake_up_interruptible(&ppd->state_wait);
done:
        return;
}

/* enable/disable chip from delivering interrupts */
static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
{
        if (enable) {
                if (dd->flags & QIB_BADINTR)
                        return;
                qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
                /* cause any pending enabled interrupts to be re-delivered */
                qib_write_kreg(dd, kr_intclear, 0ULL);
                if (dd->cspec->num_msix_entries) {
                        /* and same for MSIx */
                        u64 val = qib_read_kreg64(dd, kr_intgranted);

                        if (val)
                                qib_write_kreg(dd, kr_intgranted, val);
                }
        } else
                qib_write_kreg(dd, kr_intmask, 0ULL);
}

/*
 * Try to cleanup as much as possible for anything that might have gone
 * wrong while in freeze mode, such as pio buffers being written by user
 * processes (causing armlaunch), send errors due to going into freeze mode,
 * etc., and try to avoid causing extra interrupts while doing so.
 * Forcibly update the in-memory pioavail register copies after cleanup
 * because the chip won't do it while in freeze mode (the register values
 * themselves are kept correct).
 * Make sure that we don't lose any important interrupts by using the chip
 * feature that says that writing 0 to a bit in *clear that is set in
 * *status will cause an interrupt to be generated again (if allowed by
 * the *mask value).
 * This is in chip-specific code because of all of the register accesses,
 * even though the details are similar on most chips.
 */
static void qib_7322_clear_freeze(struct qib_devdata *dd)
{
        int pidx;

        /* disable error interrupts, to avoid confusion */
        qib_write_kreg(dd, kr_errmask, 0ULL);

        for (pidx = 0; pidx < dd->num_pports; ++pidx)
                if (dd->pport[pidx].link_speed_supported)
                        qib_write_kreg_port(dd->pport + pidx, krp_errmask,
                                            0ULL);

        /* also disable interrupts; errormask is sometimes overwritten */
        qib_7322_set_intr_state(dd, 0);

        /* clear the freeze, and be sure chip saw it */
        qib_write_kreg(dd, kr_control, dd->control);
        qib_read_kreg32(dd, kr_scratch);

        /*
         * Force new interrupt if any hwerr, error or interrupt bits are
         * still set, and clear "safe" send packet errors related to freeze
         * and cancelling sends.  Re-enable error interrupts before possible
         * force of re-interrupt on pending interrupts.
         */
        qib_write_kreg(dd, kr_hwerrclear, 0ULL);
        qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
        qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
        /* We need to purge per-port errs and reset mask, too */
        for (pidx = 0; pidx < dd->num_pports; ++pidx) {
                if (!dd->pport[pidx].link_speed_supported)
                        continue;
                qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
                qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
        }
        qib_7322_set_intr_state(dd, 1);
}

/* no error handling to speak of */
/**
 * qib_7322_handle_hwerrors - display hardware errors.
 * @dd: the qlogic_ib device
 * @msg: the output buffer
 * @msgl: the size of the output buffer
 *
 * Use same msg buffer as regular errors to avoid excessive stack
 * use.  Most hardware errors are catastrophic, but for right now,
 * we'll print them and continue.  We reuse the same message buffer as
 * qib_handle_errors() to avoid excessive stack usage.
 */
static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
                                     size_t msgl)
{
        u64 hwerrs;
        u32 ctrl;
        int isfatal = 0;

        hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
        if (!hwerrs)
                goto bail;
        if (hwerrs == ~0ULL) {
                qib_dev_err(dd,
                        "Read of hardware error status failed (all bits set); ignoring\n");
                goto bail;
        }
        qib_stats.sps_hwerrs++;

        /* Always clear the error status register, except BIST fail */
        qib_write_kreg(dd, kr_hwerrclear, hwerrs &
                       ~HWE_MASK(PowerOnBISTFailed));

        hwerrs &= dd->cspec->hwerrmask;

        /* no EEPROM logging, yet */

        if (hwerrs)
                qib_devinfo(dd->pcidev,
                        "Hardware error: hwerr=0x%llx (cleared)\n",
                        (unsigned long long) hwerrs);

        ctrl = qib_read_kreg32(dd, kr_control);
        if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
                /*
                 * No recovery yet...
                 */
                if ((hwerrs & ~HWE_MASK(LATriggered)) ||
                    dd->cspec->stay_in_freeze) {
                        /*
                         * If any set that we aren't ignoring only make the
                         * complaint once, in case it's stuck or recurring,
                         * and we get here multiple times
                         * Force link down, so switch knows, and
                         * LEDs are turned off.
                         */
                        if (dd->flags & QIB_INITTED)
                                isfatal = 1;
                } else
                        qib_7322_clear_freeze(dd);
        }

        if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
                isfatal = 1;
                strlcpy(msg,
                        "[Memory BIST test failed, InfiniPath hardware unusable]",
                        msgl);
                /* ignore from now on, so disable until driver reloaded */
                dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
                qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
        }

        err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);

        /* Ignore esoteric PLL failures et al. */

        qib_dev_err(dd, "%s hardware error\n", msg);

        if (hwerrs &
                   (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) |
                    SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) {
                int pidx = 0;
                int err;
                unsigned long flags;
                struct qib_pportdata *ppd = dd->pport;

                for (; pidx < dd->num_pports; ++pidx, ppd++) {
                        err = 0;
                        if (pidx == 0 && (hwerrs &
                                SYM_MASK(HwErrMask, SDmaMemReadErrMask_0)))
                                err++;
                        if (pidx == 1 && (hwerrs &
                                SYM_MASK(HwErrMask, SDmaMemReadErrMask_1)))
                                err++;
                        if (err) {
                                spin_lock_irqsave(&ppd->sdma_lock, flags);
                                dump_sdma_7322_state(ppd);
                                spin_unlock_irqrestore(&ppd->sdma_lock, flags);
                        }
                }
        }

        if (isfatal && !dd->diag_client) {
                qib_dev_err(dd,
                        "Fatal Hardware Error, no longer usable, SN %.16s\n",
                        dd->serial);
                /*
                 * for /sys status file and user programs to print; if no
                 * trailing brace is copied, we'll know it was truncated.
                 */
                if (dd->freezemsg)
                        snprintf(dd->freezemsg, dd->freezelen,
                                 "{%s}", msg);
                qib_disable_after_error(dd);
        }
bail:;
}

/**
 * qib_7322_init_hwerrors - enable hardware errors
 * @dd: the qlogic_ib device
 *
 * now that we have finished initializing everything that might reasonably
 * cause a hardware error, and cleared those errors bits as they occur,
 * we can enable hardware errors in the mask (potentially enabling
 * freeze mode), and enable hardware errors as errors (along with
 * everything else) in errormask
 */
static void qib_7322_init_hwerrors(struct qib_devdata *dd)
{
        int pidx;
        u64 extsval;

        extsval = qib_read_kreg64(dd, kr_extstatus);
        if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
                         QIB_EXTS_MEMBIST_ENDTEST)))
                qib_dev_err(dd, "MemBIST did not complete!\n");

        /* never clear BIST failure, so reported on each driver load */
        qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
        qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);

        /* clear all */
        qib_write_kreg(dd, kr_errclear, ~0ULL);
        /* enable errors that are masked, at least this first time. */
        qib_write_kreg(dd, kr_errmask, ~0ULL);
        dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
        for (pidx = 0; pidx < dd->num_pports; ++pidx)
                if (dd->pport[pidx].link_speed_supported)
                        qib_write_kreg_port(dd->pport + pidx, krp_errmask,
                                            ~0ULL);
}

/*
 * Disable and enable the armlaunch error.  Used for PIO bandwidth testing
 * on chips that are count-based, rather than trigger-based.  There is no
 * reference counting, but that's also fine, given the intended use.
 * Only chip-specific because it's all register accesses
 */
static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
{
        if (enable) {
                qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
                dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
        } else
                dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
        qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
}

/*
 * Formerly took parameter <which> in pre-shifted,
 * pre-merged form with LinkCmd and LinkInitCmd
 * together, and assuming the zero was NOP.
 */
static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
                                   u16 linitcmd)
{
        u64 mod_wd;
        struct qib_devdata *dd = ppd->dd;
        unsigned long flags;

        if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
                /*
                 * If we are told to disable, note that so link-recovery
                 * code does not attempt to bring us back up.
                 * Also reset everything that we can, so we start
                 * completely clean when re-enabled (before we
                 * actually issue the disable to the IBC)
                 */
                qib_7322_mini_pcs_reset(ppd);
                spin_lock_irqsave(&ppd->lflags_lock, flags);
                ppd->lflags |= QIBL_IB_LINK_DISABLED;
                spin_unlock_irqrestore(&ppd->lflags_lock, flags);
        } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
                /*
                 * Any other linkinitcmd will lead to LINKDOWN and then
                 * to INIT (if all is well), so clear flag to let
                 * link-recovery code attempt to bring us back up.
                 */
                spin_lock_irqsave(&ppd->lflags_lock, flags);
                ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
                spin_unlock_irqrestore(&ppd->lflags_lock, flags);
                /*
                 * Clear status change interrupt reduction so the
                 * new state is seen.
                 */
                ppd->cpspec->ibcctrl_a &=
                        ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
        }

        mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
                (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);

        qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
                            mod_wd);
        /* write to chip to prevent back-to-back writes of ibc reg */
        qib_write_kreg(dd, kr_scratch, 0);

}

/*
 * The total RCV buffer memory is 64KB, used for both ports, and is
 * in units of 64 bytes (same as IB flow control credit unit).
 * The consumedVL unit in the same registers are in 32 byte units!
 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
 * in krp_rxcreditvl15, rather than 10.
 */
#define RCV_BUF_UNITSZ 64
#define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))

static void set_vls(struct qib_pportdata *ppd)
{
        int i, numvls, totcred, cred_vl, vl0extra;
        struct qib_devdata *dd = ppd->dd;
        u64 val;

        numvls = qib_num_vls(ppd->vls_operational);

        /*
         * Set up per-VL credits. Below is kluge based on these assumptions:
         * 1) port is disabled at the time early_init is called.
         * 2) give VL15 17 credits, for two max-plausible packets.
         * 3) Give VL0-N the rest, with any rounding excess used for VL0
         */
        /* 2 VL15 packets @ 288 bytes each (including IB headers) */
        totcred = NUM_RCV_BUF_UNITS(dd);
        cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
        totcred -= cred_vl;
        qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
        cred_vl = totcred / numvls;
        vl0extra = totcred - cred_vl * numvls;
        qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
        for (i = 1; i < numvls; i++)
                qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
        for (; i < 8; i++) /* no buffer space for other VLs */
                qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);

        /* Notify IBC that credits need to be recalculated */
        val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
        val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
        qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
        qib_write_kreg(dd, kr_scratch, 0ULL);
        val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
        qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);

        for (i = 0; i < numvls; i++)
                val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
        val = qib_read_kreg_port(ppd, krp_rxcreditvl15);

        /* Change the number of operational VLs */
        ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
                                ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
                ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
        qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
        qib_write_kreg(dd, kr_scratch, 0ULL);
}

/*
 * The code that deals with actual SerDes is in serdes_7322_init().
 * Compared to the code for iba7220, it is minimal.
 */
static int serdes_7322_init(struct qib_pportdata *ppd);

/**
 * qib_7322_bringup_serdes - bring up the serdes
 * @ppd: physical port on the qlogic_ib device
 */
static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
{
        struct qib_devdata *dd = ppd->dd;
        u64 val, guid, ibc;
        unsigned long flags;
        int ret = 0;

        /*
         * SerDes model not in Pd, but still need to
         * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
         * eventually.
         */
        /* Put IBC in reset, sends disabled (should be in reset already) */
        ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
        qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
        qib_write_kreg(dd, kr_scratch, 0ULL);

        /* ensure previous Tx parameters are not still forced */
        qib_write_kreg_port(ppd, krp_tx_deemph_override,
                SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
                reset_tx_deemphasis_override));

        if (qib_compat_ddr_negotiate) {
                ppd->cpspec->ibdeltainprog = 1;
                ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
                                                crp_ibsymbolerr);
                ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
                                                crp_iblinkerrrecov);
        }

        /* flowcontrolwatermark is in units of KBytes */
        ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
        /*
         * Flow control is sent this often, even if no changes in
         * buffer space occur.  Units are 128ns for this chip.
         * Set to 3usec.
         */
        ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
        /* max error tolerance */
        ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
        /* IB credit flow control. */
        ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
        /*
         * set initial max size pkt IBC will send, including ICRC; it's the
         * PIO buffer size in dwords, less 1; also see qib_set_mtu()
         */
        ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
                SYM_LSB(IBCCtrlA_0, MaxPktLen);
        ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */

        /*
         * Reset the PCS interface to the serdes (and also ibc, which is still
         * in reset from above).  Writes new value of ibcctrl_a as last step.
         */
        qib_7322_mini_pcs_reset(ppd);

        if (!ppd->cpspec->ibcctrl_b) {
                unsigned lse = ppd->link_speed_enabled;

                /*
                 * Not on re-init after reset, establish shadow
                 * and force initial config.
                 */
                ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
                                                             krp_ibcctrl_b);
                ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
                                IBA7322_IBC_SPEED_DDR |
                                IBA7322_IBC_SPEED_SDR |
                                IBA7322_IBC_WIDTH_AUTONEG |
                                SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
                if (lse & (lse - 1)) /* Muliple speeds enabled */
                        ppd->cpspec->ibcctrl_b |=
                                (lse << IBA7322_IBC_SPEED_LSB) |
                                IBA7322_IBC_IBTA_1_2_MASK |
                                IBA7322_IBC_MAX_SPEED_MASK;
                else
                        ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
                                IBA7322_IBC_SPEED_QDR |
                                 IBA7322_IBC_IBTA_1_2_MASK :
                                (lse == QIB_IB_DDR) ?
                                        IBA7322_IBC_SPEED_DDR :
                                        IBA7322_IBC_SPEED_SDR;
                if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
                    (IB_WIDTH_1X | IB_WIDTH_4X))
                        ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
                else
                        ppd->cpspec->ibcctrl_b |=
                                ppd->link_width_enabled == IB_WIDTH_4X ?
                                IBA7322_IBC_WIDTH_4X_ONLY :
                                IBA7322_IBC_WIDTH_1X_ONLY;

                /* always enable these on driver reload, not sticky */
                ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
                        IBA7322_IBC_HRTBT_MASK);
        }
        qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);

        /* setup so we have more time at CFGTEST to change H1 */
        val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
        val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
        val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
        qib_write_kreg_port(ppd, krp_ibcctrl_c, val);

        serdes_7322_init(ppd);

        guid = be64_to_cpu(ppd->guid);
        if (!guid) {
                if (dd->base_guid)
                        guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
                ppd->guid = cpu_to_be64(guid);
        }

        qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
        /* write to chip to prevent back-to-back writes of ibc reg */
        qib_write_kreg(dd, kr_scratch, 0);

        /* Enable port */
        ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
        set_vls(ppd);

        /* initially come up DISABLED, without sending anything. */
        val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
                                        QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
        qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
        qib_write_kreg(dd, kr_scratch, 0ULL);
        /* clear the linkinit cmds */
        ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);

        /* be paranoid against later code motion, etc. */
        spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
        ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
        qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
        spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);

        /* Also enable IBSTATUSCHG interrupt.  */
        val = qib_read_kreg_port(ppd, krp_errmask);
        qib_write_kreg_port(ppd, krp_errmask,
                val | ERR_MASK_N(IBStatusChanged));

        /* Always zero until we start messing with SerDes for real */
        return ret;
}

/**
 * qib_7322_quiet_serdes - set serdes to txidle
 * @dd: the qlogic_ib device
 * Called when driver is being unloaded
 */
static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
{
        u64 val;
        unsigned long flags;

        qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);

        spin_lock_irqsave(&ppd->lflags_lock, flags);
        ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
        spin_unlock_irqrestore(&ppd->lflags_lock, flags);
        wake_up(&ppd->cpspec->autoneg_wait);
        cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
        if (ppd->dd->cspec->r1)
                cancel_delayed_work_sync(&ppd->cpspec->ipg_work);

        ppd->cpspec->chase_end = 0;
        if (ppd->cpspec->chase_timer.function) /* if initted */
                del_timer_sync(&ppd->cpspec->chase_timer);

        /*
         * Despite the name, actually disables IBC as well. Do it when
         * we are as sure as possible that no more packets can be
         * received, following the down and the PCS reset.
         * The actual disabling happens in qib_7322_mini_pci_reset(),
         * along with the PCS being reset.
         */
        ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
        qib_7322_mini_pcs_reset(ppd);

        /*
         * Update the adjusted counters so the adjustment persists
         * across driver reload.
         */
        if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
            ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
                struct qib_devdata *dd = ppd->dd;
                u64 diagc;

                /* enable counter writes */
                diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
                qib_write_kreg(dd, kr_hwdiagctrl,
                               diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));

                if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
                        val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
                        if (ppd->cpspec->ibdeltainprog)
                                val -= val - ppd->cpspec->ibsymsnap;
                        val -= ppd->cpspec->ibsymdelta;
                        write_7322_creg_port(ppd, crp_ibsymbolerr, val);
                }
                if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
                        val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
                        if (ppd->cpspec->ibdeltainprog)
                                val -= val - ppd->cpspec->iblnkerrsnap;
                        val -= ppd->cpspec->iblnkerrdelta;
                        write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
                }
                if (ppd->cpspec->iblnkdowndelta) {
                        val = read_7322_creg32_port(ppd, crp_iblinkdown);
                        val += ppd->cpspec->iblnkdowndelta;
                        write_7322_creg_port(ppd, crp_iblinkdown, val);
                }
                /*
                 * No need to save ibmalfdelta since IB perfcounters
                 * are cleared on driver reload.
                 */

                /* and disable counter writes */
                qib_write_kreg(dd, kr_hwdiagctrl, diagc);
        }
}

/**
 * qib_setup_7322_setextled - set the state of the two external LEDs
 * @ppd: physical port on the qlogic_ib device
 * @on: whether the link is up or not
 *
 * The exact combo of LEDs if on is true is determined by looking
 * at the ibcstatus.
 *
 * These LEDs indicate the physical and logical state of IB link.
 * For this chip (at least with recommended board pinouts), LED1
 * is Yellow (logical state) and LED2 is Green (physical state),
 *
 * Note:  We try to match the Mellanox HCA LED behavior as best
 * we can.  Green indicates physical link state is OK (something is
 * plugged in, and we can train).
 * Amber indicates the link is logically up (ACTIVE).
 * Mellanox further blinks the amber LED to indicate data packet
 * activity, but we have no hardware support for that, so it would
 * require waking up every 10-20 msecs and checking the counters
 * on the chip, and then turning the LED off if appropriate.  That's
 * visible overhead, so not something we will do.
 */
static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
{
        struct qib_devdata *dd = ppd->dd;
        u64 extctl, ledblink = 0, val;
        unsigned long flags;
        int yel, grn;

        /*
         * The diags use the LED to indicate diag info, so we leave
         * the external LED alone when the diags are running.
         */
        if (dd->diag_client)
                return;

        /* Allow override of LED display for, e.g. Locating system in rack */
        if (ppd->led_override) {
                grn = (ppd->led_override & QIB_LED_PHYS);
                yel = (ppd->led_override & QIB_LED_LOG);
        } else if (on) {
                val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
                grn = qib_7322_phys_portstate(val) ==
                        IB_PHYSPORTSTATE_LINKUP;
                yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
        } else {
                grn = 0;
                yel = 0;
        }

        spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
        extctl = dd->cspec->extctrl & (ppd->port == 1 ?
                ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
        if (grn) {
                extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
                /*
                 * Counts are in chip clock (4ns) periods.
                 * This is 1/16 sec (66.6ms) on,
                 * 3/16 sec (187.5 ms) off, with packets rcvd.
                 */
                ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
                        ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
        }
        if (yel)
                extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
        dd->cspec->extctrl = extctl;
        qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
        spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);

        if (ledblink) /* blink the LED on packet receive */
                qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
}

#ifdef CONFIG_INFINIBAND_QIB_DCA

static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event)
{
        switch (event) {
        case DCA_PROVIDER_ADD:
                if (dd->flags & QIB_DCA_ENABLED)
                        break;
                if (!dca_add_requester(&dd->pcidev->dev)) {
                        qib_devinfo(dd->pcidev, "DCA enabled\n");
                        dd->flags |= QIB_DCA_ENABLED;
                        qib_setup_dca(dd);
                }
                break;
        case DCA_PROVIDER_REMOVE:
                if (dd->flags & QIB_DCA_ENABLED) {
                        dca_remove_requester(&dd->pcidev->dev);
                        dd->flags &= ~QIB_DCA_ENABLED;
                        dd->cspec->dca_ctrl = 0;
                        qib_write_kreg(dd, KREG_IDX(DCACtrlA),
                                dd->cspec->dca_ctrl);
                }
                break;
        }
        return 0;
}

static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu)
{
        struct qib_devdata *dd = rcd->dd;
        struct qib_chip_specific *cspec = dd->cspec;

        if (!(dd->flags & QIB_DCA_ENABLED))
                return;
        if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
                const struct dca_reg_map *rmp;

                cspec->rhdr_cpu[rcd->ctxt] = cpu;
                rmp = &dca_rcvhdr_reg_map[rcd->ctxt];
                cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
                cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
                        (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb;
                qib_devinfo(dd->pcidev,
                        "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu,
                        (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
                qib_write_kreg(dd, rmp->regno,
                               cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
                cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
                qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
        }
}

static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu)
{
        struct qib_devdata *dd = ppd->dd;
        struct qib_chip_specific *cspec = dd->cspec;
        unsigned pidx = ppd->port - 1;

        if (!(dd->flags & QIB_DCA_ENABLED))
                return;
        if (cspec->sdma_cpu[pidx] != cpu) {
                cspec->sdma_cpu[pidx] = cpu;
                cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
                        SYM_MASK(DCACtrlF, SendDma1DCAOPH) :
                        SYM_MASK(DCACtrlF, SendDma0DCAOPH));
                cspec->dca_rcvhdr_ctrl[4] |=
                        (u64) dca3_get_tag(&dd->pcidev->dev, cpu) <<
                                (ppd->hw_pidx ?
                                        SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
                                        SYM_LSB(DCACtrlF, SendDma0DCAOPH));
                qib_devinfo(dd->pcidev,
                        "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu,
                        (long long) cspec->dca_rcvhdr_ctrl[4]);
                qib_write_kreg(dd, KREG_IDX(DCACtrlF),
                               cspec->dca_rcvhdr_ctrl[4]);
                cspec->dca_ctrl |= ppd->hw_pidx ?
                        SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) :
                        SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable);
                qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
        }
}

static void qib_setup_dca(struct qib_devdata *dd)
{
        struct qib_chip_specific *cspec = dd->cspec;
        int i;

        for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
                cspec->rhdr_cpu[i] = -1;
        for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
                cspec->sdma_cpu[i] = -1;
        cspec->dca_rcvhdr_ctrl[0] =
                (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
        cspec->dca_rcvhdr_ctrl[1] =
                (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
        cspec->dca_rcvhdr_ctrl[2] =
                (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
        cspec->dca_rcvhdr_ctrl[3] =
                (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
        cspec->dca_rcvhdr_ctrl[4] =
                (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
                (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
        for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
                qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
                               cspec->dca_rcvhdr_ctrl[i]);
        for (i = 0; i < cspec->num_msix_entries; i++)
                setup_dca_notifier(dd, i);
}

static void qib_irq_notifier_notify(struct irq_affinity_notify *notify,
                             const cpumask_t *mask)
{
        struct qib_irq_notify *n =
                container_of(notify, struct qib_irq_notify, notify);
        int cpu = cpumask_first(mask);

        if (n->rcv) {
                struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;

                qib_update_rhdrq_dca(rcd, cpu);
        } else {
                struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;

                qib_update_sdma_dca(ppd, cpu);
        }
}

static void qib_irq_notifier_release(struct kref *ref)
{
        struct qib_irq_notify *n =
                container_of(ref, struct qib_irq_notify, notify.kref);
        struct qib_devdata *dd;

        if (n->rcv) {
                struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;

                dd = rcd->dd;
        } else {
                struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;

                dd = ppd->dd;
        }
        qib_devinfo(dd->pcidev,
                "release on HCA notify 0x%p n 0x%p\n", ref, n);
        kfree(n);
}
#endif

static void qib_7322_free_irq(struct qib_devdata *dd)
{
        u64 intgranted;
        int i;

        dd->cspec->main_int_mask = ~0ULL;

        for (i = 0; i < dd->cspec->num_msix_entries; i++) {
                /* only free IRQs that were allocated */
                if (dd->cspec->msix_entries[i].arg) {
#ifdef CONFIG_INFINIBAND_QIB_DCA
                        reset_dca_notifier(dd, i);
#endif
                        irq_set_affinity_hint(pci_irq_vector(dd->pcidev, i),
                                              NULL);
                        free_cpumask_var(dd->cspec->msix_entries[i].mask);
                        pci_free_irq(dd->pcidev, i,
                                     dd->cspec->msix_entries[i].arg);
                }
        }

        /* If num_msix_entries was 0, disable the INTx IRQ */
        if (!dd->cspec->num_msix_entries)
                pci_free_irq(dd->pcidev, 0, dd);
        else
                dd->cspec->num_msix_entries = 0;

        pci_free_irq_vectors(dd->pcidev);

        /* make sure no MSIx interrupts are left pending */
        intgranted = qib_read_kreg64(dd, kr_intgranted);
        if (intgranted)
                qib_write_kreg(dd, kr_intgranted, intgranted);
}

static void qib_setup_7322_cleanup(struct qib_devdata *dd)
{
        int i;

#ifdef CONFIG_INFINIBAND_QIB_DCA
        if (dd->flags & QIB_DCA_ENABLED) {
                dca_remove_requester(&dd->pcidev->dev);
                dd->flags &= ~QIB_DCA_ENABLED;
                dd->cspec->dca_ctrl = 0;
                qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
        }
#endif

        qib_7322_free_irq(dd);
        kfree(dd->cspec->cntrs);
        kfree(dd->cspec->sendchkenable);
        kfree(dd->cspec->sendgrhchk);
        kfree(dd->cspec->sendibchk);
        kfree(dd->cspec->msix_entries);
        for (i = 0; i < dd->num_pports; i++) {
                unsigned long flags;
                u32 mask = QSFP_GPIO_MOD_PRS_N |
                        (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);

                kfree(dd->pport[i].cpspec->portcntrs);
                if (dd->flags & QIB_HAS_QSFP) {
                        spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
                        dd->cspec->gpio_mask &= ~mask;
                        qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
                        spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
                }
        }
}

/* handle SDMA interrupts */
static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
{
        struct qib_pportdata *ppd0 = &dd->pport[0];
        struct qib_pportdata *ppd1 = &dd->pport[1];
        u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
                INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
        u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
                INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));

        if (intr0)
                qib_sdma_intr(ppd0);
        if (intr1)
                qib_sdma_intr(ppd1);

        if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
                qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
        if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
                qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
}

/*
 * Set or clear the Send buffer available interrupt enable bit.
 */
static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
{
        unsigned long flags;

        spin_lock_irqsave(&dd->sendctrl_lock, flags);
        if (needint)
                dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
        else
                dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
        qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
        qib_write_kreg(dd, kr_scratch, 0ULL);
        spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
}

/*
 * Somehow got an interrupt with reserved bits set in interrupt status.
 * Print a message so we know it happened, then clear them.
 * keep mainline interrupt handler cache-friendly
 */
static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
{
        u64 kills;
        char msg[128];

        kills = istat & ~QIB_I_BITSEXTANT;
        qib_dev_err(dd,
                "Clearing reserved interrupt(s) 0x%016llx: %s\n",
                (unsigned long long) kills, msg);
        qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
}

/* keep mainline interrupt handler cache-friendly */
static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
{
        u32 gpiostatus;
        int handled = 0;
        int pidx;

        /*
         * Boards for this chip currently don't use GPIO interrupts,
         * so clear by writing GPIOstatus to GPIOclear, and complain
         * to developer.  To avoid endless repeats, clear
         * the bits in the mask, since there is some kind of
         * programming error or chip problem.
         */
        gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
        /*
         * In theory, writing GPIOstatus to GPIOclear could
         * have a bad side-effect on some diagnostic that wanted
         * to poll for a status-change, but the various shadows
         * make that problematic at best. Diags will just suppress
         * all GPIO interrupts during such tests.
         */
        qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
        /*
         * Check for QSFP MOD_PRS changes
         * only works for single port if IB1 != pidx1
         */
        for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
             ++pidx) {
                struct qib_pportdata *ppd;
                struct qib_qsfp_data *qd;
                u32 mask;

                if (!dd->pport[pidx].link_speed_supported)
                        continue;
                mask = QSFP_GPIO_MOD_PRS_N;
                ppd = dd->pport + pidx;
                mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
                if (gpiostatus & dd->cspec->gpio_mask & mask) {
                        u64 pins;

                        qd = &ppd->cpspec->qsfp_data;
                        gpiostatus &= ~mask;
                        pins = qib_read_kreg64(dd, kr_extstatus);
                        pins >>= SYM_LSB(EXTStatus, GPIOIn);
                        if (!(pins & mask)) {
                                ++handled;
                                qd->t_insert = jiffies;
                                queue_work(ib_wq, &qd->work);
                        }
                }