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10#ifndef _OMAP_IOMMU_H
11#define _OMAP_IOMMU_H
12
13#include <linux/bitops.h>
14#include <linux/iommu.h>
15
16#define for_each_iotlb_cr(obj, n, __i, cr) \
17 for (__i = 0; \
18 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
19 __i++)
20
21struct iotlb_entry {
22 u32 da;
23 u32 pa;
24 u32 pgsz, prsvd, valid;
25 u32 endian, elsz, mixed;
26};
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32
33struct omap_iommu_device {
34 u32 *pgtable;
35 struct omap_iommu *iommu_dev;
36};
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44
45
46struct omap_iommu_domain {
47 u32 num_iommus;
48 struct omap_iommu_device *iommus;
49 struct device *dev;
50 spinlock_t lock;
51 struct iommu_domain domain;
52};
53
54struct omap_iommu {
55 const char *name;
56 void __iomem *regbase;
57 struct regmap *syscfg;
58 struct device *dev;
59 struct iommu_domain *domain;
60 struct dentry *debug_dir;
61
62 spinlock_t iommu_lock;
63
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67
68 u32 *iopgd;
69 spinlock_t page_table_lock;
70 dma_addr_t pd_dma;
71
72 int nr_tlb_entries;
73
74 void *ctx;
75
76 int has_bus_err_back;
77 u32 id;
78
79 struct iommu_device iommu;
80 struct iommu_group *group;
81};
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91
92struct omap_iommu_arch_data {
93 struct omap_iommu *iommu_dev;
94};
95
96struct cr_regs {
97 u32 cam;
98 u32 ram;
99};
100
101struct iotlb_lock {
102 short base;
103 short vict;
104};
105
106
107
108
109#define MMU_REVISION 0x00
110#define MMU_IRQSTATUS 0x18
111#define MMU_IRQENABLE 0x1c
112#define MMU_WALKING_ST 0x40
113#define MMU_CNTL 0x44
114#define MMU_FAULT_AD 0x48
115#define MMU_TTB 0x4c
116#define MMU_LOCK 0x50
117#define MMU_LD_TLB 0x54
118#define MMU_CAM 0x58
119#define MMU_RAM 0x5c
120#define MMU_GFLUSH 0x60
121#define MMU_FLUSH_ENTRY 0x64
122#define MMU_READ_CAM 0x68
123#define MMU_READ_RAM 0x6c
124#define MMU_EMU_FAULT_AD 0x70
125#define MMU_GP_REG 0x88
126
127#define MMU_REG_SIZE 256
128
129
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131
132
133#define MMU_IRQ_MULTIHITFAULT BIT(4)
134#define MMU_IRQ_TABLEWALKFAULT BIT(3)
135#define MMU_IRQ_EMUMISS BIT(2)
136#define MMU_IRQ_TRANSLATIONFAULT BIT(1)
137#define MMU_IRQ_TLBMISS BIT(0)
138
139#define __MMU_IRQ_FAULT \
140 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
141#define MMU_IRQ_MASK \
142 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
143#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
144#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
145
146
147#define MMU_CNTL_SHIFT 1
148#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
149#define MMU_CNTL_EML_TLB BIT(3)
150#define MMU_CNTL_TWL_EN BIT(2)
151#define MMU_CNTL_MMU_EN BIT(1)
152
153
154#define MMU_CAM_VATAG_SHIFT 12
155#define MMU_CAM_VATAG_MASK \
156 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
157#define MMU_CAM_P BIT(3)
158#define MMU_CAM_V BIT(2)
159#define MMU_CAM_PGSZ_MASK 3
160#define MMU_CAM_PGSZ_1M (0 << 0)
161#define MMU_CAM_PGSZ_64K (1 << 0)
162#define MMU_CAM_PGSZ_4K (2 << 0)
163#define MMU_CAM_PGSZ_16M (3 << 0)
164
165
166#define MMU_RAM_PADDR_SHIFT 12
167#define MMU_RAM_PADDR_MASK \
168 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
169
170#define MMU_RAM_ENDIAN_SHIFT 9
171#define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
172#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
173#define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
174
175#define MMU_RAM_ELSZ_SHIFT 7
176#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
177#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
178#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
179#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
180#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
181#define MMU_RAM_MIXED_SHIFT 6
182#define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
183#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
184
185#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
186
187#define get_cam_va_mask(pgsz) \
188 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
189 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
190 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
191 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
192
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195
196#define DSP_SYS_REVISION 0x00
197#define DSP_SYS_MMU_CONFIG 0x18
198#define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
199
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203
204#define iopgsz_max(bytes) \
205 (((bytes) >= SZ_16M) ? SZ_16M : \
206 ((bytes) >= SZ_1M) ? SZ_1M : \
207 ((bytes) >= SZ_64K) ? SZ_64K : \
208 ((bytes) >= SZ_4K) ? SZ_4K : 0)
209
210#define bytes_to_iopgsz(bytes) \
211 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
212 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
213 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
214 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
215
216#define iopgsz_to_bytes(iopgsz) \
217 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
218 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
219 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
220 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
221
222#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
223
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227
228struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
229void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
230void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
231
232#ifdef CONFIG_OMAP_IOMMU_DEBUG
233void omap_iommu_debugfs_init(void);
234void omap_iommu_debugfs_exit(void);
235
236void omap_iommu_debugfs_add(struct omap_iommu *obj);
237void omap_iommu_debugfs_remove(struct omap_iommu *obj);
238#else
239static inline void omap_iommu_debugfs_init(void) { }
240static inline void omap_iommu_debugfs_exit(void) { }
241
242static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
243static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
244#endif
245
246
247
248
249static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
250{
251 return __raw_readl(obj->regbase + offs);
252}
253
254static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
255{
256 __raw_writel(val, obj->regbase + offs);
257}
258
259static inline int iotlb_cr_valid(struct cr_regs *cr)
260{
261 if (!cr)
262 return -EINVAL;
263
264 return cr->cam & MMU_CAM_V;
265}
266
267#endif
268
