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8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/irqchip.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#define NUM_CHANNEL 8
20#define MAX_INPUT_MUX 256
21
22#define REG_EDGE_POL 0x00
23#define REG_PIN_03_SEL 0x04
24#define REG_PIN_47_SEL 0x08
25#define REG_FILTER_SEL 0x0c
26
27#define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x)))
28#define REG_EDGE_POL_EDGE(x) BIT(x)
29#define REG_EDGE_POL_LOW(x) BIT(16 + (x))
30#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
31#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
32
33struct meson_gpio_irq_params {
34 unsigned int nr_hwirq;
35};
36
37static const struct meson_gpio_irq_params meson8_params = {
38 .nr_hwirq = 134,
39};
40
41static const struct meson_gpio_irq_params meson8b_params = {
42 .nr_hwirq = 119,
43};
44
45static const struct meson_gpio_irq_params gxbb_params = {
46 .nr_hwirq = 133,
47};
48
49static const struct meson_gpio_irq_params gxl_params = {
50 .nr_hwirq = 110,
51};
52
53static const struct meson_gpio_irq_params axg_params = {
54 .nr_hwirq = 100,
55};
56
57static const struct of_device_id meson_irq_gpio_matches[] = {
58 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
59 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
60 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
61 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
62 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
63 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
64 { }
65};
66
67struct meson_gpio_irq_controller {
68 unsigned int nr_hwirq;
69 void __iomem *base;
70 u32 channel_irqs[NUM_CHANNEL];
71 DECLARE_BITMAP(channel_map, NUM_CHANNEL);
72 spinlock_t lock;
73};
74
75static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
76 unsigned int reg, u32 mask, u32 val)
77{
78 u32 tmp;
79
80 tmp = readl_relaxed(ctl->base + reg);
81 tmp &= ~mask;
82 tmp |= val;
83 writel_relaxed(tmp, ctl->base + reg);
84}
85
86static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
87{
88 return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
89}
90
91static int
92meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
93 unsigned long hwirq,
94 u32 **channel_hwirq)
95{
96 unsigned int reg, idx;
97
98 spin_lock(&ctl->lock);
99
100
101 idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
102 if (idx >= NUM_CHANNEL) {
103 spin_unlock(&ctl->lock);
104 pr_err("No channel available\n");
105 return -ENOSPC;
106 }
107
108
109 set_bit(idx, ctl->channel_map);
110
111
112
113
114
115 reg = meson_gpio_irq_channel_to_reg(idx);
116 meson_gpio_irq_update_bits(ctl, reg,
117 0xff << REG_PIN_SEL_SHIFT(idx),
118 hwirq << REG_PIN_SEL_SHIFT(idx));
119
120
121
122
123
124
125
126 *channel_hwirq = &(ctl->channel_irqs[idx]);
127
128 spin_unlock(&ctl->lock);
129
130 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
131 hwirq, idx, **channel_hwirq);
132
133 return 0;
134}
135
136static unsigned int
137meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
138 u32 *channel_hwirq)
139{
140 return channel_hwirq - ctl->channel_irqs;
141}
142
143static void
144meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
145 u32 *channel_hwirq)
146{
147 unsigned int idx;
148
149 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
150 clear_bit(idx, ctl->channel_map);
151}
152
153static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
154 unsigned int type,
155 u32 *channel_hwirq)
156{
157 u32 val = 0;
158 unsigned int idx;
159
160 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
161
162
163
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165
166
167
168
169 type &= IRQ_TYPE_SENSE_MASK;
170
171 if (type == IRQ_TYPE_EDGE_BOTH)
172 return -EINVAL;
173
174 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
175 val |= REG_EDGE_POL_EDGE(idx);
176
177 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
178 val |= REG_EDGE_POL_LOW(idx);
179
180 spin_lock(&ctl->lock);
181
182 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
183 REG_EDGE_POL_MASK(idx), val);
184
185 spin_unlock(&ctl->lock);
186
187 return 0;
188}
189
190static unsigned int meson_gpio_irq_type_output(unsigned int type)
191{
192 unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
193
194 type &= ~IRQ_TYPE_SENSE_MASK;
195
196
197
198
199
200 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
201 type |= IRQ_TYPE_LEVEL_HIGH;
202 else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
203 type |= IRQ_TYPE_EDGE_RISING;
204
205 return type;
206}
207
208static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
209{
210 struct meson_gpio_irq_controller *ctl = data->domain->host_data;
211 u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
212 int ret;
213
214 ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
215 if (ret)
216 return ret;
217
218 return irq_chip_set_type_parent(data,
219 meson_gpio_irq_type_output(type));
220}
221
222static struct irq_chip meson_gpio_irq_chip = {
223 .name = "meson-gpio-irqchip",
224 .irq_mask = irq_chip_mask_parent,
225 .irq_unmask = irq_chip_unmask_parent,
226 .irq_eoi = irq_chip_eoi_parent,
227 .irq_set_type = meson_gpio_irq_set_type,
228 .irq_retrigger = irq_chip_retrigger_hierarchy,
229#ifdef CONFIG_SMP
230 .irq_set_affinity = irq_chip_set_affinity_parent,
231#endif
232 .flags = IRQCHIP_SET_TYPE_MASKED,
233};
234
235static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
236 struct irq_fwspec *fwspec,
237 unsigned long *hwirq,
238 unsigned int *type)
239{
240 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
241 *hwirq = fwspec->param[0];
242 *type = fwspec->param[1];
243 return 0;
244 }
245
246 return -EINVAL;
247}
248
249static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
250 unsigned int virq,
251 u32 hwirq,
252 unsigned int type)
253{
254 struct irq_fwspec fwspec;
255
256 fwspec.fwnode = domain->parent->fwnode;
257 fwspec.param_count = 3;
258 fwspec.param[0] = 0;
259 fwspec.param[1] = hwirq;
260 fwspec.param[2] = meson_gpio_irq_type_output(type);
261
262 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
263}
264
265static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
266 unsigned int virq,
267 unsigned int nr_irqs,
268 void *data)
269{
270 struct irq_fwspec *fwspec = data;
271 struct meson_gpio_irq_controller *ctl = domain->host_data;
272 unsigned long hwirq;
273 u32 *channel_hwirq;
274 unsigned int type;
275 int ret;
276
277 if (WARN_ON(nr_irqs != 1))
278 return -EINVAL;
279
280 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
281 if (ret)
282 return ret;
283
284 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
285 if (ret)
286 return ret;
287
288 ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
289 *channel_hwirq, type);
290 if (ret < 0) {
291 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
292 meson_gpio_irq_release_channel(ctl, channel_hwirq);
293 return ret;
294 }
295
296 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
297 &meson_gpio_irq_chip, channel_hwirq);
298
299 return 0;
300}
301
302static void meson_gpio_irq_domain_free(struct irq_domain *domain,
303 unsigned int virq,
304 unsigned int nr_irqs)
305{
306 struct meson_gpio_irq_controller *ctl = domain->host_data;
307 struct irq_data *irq_data;
308 u32 *channel_hwirq;
309
310 if (WARN_ON(nr_irqs != 1))
311 return;
312
313 irq_domain_free_irqs_parent(domain, virq, 1);
314
315 irq_data = irq_domain_get_irq_data(domain, virq);
316 channel_hwirq = irq_data_get_irq_chip_data(irq_data);
317
318 meson_gpio_irq_release_channel(ctl, channel_hwirq);
319}
320
321static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
322 .alloc = meson_gpio_irq_domain_alloc,
323 .free = meson_gpio_irq_domain_free,
324 .translate = meson_gpio_irq_domain_translate,
325};
326
327static int __init meson_gpio_irq_parse_dt(struct device_node *node,
328 struct meson_gpio_irq_controller *ctl)
329{
330 const struct of_device_id *match;
331 const struct meson_gpio_irq_params *params;
332 int ret;
333
334 match = of_match_node(meson_irq_gpio_matches, node);
335 if (!match)
336 return -ENODEV;
337
338 params = match->data;
339 ctl->nr_hwirq = params->nr_hwirq;
340
341 ret = of_property_read_variable_u32_array(node,
342 "amlogic,channel-interrupts",
343 ctl->channel_irqs,
344 NUM_CHANNEL,
345 NUM_CHANNEL);
346 if (ret < 0) {
347 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
348 return ret;
349 }
350
351 return 0;
352}
353
354static int __init meson_gpio_irq_of_init(struct device_node *node,
355 struct device_node *parent)
356{
357 struct irq_domain *domain, *parent_domain;
358 struct meson_gpio_irq_controller *ctl;
359 int ret;
360
361 if (!parent) {
362 pr_err("missing parent interrupt node\n");
363 return -ENODEV;
364 }
365
366 parent_domain = irq_find_host(parent);
367 if (!parent_domain) {
368 pr_err("unable to obtain parent domain\n");
369 return -ENXIO;
370 }
371
372 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
373 if (!ctl)
374 return -ENOMEM;
375
376 spin_lock_init(&ctl->lock);
377
378 ctl->base = of_iomap(node, 0);
379 if (!ctl->base) {
380 ret = -ENOMEM;
381 goto free_ctl;
382 }
383
384 ret = meson_gpio_irq_parse_dt(node, ctl);
385 if (ret)
386 goto free_channel_irqs;
387
388 domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq,
389 of_node_to_fwnode(node),
390 &meson_gpio_irq_domain_ops,
391 ctl);
392 if (!domain) {
393 pr_err("failed to add domain\n");
394 ret = -ENODEV;
395 goto free_channel_irqs;
396 }
397
398 pr_info("%d to %d gpio interrupt mux initialized\n",
399 ctl->nr_hwirq, NUM_CHANNEL);
400
401 return 0;
402
403free_channel_irqs:
404 iounmap(ctl->base);
405free_ctl:
406 kfree(ctl);
407
408 return ret;
409}
410
411IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
412 meson_gpio_irq_of_init);
413
