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14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21
22#include <media/dvb_frontend.h>
23#include "mt312_priv.h"
24#include "mt312.h"
25
26
27#define MAX_XFER_SIZE 64
28
29struct mt312_state {
30 struct i2c_adapter *i2c;
31
32 const struct mt312_config *config;
33 struct dvb_frontend frontend;
34
35 u8 id;
36 unsigned long xtal;
37 u8 freq_mult;
38};
39
40static int debug;
41#define dprintk(args...) \
42 do { \
43 if (debug) \
44 printk(KERN_DEBUG "mt312: " args); \
45 } while (0)
46
47#define MT312_PLL_CLK 10000000UL
48#define MT312_PLL_CLK_10_111 10111000UL
49
50static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
51 u8 *buf, const size_t count)
52{
53 int ret;
54 struct i2c_msg msg[2];
55 u8 regbuf[1] = { reg };
56
57 msg[0].addr = state->config->demod_address;
58 msg[0].flags = 0;
59 msg[0].buf = regbuf;
60 msg[0].len = 1;
61 msg[1].addr = state->config->demod_address;
62 msg[1].flags = I2C_M_RD;
63 msg[1].buf = buf;
64 msg[1].len = count;
65
66 ret = i2c_transfer(state->i2c, msg, 2);
67
68 if (ret != 2) {
69 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
70 return -EREMOTEIO;
71 }
72
73 if (debug) {
74 int i;
75 dprintk("R(%d):", reg & 0x7f);
76 for (i = 0; i < count; i++)
77 printk(KERN_CONT " %02x", buf[i]);
78 printk("\n");
79 }
80
81 return 0;
82}
83
84static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
85 const u8 *src, const size_t count)
86{
87 int ret;
88 u8 buf[MAX_XFER_SIZE];
89 struct i2c_msg msg;
90
91 if (1 + count > sizeof(buf)) {
92 printk(KERN_WARNING
93 "mt312: write: len=%zu is too big!\n", count);
94 return -EINVAL;
95 }
96
97 if (debug) {
98 int i;
99 dprintk("W(%d):", reg & 0x7f);
100 for (i = 0; i < count; i++)
101 printk(KERN_CONT " %02x", src[i]);
102 printk("\n");
103 }
104
105 buf[0] = reg;
106 memcpy(&buf[1], src, count);
107
108 msg.addr = state->config->demod_address;
109 msg.flags = 0;
110 msg.buf = buf;
111 msg.len = count + 1;
112
113 ret = i2c_transfer(state->i2c, &msg, 1);
114
115 if (ret != 1) {
116 dprintk("%s: ret == %d\n", __func__, ret);
117 return -EREMOTEIO;
118 }
119
120 return 0;
121}
122
123static inline int mt312_readreg(struct mt312_state *state,
124 const enum mt312_reg_addr reg, u8 *val)
125{
126 return mt312_read(state, reg, val, 1);
127}
128
129static inline int mt312_writereg(struct mt312_state *state,
130 const enum mt312_reg_addr reg, const u8 val)
131{
132 u8 tmp = val;
133
134
135 return mt312_write(state, reg, &tmp, 1);
136}
137
138static inline u32 mt312_div(u32 a, u32 b)
139{
140 return (a + (b / 2)) / b;
141}
142
143static int mt312_reset(struct mt312_state *state, const u8 full)
144{
145 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
146}
147
148static int mt312_get_inversion(struct mt312_state *state,
149 enum fe_spectral_inversion *i)
150{
151 int ret;
152 u8 vit_mode;
153
154 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
155 if (ret < 0)
156 return ret;
157
158 if (vit_mode & 0x80)
159 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
160
161 return 0;
162}
163
164static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
165{
166 int ret;
167 u8 sym_rate_h;
168 u8 dec_ratio;
169 u16 sym_rat_op;
170 u16 monitor;
171 u8 buf[2];
172
173 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
174 if (ret < 0)
175 return ret;
176
177 if (sym_rate_h & 0x80) {
178
179 ret = mt312_writereg(state, MON_CTRL, 0x03);
180 if (ret < 0)
181 return ret;
182
183 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
184 if (ret < 0)
185 return ret;
186
187 monitor = (buf[0] << 8) | buf[1];
188
189 dprintk("sr(auto) = %u\n",
190 mt312_div(monitor * 15625, 4));
191 } else {
192 ret = mt312_writereg(state, MON_CTRL, 0x05);
193 if (ret < 0)
194 return ret;
195
196 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
197 if (ret < 0)
198 return ret;
199
200 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
201
202 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
203 if (ret < 0)
204 return ret;
205
206 sym_rat_op = (buf[0] << 8) | buf[1];
207
208 dprintk("sym_rat_op=%d dec_ratio=%d\n",
209 sym_rat_op, dec_ratio);
210 dprintk("*sr(manual) = %lu\n",
211 (((state->xtal * 8192) / (sym_rat_op + 8192)) *
212 2) - dec_ratio);
213 }
214
215 return 0;
216}
217
218static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
219{
220 const enum fe_code_rate fec_tab[8] =
221 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
222 FEC_AUTO, FEC_AUTO };
223
224 int ret;
225 u8 fec_status;
226
227 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
228 if (ret < 0)
229 return ret;
230
231 *cr = fec_tab[(fec_status >> 4) & 0x07];
232
233 return 0;
234}
235
236static int mt312_initfe(struct dvb_frontend *fe)
237{
238 struct mt312_state *state = fe->demodulator_priv;
239 int ret;
240 u8 buf[2];
241
242
243 ret = mt312_writereg(state, CONFIG,
244 (state->freq_mult == 6 ? 0x88 : 0x8c));
245 if (ret < 0)
246 return ret;
247
248
249 udelay(150);
250
251
252 ret = mt312_reset(state, 1);
253 if (ret < 0)
254 return ret;
255
256
257
258 {
259 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
260 0x01, 0x00, 0x00, 0x00 };
261
262 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
263 if (ret < 0)
264 return ret;
265 }
266
267 switch (state->id) {
268 case ID_ZL10313:
269
270 ret = mt312_writereg(state, GPP_CTRL, 0x80);
271 if (ret < 0)
272 return ret;
273
274
275 buf[0] = 0x80;
276 buf[1] = 0xB0;
277 ret = mt312_write(state, HW_CTRL, buf, 2);
278 if (ret < 0)
279 return ret;
280
281
282 ret = mt312_writereg(state, HW_CTRL, 0x00);
283 if (ret < 0)
284 return ret;
285
286 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
287 if (ret < 0)
288 return ret;
289
290 break;
291 }
292
293
294 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
295
296
297 buf[1] = mt312_div(state->xtal, 22000 * 4);
298
299 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
300 if (ret < 0)
301 return ret;
302
303 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
304 if (ret < 0)
305 return ret;
306
307
308 switch (state->id) {
309 case ID_ZL10313:
310 buf[0] = 0x33;
311 break;
312 default:
313 buf[0] = 0x53;
314 break;
315 }
316
317 ret = mt312_writereg(state, OP_CTRL, buf[0]);
318 if (ret < 0)
319 return ret;
320
321
322 buf[0] = 0x8c;
323 buf[1] = 0x98;
324
325 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
326 if (ret < 0)
327 return ret;
328
329 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
330 if (ret < 0)
331 return ret;
332
333 return 0;
334}
335
336static int mt312_send_master_cmd(struct dvb_frontend *fe,
337 struct dvb_diseqc_master_cmd *c)
338{
339 struct mt312_state *state = fe->demodulator_priv;
340 int ret;
341 u8 diseqc_mode;
342
343 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
344 return -EINVAL;
345
346 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
347 if (ret < 0)
348 return ret;
349
350 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
351 if (ret < 0)
352 return ret;
353
354 ret = mt312_writereg(state, DISEQC_MODE,
355 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
356 | 0x04);
357 if (ret < 0)
358 return ret;
359
360
361 msleep(100);
362
363
364 if (c->msg[0] & 0x02) {
365 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
366 if (ret < 0)
367 return ret;
368 }
369
370 return 0;
371}
372
373static int mt312_send_burst(struct dvb_frontend *fe,
374 const enum fe_sec_mini_cmd c)
375{
376 struct mt312_state *state = fe->demodulator_priv;
377 const u8 mini_tab[2] = { 0x02, 0x03 };
378
379 int ret;
380 u8 diseqc_mode;
381
382 if (c > SEC_MINI_B)
383 return -EINVAL;
384
385 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
386 if (ret < 0)
387 return ret;
388
389 ret = mt312_writereg(state, DISEQC_MODE,
390 (diseqc_mode & 0x40) | mini_tab[c]);
391 if (ret < 0)
392 return ret;
393
394 return 0;
395}
396
397static int mt312_set_tone(struct dvb_frontend *fe,
398 const enum fe_sec_tone_mode t)
399{
400 struct mt312_state *state = fe->demodulator_priv;
401 const u8 tone_tab[2] = { 0x01, 0x00 };
402
403 int ret;
404 u8 diseqc_mode;
405
406 if (t > SEC_TONE_OFF)
407 return -EINVAL;
408
409 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
410 if (ret < 0)
411 return ret;
412
413 ret = mt312_writereg(state, DISEQC_MODE,
414 (diseqc_mode & 0x40) | tone_tab[t]);
415 if (ret < 0)
416 return ret;
417
418 return 0;
419}
420
421static int mt312_set_voltage(struct dvb_frontend *fe,
422 const enum fe_sec_voltage v)
423{
424 struct mt312_state *state = fe->demodulator_priv;
425 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
426 u8 val;
427
428 if (v > SEC_VOLTAGE_OFF)
429 return -EINVAL;
430
431 val = volt_tab[v];
432 if (state->config->voltage_inverted)
433 val ^= 0x40;
434
435 return mt312_writereg(state, DISEQC_MODE, val);
436}
437
438static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
439{
440 struct mt312_state *state = fe->demodulator_priv;
441 int ret;
442 u8 status[3];
443
444 *s = 0;
445
446 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
447 if (ret < 0)
448 return ret;
449
450 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n",
451 status[0], status[1], status[2]);
452
453 if (status[0] & 0xc0)
454 *s |= FE_HAS_SIGNAL;
455 if (status[0] & 0x04)
456 *s |= FE_HAS_CARRIER;
457 if (status[2] & 0x02)
458 *s |= FE_HAS_VITERBI;
459 if (status[2] & 0x04)
460 *s |= FE_HAS_SYNC;
461 if (status[0] & 0x01)
462 *s |= FE_HAS_LOCK;
463
464 return 0;
465}
466
467static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
468{
469 struct mt312_state *state = fe->demodulator_priv;
470 int ret;
471 u8 buf[3];
472
473 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
474 if (ret < 0)
475 return ret;
476
477 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
478
479 return 0;
480}
481
482static int mt312_read_signal_strength(struct dvb_frontend *fe,
483 u16 *signal_strength)
484{
485 struct mt312_state *state = fe->demodulator_priv;
486 int ret;
487 u8 buf[3];
488 u16 agc;
489 s16 err_db;
490
491 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
492 if (ret < 0)
493 return ret;
494
495 agc = (buf[0] << 6) | (buf[1] >> 2);
496 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
497
498 *signal_strength = agc;
499
500 dprintk("agc=%08x err_db=%hd\n", agc, err_db);
501
502 return 0;
503}
504
505static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
506{
507 struct mt312_state *state = fe->demodulator_priv;
508 int ret;
509 u8 buf[2];
510
511 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
512 if (ret < 0)
513 return ret;
514
515 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
516
517 return 0;
518}
519
520static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
521{
522 struct mt312_state *state = fe->demodulator_priv;
523 int ret;
524 u8 buf[2];
525
526 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
527 if (ret < 0)
528 return ret;
529
530 *ubc = (buf[0] << 8) | buf[1];
531
532 return 0;
533}
534
535static int mt312_set_frontend(struct dvb_frontend *fe)
536{
537 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
538 struct mt312_state *state = fe->demodulator_priv;
539 int ret;
540 u8 buf[5], config_val;
541 u16 sr;
542
543 const u8 fec_tab[10] =
544 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
545 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
546
547 dprintk("%s: Freq %d\n", __func__, p->frequency);
548
549 if ((p->frequency < fe->ops.info.frequency_min_hz / kHz)
550 || (p->frequency > fe->ops.info.frequency_max_hz / kHz))
551 return -EINVAL;
552
553 if (((int)p->inversion < INVERSION_OFF)
554 || (p->inversion > INVERSION_ON))
555 return -EINVAL;
556
557 if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
558 || (p->symbol_rate > fe->ops.info.symbol_rate_max))
559 return -EINVAL;
560
561 if (((int)p->fec_inner < FEC_NONE)
562 || (p->fec_inner > FEC_AUTO))
563 return -EINVAL;
564
565 if ((p->fec_inner == FEC_4_5)
566 || (p->fec_inner == FEC_8_9))
567 return -EINVAL;
568
569 switch (state->id) {
570 case ID_VP310:
571
572
573
574
575 ret = mt312_readreg(state, CONFIG, &config_val);
576 if (ret < 0)
577 return ret;
578 if (p->symbol_rate >= 30000000) {
579
580 if (state->freq_mult == 6) {
581
582 state->freq_mult = 9;
583 ret = mt312_initfe(fe);
584 if (ret < 0)
585 return ret;
586 }
587 } else {
588 if (state->freq_mult == 9) {
589
590 state->freq_mult = 6;
591 ret = mt312_initfe(fe);
592 if (ret < 0)
593 return ret;
594 }
595 }
596 break;
597
598 case ID_MT312:
599 case ID_ZL10313:
600 break;
601
602 default:
603 return -EINVAL;
604 }
605
606 if (fe->ops.tuner_ops.set_params) {
607 fe->ops.tuner_ops.set_params(fe);
608 if (fe->ops.i2c_gate_ctrl)
609 fe->ops.i2c_gate_ctrl(fe, 0);
610 }
611
612
613 sr = mt312_div(p->symbol_rate * 4, 15625);
614
615
616 buf[0] = (sr >> 8) & 0x3f;
617 buf[1] = (sr >> 0) & 0xff;
618
619
620 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
621
622
623 buf[3] = 0x40;
624
625 if (p->symbol_rate < 10000000)
626 buf[3] |= 0x04;
627
628
629 buf[4] = 0x01;
630
631 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
632 if (ret < 0)
633 return ret;
634
635 ret = mt312_reset(state, 0);
636 if (ret < 0)
637 return ret;
638
639 return 0;
640}
641
642static int mt312_get_frontend(struct dvb_frontend *fe,
643 struct dtv_frontend_properties *p)
644{
645 struct mt312_state *state = fe->demodulator_priv;
646 int ret;
647
648 ret = mt312_get_inversion(state, &p->inversion);
649 if (ret < 0)
650 return ret;
651
652 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
653 if (ret < 0)
654 return ret;
655
656 ret = mt312_get_code_rate(state, &p->fec_inner);
657 if (ret < 0)
658 return ret;
659
660 return 0;
661}
662
663static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
664{
665 struct mt312_state *state = fe->demodulator_priv;
666
667 u8 val = 0x00;
668 int ret;
669
670 switch (state->id) {
671 case ID_ZL10313:
672 ret = mt312_readreg(state, GPP_CTRL, &val);
673 if (ret < 0)
674 goto error;
675
676
677 val &= 0x80;
678 break;
679 }
680
681 if (enable)
682 val |= 0x40;
683 else
684 val &= ~0x40;
685
686 ret = mt312_writereg(state, GPP_CTRL, val);
687
688error:
689 return ret;
690}
691
692static int mt312_sleep(struct dvb_frontend *fe)
693{
694 struct mt312_state *state = fe->demodulator_priv;
695 int ret;
696 u8 config;
697
698
699 ret = mt312_reset(state, 1);
700 if (ret < 0)
701 return ret;
702
703 if (state->id == ID_ZL10313) {
704
705 ret = mt312_writereg(state, GPP_CTRL, 0x00);
706 if (ret < 0)
707 return ret;
708
709
710 ret = mt312_writereg(state, HW_CTRL, 0x0d);
711 if (ret < 0)
712 return ret;
713 }
714
715 ret = mt312_readreg(state, CONFIG, &config);
716 if (ret < 0)
717 return ret;
718
719
720 ret = mt312_writereg(state, CONFIG, config & 0x7f);
721 if (ret < 0)
722 return ret;
723
724 return 0;
725}
726
727static int mt312_get_tune_settings(struct dvb_frontend *fe,
728 struct dvb_frontend_tune_settings *fesettings)
729{
730 fesettings->min_delay_ms = 50;
731 fesettings->step_size = 0;
732 fesettings->max_drift = 0;
733 return 0;
734}
735
736static void mt312_release(struct dvb_frontend *fe)
737{
738 struct mt312_state *state = fe->demodulator_priv;
739 kfree(state);
740}
741
742#define MT312_SYS_CLK 90000000UL
743static const struct dvb_frontend_ops mt312_ops = {
744 .delsys = { SYS_DVBS },
745 .info = {
746 .name = "Zarlink ???? DVB-S",
747 .frequency_min_hz = 950 * MHz,
748 .frequency_max_hz = 2150 * MHz,
749
750 .frequency_stepsize_hz = MT312_PLL_CLK / 128,
751 .symbol_rate_min = MT312_SYS_CLK / 128,
752 .symbol_rate_max = MT312_SYS_CLK / 2,
753 .caps =
754 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
755 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
756 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
757 FE_CAN_RECOVER
758 },
759
760 .release = mt312_release,
761
762 .init = mt312_initfe,
763 .sleep = mt312_sleep,
764 .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
765
766 .set_frontend = mt312_set_frontend,
767 .get_frontend = mt312_get_frontend,
768 .get_tune_settings = mt312_get_tune_settings,
769
770 .read_status = mt312_read_status,
771 .read_ber = mt312_read_ber,
772 .read_signal_strength = mt312_read_signal_strength,
773 .read_snr = mt312_read_snr,
774 .read_ucblocks = mt312_read_ucblocks,
775
776 .diseqc_send_master_cmd = mt312_send_master_cmd,
777 .diseqc_send_burst = mt312_send_burst,
778 .set_tone = mt312_set_tone,
779 .set_voltage = mt312_set_voltage,
780};
781
782struct dvb_frontend *mt312_attach(const struct mt312_config *config,
783 struct i2c_adapter *i2c)
784{
785 struct mt312_state *state = NULL;
786
787
788 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
789 if (state == NULL)
790 goto error;
791
792
793 state->config = config;
794 state->i2c = i2c;
795
796
797 if (mt312_readreg(state, ID, &state->id) < 0)
798 goto error;
799
800
801 memcpy(&state->frontend.ops, &mt312_ops,
802 sizeof(struct dvb_frontend_ops));
803 state->frontend.demodulator_priv = state;
804
805 switch (state->id) {
806 case ID_VP310:
807 strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S",
808 sizeof(state->frontend.ops.info.name));
809 state->xtal = MT312_PLL_CLK;
810 state->freq_mult = 9;
811 break;
812 case ID_MT312:
813 strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S",
814 sizeof(state->frontend.ops.info.name));
815 state->xtal = MT312_PLL_CLK;
816 state->freq_mult = 6;
817 break;
818 case ID_ZL10313:
819 strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S",
820 sizeof(state->frontend.ops.info.name));
821 state->xtal = MT312_PLL_CLK_10_111;
822 state->freq_mult = 9;
823 break;
824 default:
825 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n");
826 goto error;
827 }
828
829 return &state->frontend;
830
831error:
832 kfree(state);
833 return NULL;
834}
835EXPORT_SYMBOL(mt312_attach);
836
837module_param(debug, int, 0644);
838MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
839
840MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
841MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
842MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
843MODULE_LICENSE("GPL");
844
845
