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12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/gpio/consumer.h>
15#include <linux/i2c.h>
16#include <linux/log2.h>
17#include <linux/mutex.h>
18#include <linux/of.h>
19#include <linux/of_graph.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22#include <linux/videodev2.h>
23#include <linux/v4l2-mediabus.h>
24#include <linux/module.h>
25
26#include <media/i2c/mt9v032.h>
27#include <media/v4l2-ctrls.h>
28#include <media/v4l2-device.h>
29#include <media/v4l2-fwnode.h>
30#include <media/v4l2-subdev.h>
31
32
33#define MT9V032_PIXEL_ARRAY_HEIGHT 485
34#define MT9V032_PIXEL_ARRAY_WIDTH 753
35
36#define MT9V032_SYSCLK_FREQ_DEF 26600000
37
38#define MT9V032_CHIP_VERSION 0x00
39#define MT9V032_CHIP_ID_REV1 0x1311
40#define MT9V032_CHIP_ID_REV3 0x1313
41#define MT9V034_CHIP_ID_REV1 0X1324
42#define MT9V032_COLUMN_START 0x01
43#define MT9V032_COLUMN_START_MIN 1
44#define MT9V032_COLUMN_START_DEF 1
45#define MT9V032_COLUMN_START_MAX 752
46#define MT9V032_ROW_START 0x02
47#define MT9V032_ROW_START_MIN 4
48#define MT9V032_ROW_START_DEF 5
49#define MT9V032_ROW_START_MAX 482
50#define MT9V032_WINDOW_HEIGHT 0x03
51#define MT9V032_WINDOW_HEIGHT_MIN 1
52#define MT9V032_WINDOW_HEIGHT_DEF 480
53#define MT9V032_WINDOW_HEIGHT_MAX 480
54#define MT9V032_WINDOW_WIDTH 0x04
55#define MT9V032_WINDOW_WIDTH_MIN 1
56#define MT9V032_WINDOW_WIDTH_DEF 752
57#define MT9V032_WINDOW_WIDTH_MAX 752
58#define MT9V032_HORIZONTAL_BLANKING 0x05
59#define MT9V032_HORIZONTAL_BLANKING_MIN 43
60#define MT9V034_HORIZONTAL_BLANKING_MIN 61
61#define MT9V032_HORIZONTAL_BLANKING_DEF 94
62#define MT9V032_HORIZONTAL_BLANKING_MAX 1023
63#define MT9V032_VERTICAL_BLANKING 0x06
64#define MT9V032_VERTICAL_BLANKING_MIN 4
65#define MT9V034_VERTICAL_BLANKING_MIN 2
66#define MT9V032_VERTICAL_BLANKING_DEF 45
67#define MT9V032_VERTICAL_BLANKING_MAX 3000
68#define MT9V034_VERTICAL_BLANKING_MAX 32288
69#define MT9V032_CHIP_CONTROL 0x07
70#define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
71#define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
72#define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
73#define MT9V032_SHUTTER_WIDTH1 0x08
74#define MT9V032_SHUTTER_WIDTH2 0x09
75#define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
76#define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
77#define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
78#define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
79#define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
80#define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
81#define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
82#define MT9V032_RESET 0x0c
83#define MT9V032_READ_MODE 0x0d
84#define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
85#define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
86#define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
87#define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
88#define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
89#define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
90#define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
91#define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
92#define MT9V032_READ_MODE_RESERVED 0x0300
93#define MT9V032_PIXEL_OPERATION_MODE 0x0f
94#define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
95#define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
96#define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
97#define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
98#define MT9V032_ANALOG_GAIN 0x35
99#define MT9V032_ANALOG_GAIN_MIN 16
100#define MT9V032_ANALOG_GAIN_DEF 16
101#define MT9V032_ANALOG_GAIN_MAX 64
102#define MT9V032_MAX_ANALOG_GAIN 0x36
103#define MT9V032_MAX_ANALOG_GAIN_MAX 127
104#define MT9V032_FRAME_DARK_AVERAGE 0x42
105#define MT9V032_DARK_AVG_THRESH 0x46
106#define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
107#define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
108#define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
109#define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
110#define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
111#define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
112#define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
113#define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
114#define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
115#define MT9V032_PIXEL_CLOCK 0x74
116#define MT9V034_PIXEL_CLOCK 0x72
117#define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
118#define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
119#define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
120#define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
121#define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
122#define MT9V032_TEST_PATTERN 0x7f
123#define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
124#define MT9V032_TEST_PATTERN_DATA_SHIFT 0
125#define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
126#define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
127#define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
128#define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
129#define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
130#define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
131#define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
132#define MT9V032_TEST_PATTERN_FLIP (1 << 14)
133#define MT9V032_AEGC_DESIRED_BIN 0xa5
134#define MT9V032_AEC_UPDATE_FREQUENCY 0xa6
135#define MT9V032_AEC_LPF 0xa8
136#define MT9V032_AGC_UPDATE_FREQUENCY 0xa9
137#define MT9V032_AGC_LPF 0xaa
138#define MT9V032_AEC_AGC_ENABLE 0xaf
139#define MT9V032_AEC_ENABLE (1 << 0)
140#define MT9V032_AGC_ENABLE (1 << 1)
141#define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad
142#define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd
143#define MT9V032_THERMAL_INFO 0xc1
144
145enum mt9v032_model {
146 MT9V032_MODEL_V022_COLOR,
147 MT9V032_MODEL_V022_MONO,
148 MT9V032_MODEL_V024_COLOR,
149 MT9V032_MODEL_V024_MONO,
150 MT9V032_MODEL_V032_COLOR,
151 MT9V032_MODEL_V032_MONO,
152 MT9V032_MODEL_V034_COLOR,
153 MT9V032_MODEL_V034_MONO,
154};
155
156struct mt9v032_model_version {
157 unsigned int version;
158 const char *name;
159};
160
161struct mt9v032_model_data {
162 unsigned int min_row_time;
163 unsigned int min_hblank;
164 unsigned int min_vblank;
165 unsigned int max_vblank;
166 unsigned int min_shutter;
167 unsigned int max_shutter;
168 unsigned int pclk_reg;
169 unsigned int aec_max_shutter_reg;
170 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
171};
172
173struct mt9v032_model_info {
174 const struct mt9v032_model_data *data;
175 bool color;
176};
177
178static const struct mt9v032_model_version mt9v032_versions[] = {
179 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
180 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
181 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
182};
183
184struct mt9v032 {
185 struct v4l2_subdev subdev;
186 struct media_pad pad;
187
188 struct v4l2_mbus_framefmt format;
189 struct v4l2_rect crop;
190 unsigned int hratio;
191 unsigned int vratio;
192
193 struct v4l2_ctrl_handler ctrls;
194 struct {
195 struct v4l2_ctrl *link_freq;
196 struct v4l2_ctrl *pixel_rate;
197 };
198
199 struct mutex power_lock;
200 int power_count;
201
202 struct regmap *regmap;
203 struct clk *clk;
204 struct gpio_desc *reset_gpio;
205 struct gpio_desc *standby_gpio;
206
207 struct mt9v032_platform_data *pdata;
208 const struct mt9v032_model_info *model;
209 const struct mt9v032_model_version *version;
210
211 u32 sysclk;
212 u16 aec_agc;
213 u16 hblank;
214 struct {
215 struct v4l2_ctrl *test_pattern;
216 struct v4l2_ctrl *test_pattern_color;
217 };
218};
219
220static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
221{
222 return container_of(sd, struct mt9v032, subdev);
223}
224
225static int
226mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
227{
228 struct regmap *map = mt9v032->regmap;
229 u16 value = mt9v032->aec_agc;
230 int ret;
231
232 if (enable)
233 value |= which;
234 else
235 value &= ~which;
236
237 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
238 if (ret < 0)
239 return ret;
240
241 mt9v032->aec_agc = value;
242 return 0;
243}
244
245static int
246mt9v032_update_hblank(struct mt9v032 *mt9v032)
247{
248 struct v4l2_rect *crop = &mt9v032->crop;
249 unsigned int min_hblank = mt9v032->model->data->min_hblank;
250 unsigned int hblank;
251
252 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
253 min_hblank += (mt9v032->hratio - 1) * 10;
254 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
255 min_hblank);
256 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
257
258 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
259 hblank);
260}
261
262static int mt9v032_power_on(struct mt9v032 *mt9v032)
263{
264 struct regmap *map = mt9v032->regmap;
265 int ret;
266
267 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
268
269 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
270 if (ret < 0)
271 return ret;
272
273
274 ret = clk_prepare_enable(mt9v032->clk);
275 if (ret)
276 return ret;
277
278 udelay(1);
279
280 if (mt9v032->reset_gpio) {
281 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
282
283
284
285
286
287
288 udelay(1);
289 }
290
291
292 ret = regmap_write(map, MT9V032_RESET, 1);
293 if (ret < 0)
294 goto err;
295
296 ret = regmap_write(map, MT9V032_RESET, 0);
297 if (ret < 0)
298 goto err;
299
300 ret = regmap_write(map, MT9V032_CHIP_CONTROL,
301 MT9V032_CHIP_CONTROL_MASTER_MODE);
302 if (ret < 0)
303 goto err;
304
305 return 0;
306
307err:
308 clk_disable_unprepare(mt9v032->clk);
309 return ret;
310}
311
312static void mt9v032_power_off(struct mt9v032 *mt9v032)
313{
314 clk_disable_unprepare(mt9v032->clk);
315}
316
317static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
318{
319 struct regmap *map = mt9v032->regmap;
320 int ret;
321
322 if (!on) {
323 mt9v032_power_off(mt9v032);
324 return 0;
325 }
326
327 ret = mt9v032_power_on(mt9v032);
328 if (ret < 0)
329 return ret;
330
331
332 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
333 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
334 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
335 if (ret < 0)
336 return ret;
337 }
338
339
340 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
341 if (ret < 0)
342 return ret;
343
344 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
345}
346
347
348
349
350
351static struct v4l2_mbus_framefmt *
352__mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
353 unsigned int pad, enum v4l2_subdev_format_whence which)
354{
355 switch (which) {
356 case V4L2_SUBDEV_FORMAT_TRY:
357 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad);
358 case V4L2_SUBDEV_FORMAT_ACTIVE:
359 return &mt9v032->format;
360 default:
361 return NULL;
362 }
363}
364
365static struct v4l2_rect *
366__mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
367 unsigned int pad, enum v4l2_subdev_format_whence which)
368{
369 switch (which) {
370 case V4L2_SUBDEV_FORMAT_TRY:
371 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad);
372 case V4L2_SUBDEV_FORMAT_ACTIVE:
373 return &mt9v032->crop;
374 default:
375 return NULL;
376 }
377}
378
379static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
380{
381 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
382 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
383 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
384 struct v4l2_rect *crop = &mt9v032->crop;
385 struct regmap *map = mt9v032->regmap;
386 unsigned int hbin;
387 unsigned int vbin;
388 int ret;
389
390 if (!enable)
391 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
392
393
394 hbin = fls(mt9v032->hratio) - 1;
395 vbin = fls(mt9v032->vratio) - 1;
396 ret = regmap_update_bits(map, MT9V032_READ_MODE,
397 ~MT9V032_READ_MODE_RESERVED,
398 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
399 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
400 if (ret < 0)
401 return ret;
402
403 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
404 if (ret < 0)
405 return ret;
406
407 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
408 if (ret < 0)
409 return ret;
410
411 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
412 if (ret < 0)
413 return ret;
414
415 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
416 if (ret < 0)
417 return ret;
418
419 ret = mt9v032_update_hblank(mt9v032);
420 if (ret < 0)
421 return ret;
422
423
424 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
425}
426
427static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
428 struct v4l2_subdev_pad_config *cfg,
429 struct v4l2_subdev_mbus_code_enum *code)
430{
431 if (code->index > 0)
432 return -EINVAL;
433
434 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
435 return 0;
436}
437
438static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
439 struct v4l2_subdev_pad_config *cfg,
440 struct v4l2_subdev_frame_size_enum *fse)
441{
442 if (fse->index >= 3 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
443 return -EINVAL;
444
445 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
446 fse->max_width = fse->min_width;
447 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
448 fse->max_height = fse->min_height;
449
450 return 0;
451}
452
453static int mt9v032_get_format(struct v4l2_subdev *subdev,
454 struct v4l2_subdev_pad_config *cfg,
455 struct v4l2_subdev_format *format)
456{
457 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
458
459 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad,
460 format->which);
461 return 0;
462}
463
464static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
465{
466 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
467 int ret;
468
469 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
470 mt9v032->sysclk / mt9v032->hratio);
471 if (ret < 0)
472 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
473}
474
475static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
476{
477
478
479
480
481 if (output * 3 > input * 2)
482 return 1;
483 if (output * 3 > input)
484 return 2;
485 return 4;
486}
487
488static int mt9v032_set_format(struct v4l2_subdev *subdev,
489 struct v4l2_subdev_pad_config *cfg,
490 struct v4l2_subdev_format *format)
491{
492 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
493 struct v4l2_mbus_framefmt *__format;
494 struct v4l2_rect *__crop;
495 unsigned int width;
496 unsigned int height;
497 unsigned int hratio;
498 unsigned int vratio;
499
500 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad,
501 format->which);
502
503
504 width = clamp(ALIGN(format->format.width, 2),
505 max_t(unsigned int, __crop->width / 4,
506 MT9V032_WINDOW_WIDTH_MIN),
507 __crop->width);
508 height = clamp(ALIGN(format->format.height, 2),
509 max_t(unsigned int, __crop->height / 4,
510 MT9V032_WINDOW_HEIGHT_MIN),
511 __crop->height);
512
513 hratio = mt9v032_calc_ratio(__crop->width, width);
514 vratio = mt9v032_calc_ratio(__crop->height, height);
515
516 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad,
517 format->which);
518 __format->width = __crop->width / hratio;
519 __format->height = __crop->height / vratio;
520
521 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
522 mt9v032->hratio = hratio;
523 mt9v032->vratio = vratio;
524 mt9v032_configure_pixel_rate(mt9v032);
525 }
526
527 format->format = *__format;
528
529 return 0;
530}
531
532static int mt9v032_get_selection(struct v4l2_subdev *subdev,
533 struct v4l2_subdev_pad_config *cfg,
534 struct v4l2_subdev_selection *sel)
535{
536 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
537
538 if (sel->target != V4L2_SEL_TGT_CROP)
539 return -EINVAL;
540
541 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
542 return 0;
543}
544
545static int mt9v032_set_selection(struct v4l2_subdev *subdev,
546 struct v4l2_subdev_pad_config *cfg,
547 struct v4l2_subdev_selection *sel)
548{
549 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
550 struct v4l2_mbus_framefmt *__format;
551 struct v4l2_rect *__crop;
552 struct v4l2_rect rect;
553
554 if (sel->target != V4L2_SEL_TGT_CROP)
555 return -EINVAL;
556
557
558
559
560 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
561 MT9V032_COLUMN_START_MIN,
562 MT9V032_COLUMN_START_MAX);
563 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
564 MT9V032_ROW_START_MIN,
565 MT9V032_ROW_START_MAX);
566 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
567 MT9V032_WINDOW_WIDTH_MIN,
568 MT9V032_WINDOW_WIDTH_MAX);
569 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
570 MT9V032_WINDOW_HEIGHT_MIN,
571 MT9V032_WINDOW_HEIGHT_MAX);
572
573 rect.width = min_t(unsigned int,
574 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
575 rect.height = min_t(unsigned int,
576 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
577
578 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
579
580 if (rect.width != __crop->width || rect.height != __crop->height) {
581
582
583
584 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad,
585 sel->which);
586 __format->width = rect.width;
587 __format->height = rect.height;
588 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
589 mt9v032->hratio = 1;
590 mt9v032->vratio = 1;
591 mt9v032_configure_pixel_rate(mt9v032);
592 }
593 }
594
595 *__crop = rect;
596 sel->r = rect;
597
598 return 0;
599}
600
601
602
603
604
605#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
606
607
608
609
610
611#define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002)
612
613
614
615
616
617
618
619
620
621
622#define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003)
623#define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004)
624
625
626
627
628#define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005)
629#define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006)
630
631
632
633#define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007)
634
635static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
636{
637 struct mt9v032 *mt9v032 =
638 container_of(ctrl->handler, struct mt9v032, ctrls);
639 struct regmap *map = mt9v032->regmap;
640 u32 freq;
641 u16 data;
642
643 switch (ctrl->id) {
644 case V4L2_CID_AUTOGAIN:
645 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
646 ctrl->val);
647
648 case V4L2_CID_GAIN:
649 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
650
651 case V4L2_CID_EXPOSURE_AUTO:
652 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
653 !ctrl->val);
654
655 case V4L2_CID_EXPOSURE:
656 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
657 ctrl->val);
658
659 case V4L2_CID_HBLANK:
660 mt9v032->hblank = ctrl->val;
661 return mt9v032_update_hblank(mt9v032);
662
663 case V4L2_CID_VBLANK:
664 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
665 ctrl->val);
666
667 case V4L2_CID_PIXEL_RATE:
668 case V4L2_CID_LINK_FREQ:
669 if (mt9v032->link_freq == NULL)
670 break;
671
672 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
673 *mt9v032->pixel_rate->p_new.p_s64 = freq;
674 mt9v032->sysclk = freq;
675 break;
676
677 case V4L2_CID_TEST_PATTERN:
678 switch (mt9v032->test_pattern->val) {
679 case 0:
680 data = 0;
681 break;
682 case 1:
683 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
684 | MT9V032_TEST_PATTERN_ENABLE;
685 break;
686 case 2:
687 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
688 | MT9V032_TEST_PATTERN_ENABLE;
689 break;
690 case 3:
691 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
692 | MT9V032_TEST_PATTERN_ENABLE;
693 break;
694 default:
695 data = (mt9v032->test_pattern_color->val <<
696 MT9V032_TEST_PATTERN_DATA_SHIFT)
697 | MT9V032_TEST_PATTERN_USE_DATA
698 | MT9V032_TEST_PATTERN_ENABLE
699 | MT9V032_TEST_PATTERN_FLIP;
700 break;
701 }
702 return regmap_write(map, MT9V032_TEST_PATTERN, data);
703
704 case V4L2_CID_AEGC_DESIRED_BIN:
705 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
706
707 case V4L2_CID_AEC_LPF:
708 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
709
710 case V4L2_CID_AGC_LPF:
711 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
712
713 case V4L2_CID_AEC_UPDATE_INTERVAL:
714 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
715 ctrl->val);
716
717 case V4L2_CID_AGC_UPDATE_INTERVAL:
718 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
719 ctrl->val);
720
721 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
722 return regmap_write(map,
723 mt9v032->model->data->aec_max_shutter_reg,
724 ctrl->val);
725 }
726
727 return 0;
728}
729
730static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
731 .s_ctrl = mt9v032_s_ctrl,
732};
733
734static const char * const mt9v032_test_pattern_menu[] = {
735 "Disabled",
736 "Gray Vertical Shade",
737 "Gray Horizontal Shade",
738 "Gray Diagonal Shade",
739 "Plain",
740};
741
742static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
743 .ops = &mt9v032_ctrl_ops,
744 .id = V4L2_CID_TEST_PATTERN_COLOR,
745 .type = V4L2_CTRL_TYPE_INTEGER,
746 .name = "Test Pattern Color",
747 .min = 0,
748 .max = 1023,
749 .step = 1,
750 .def = 0,
751 .flags = 0,
752};
753
754static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
755 {
756 .ops = &mt9v032_ctrl_ops,
757 .id = V4L2_CID_AEGC_DESIRED_BIN,
758 .type = V4L2_CTRL_TYPE_INTEGER,
759 .name = "AEC/AGC Desired Bin",
760 .min = 1,
761 .max = 64,
762 .step = 1,
763 .def = 58,
764 .flags = 0,
765 }, {
766 .ops = &mt9v032_ctrl_ops,
767 .id = V4L2_CID_AEC_LPF,
768 .type = V4L2_CTRL_TYPE_INTEGER,
769 .name = "AEC Low Pass Filter",
770 .min = 0,
771 .max = 2,
772 .step = 1,
773 .def = 0,
774 .flags = 0,
775 }, {
776 .ops = &mt9v032_ctrl_ops,
777 .id = V4L2_CID_AGC_LPF,
778 .type = V4L2_CTRL_TYPE_INTEGER,
779 .name = "AGC Low Pass Filter",
780 .min = 0,
781 .max = 2,
782 .step = 1,
783 .def = 2,
784 .flags = 0,
785 }, {
786 .ops = &mt9v032_ctrl_ops,
787 .id = V4L2_CID_AEC_UPDATE_INTERVAL,
788 .type = V4L2_CTRL_TYPE_INTEGER,
789 .name = "AEC Update Interval",
790 .min = 0,
791 .max = 16,
792 .step = 1,
793 .def = 2,
794 .flags = 0,
795 }, {
796 .ops = &mt9v032_ctrl_ops,
797 .id = V4L2_CID_AGC_UPDATE_INTERVAL,
798 .type = V4L2_CTRL_TYPE_INTEGER,
799 .name = "AGC Update Interval",
800 .min = 0,
801 .max = 16,
802 .step = 1,
803 .def = 2,
804 .flags = 0,
805 }
806};
807
808static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
809 .ops = &mt9v032_ctrl_ops,
810 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
811 .type = V4L2_CTRL_TYPE_INTEGER,
812 .name = "AEC Max Shutter Width",
813 .min = 1,
814 .max = 2047,
815 .step = 1,
816 .def = 480,
817 .flags = 0,
818};
819
820static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
821 .ops = &mt9v032_ctrl_ops,
822 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
823 .type = V4L2_CTRL_TYPE_INTEGER,
824 .name = "AEC Max Shutter Width",
825 .min = 1,
826 .max = 32765,
827 .step = 1,
828 .def = 480,
829 .flags = 0,
830};
831
832
833
834
835
836static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
837{
838 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
839 int ret = 0;
840
841 mutex_lock(&mt9v032->power_lock);
842
843
844
845
846 if (mt9v032->power_count == !on) {
847 ret = __mt9v032_set_power(mt9v032, !!on);
848 if (ret < 0)
849 goto done;
850 }
851
852
853 mt9v032->power_count += on ? 1 : -1;
854 WARN_ON(mt9v032->power_count < 0);
855
856done:
857 mutex_unlock(&mt9v032->power_lock);
858 return ret;
859}
860
861
862
863
864
865static int mt9v032_registered(struct v4l2_subdev *subdev)
866{
867 struct i2c_client *client = v4l2_get_subdevdata(subdev);
868 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
869 unsigned int i;
870 u32 version;
871 int ret;
872
873 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
874 client->addr);
875
876 ret = mt9v032_power_on(mt9v032);
877 if (ret < 0) {
878 dev_err(&client->dev, "MT9V032 power up failed\n");
879 return ret;
880 }
881
882
883 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
884
885 mt9v032_power_off(mt9v032);
886
887 if (ret < 0) {
888 dev_err(&client->dev, "Failed reading chip version\n");
889 return ret;
890 }
891
892 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
893 if (mt9v032_versions[i].version == version) {
894 mt9v032->version = &mt9v032_versions[i];
895 break;
896 }
897 }
898
899 if (mt9v032->version == NULL) {
900 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
901 version);
902 return -ENODEV;
903 }
904
905 dev_info(&client->dev, "%s detected at address 0x%02x\n",
906 mt9v032->version->name, client->addr);
907
908 mt9v032_configure_pixel_rate(mt9v032);
909
910 return ret;
911}
912
913static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
914{
915 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
916 struct v4l2_mbus_framefmt *format;
917 struct v4l2_rect *crop;
918
919 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
920 crop->left = MT9V032_COLUMN_START_DEF;
921 crop->top = MT9V032_ROW_START_DEF;
922 crop->width = MT9V032_WINDOW_WIDTH_DEF;
923 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
924
925 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
926
927 if (mt9v032->model->color)
928 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
929 else
930 format->code = MEDIA_BUS_FMT_Y10_1X10;
931
932 format->width = MT9V032_WINDOW_WIDTH_DEF;
933 format->height = MT9V032_WINDOW_HEIGHT_DEF;
934 format->field = V4L2_FIELD_NONE;
935 format->colorspace = V4L2_COLORSPACE_SRGB;
936
937 return mt9v032_set_power(subdev, 1);
938}
939
940static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
941{
942 return mt9v032_set_power(subdev, 0);
943}
944
945static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
946 .s_power = mt9v032_set_power,
947};
948
949static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
950 .s_stream = mt9v032_s_stream,
951};
952
953static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
954 .enum_mbus_code = mt9v032_enum_mbus_code,
955 .enum_frame_size = mt9v032_enum_frame_size,
956 .get_fmt = mt9v032_get_format,
957 .set_fmt = mt9v032_set_format,
958 .get_selection = mt9v032_get_selection,
959 .set_selection = mt9v032_set_selection,
960};
961
962static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
963 .core = &mt9v032_subdev_core_ops,
964 .video = &mt9v032_subdev_video_ops,
965 .pad = &mt9v032_subdev_pad_ops,
966};
967
968static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
969 .registered = mt9v032_registered,
970 .open = mt9v032_open,
971 .close = mt9v032_close,
972};
973
974static const struct regmap_config mt9v032_regmap_config = {
975 .reg_bits = 8,
976 .val_bits = 16,
977 .max_register = 0xff,
978 .cache_type = REGCACHE_RBTREE,
979};
980
981
982
983
984
985static struct mt9v032_platform_data *
986mt9v032_get_pdata(struct i2c_client *client)
987{
988 struct mt9v032_platform_data *pdata = NULL;
989 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
990 struct device_node *np;
991 struct property *prop;
992
993 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
994 return client->dev.platform_data;
995
996 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
997 if (!np)
998 return NULL;
999
1000 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1001 goto done;
1002
1003 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1004 if (!pdata)
1005 goto done;
1006
1007 prop = of_find_property(np, "link-frequencies", NULL);
1008 if (prop) {
1009 u64 *link_freqs;
1010 size_t size = prop->length / sizeof(*link_freqs);
1011
1012 link_freqs = devm_kcalloc(&client->dev, size,
1013 sizeof(*link_freqs), GFP_KERNEL);
1014 if (!link_freqs)
1015 goto done;
1016
1017 if (of_property_read_u64_array(np, "link-frequencies",
1018 link_freqs, size) < 0)
1019 goto done;
1020
1021 pdata->link_freqs = link_freqs;
1022 pdata->link_def_freq = link_freqs[0];
1023 }
1024
1025 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1026 V4L2_MBUS_PCLK_SAMPLE_RISING);
1027
1028done:
1029 of_node_put(np);
1030 return pdata;
1031}
1032
1033static int mt9v032_probe(struct i2c_client *client,
1034 const struct i2c_device_id *did)
1035{
1036 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1037 struct mt9v032 *mt9v032;
1038 unsigned int i;
1039 int ret;
1040
1041 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1042 if (!mt9v032)
1043 return -ENOMEM;
1044
1045 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1046 if (IS_ERR(mt9v032->regmap))
1047 return PTR_ERR(mt9v032->regmap);
1048
1049 mt9v032->clk = devm_clk_get(&client->dev, NULL);
1050 if (IS_ERR(mt9v032->clk))
1051 return PTR_ERR(mt9v032->clk);
1052
1053 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1054 GPIOD_OUT_HIGH);
1055 if (IS_ERR(mt9v032->reset_gpio))
1056 return PTR_ERR(mt9v032->reset_gpio);
1057
1058 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1059 GPIOD_OUT_LOW);
1060 if (IS_ERR(mt9v032->standby_gpio))
1061 return PTR_ERR(mt9v032->standby_gpio);
1062
1063 mutex_init(&mt9v032->power_lock);
1064 mt9v032->pdata = pdata;
1065 mt9v032->model = (const void *)did->driver_data;
1066
1067 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1068 ARRAY_SIZE(mt9v032_aegc_controls));
1069
1070 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1071 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1072 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1073 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1074 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1075 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1076 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1077 V4L2_EXPOSURE_AUTO);
1078 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1079 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1080 mt9v032->model->data->max_shutter, 1,
1081 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1082 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1083 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1084 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1085 MT9V032_HORIZONTAL_BLANKING_DEF);
1086 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1087 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1088 mt9v032->model->data->max_vblank, 1,
1089 MT9V032_VERTICAL_BLANKING_DEF);
1090 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1091 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1092 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1093 mt9v032_test_pattern_menu);
1094 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1095 &mt9v032_test_pattern_color, NULL);
1096
1097 v4l2_ctrl_new_custom(&mt9v032->ctrls,
1098 mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1099 NULL);
1100 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1101 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1102 NULL);
1103
1104 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1105
1106 mt9v032->pixel_rate =
1107 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1108 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1109
1110 if (pdata && pdata->link_freqs) {
1111 unsigned int def = 0;
1112
1113 for (i = 0; pdata->link_freqs[i]; ++i) {
1114 if (pdata->link_freqs[i] == pdata->link_def_freq)
1115 def = i;
1116 }
1117
1118 mt9v032->link_freq =
1119 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1120 &mt9v032_ctrl_ops,
1121 V4L2_CID_LINK_FREQ, i - 1, def,
1122 pdata->link_freqs);
1123 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1124 }
1125
1126
1127 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1128
1129 if (mt9v032->ctrls.error) {
1130 dev_err(&client->dev, "control initialization error %d\n",
1131 mt9v032->ctrls.error);
1132 ret = mt9v032->ctrls.error;
1133 goto err;
1134 }
1135
1136 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1137 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1138 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1139 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1140
1141 if (mt9v032->model->color)
1142 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1143 else
1144 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1145
1146 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1147 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1148 mt9v032->format.field = V4L2_FIELD_NONE;
1149 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1150
1151 mt9v032->hratio = 1;
1152 mt9v032->vratio = 1;
1153
1154 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1155 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1156 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1157
1158 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1159 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1160 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1161
1162 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1163 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1164 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1165 if (ret < 0)
1166 goto err;
1167
1168 mt9v032->subdev.dev = &client->dev;
1169 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1170 if (ret < 0)
1171 goto err;
1172
1173 return 0;
1174
1175err:
1176 media_entity_cleanup(&mt9v032->subdev.entity);
1177 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1178 return ret;
1179}
1180
1181static int mt9v032_remove(struct i2c_client *client)
1182{
1183 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1184 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1185
1186 v4l2_async_unregister_subdev(subdev);
1187 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1188 media_entity_cleanup(&subdev->entity);
1189
1190 return 0;
1191}
1192
1193static const struct mt9v032_model_data mt9v032_model_data[] = {
1194 {
1195
1196 .min_row_time = 660,
1197 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1198 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1199 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1200 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1201 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1202 .pclk_reg = MT9V032_PIXEL_CLOCK,
1203 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1204 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1205 }, {
1206
1207 .min_row_time = 690,
1208 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1209 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1210 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1211 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1212 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1213 .pclk_reg = MT9V034_PIXEL_CLOCK,
1214 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1215 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1216 },
1217};
1218
1219static const struct mt9v032_model_info mt9v032_models[] = {
1220 [MT9V032_MODEL_V022_COLOR] = {
1221 .data = &mt9v032_model_data[0],
1222 .color = true,
1223 },
1224 [MT9V032_MODEL_V022_MONO] = {
1225 .data = &mt9v032_model_data[0],
1226 .color = false,
1227 },
1228 [MT9V032_MODEL_V024_COLOR] = {
1229 .data = &mt9v032_model_data[1],
1230 .color = true,
1231 },
1232 [MT9V032_MODEL_V024_MONO] = {
1233 .data = &mt9v032_model_data[1],
1234 .color = false,
1235 },
1236 [MT9V032_MODEL_V032_COLOR] = {
1237 .data = &mt9v032_model_data[0],
1238 .color = true,
1239 },
1240 [MT9V032_MODEL_V032_MONO] = {
1241 .data = &mt9v032_model_data[0],
1242 .color = false,
1243 },
1244 [MT9V032_MODEL_V034_COLOR] = {
1245 .data = &mt9v032_model_data[1],
1246 .color = true,
1247 },
1248 [MT9V032_MODEL_V034_MONO] = {
1249 .data = &mt9v032_model_data[1],
1250 .color = false,
1251 },
1252};
1253
1254static const struct i2c_device_id mt9v032_id[] = {
1255 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1256 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1257 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1258 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1259 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1260 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1261 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1262 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1263 { }
1264};
1265MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1266
1267#if IS_ENABLED(CONFIG_OF)
1268static const struct of_device_id mt9v032_of_match[] = {
1269 { .compatible = "aptina,mt9v022" },
1270 { .compatible = "aptina,mt9v022m" },
1271 { .compatible = "aptina,mt9v024" },
1272 { .compatible = "aptina,mt9v024m" },
1273 { .compatible = "aptina,mt9v032" },
1274 { .compatible = "aptina,mt9v032m" },
1275 { .compatible = "aptina,mt9v034" },
1276 { .compatible = "aptina,mt9v034m" },
1277 { }
1278};
1279MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1280#endif
1281
1282static struct i2c_driver mt9v032_driver = {
1283 .driver = {
1284 .name = "mt9v032",
1285 .of_match_table = of_match_ptr(mt9v032_of_match),
1286 },
1287 .probe = mt9v032_probe,
1288 .remove = mt9v032_remove,
1289 .id_table = mt9v032_id,
1290};
1291
1292module_i2c_driver(mt9v032_driver);
1293
1294MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1295MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1296MODULE_LICENSE("GPL");
1297
