1
2
3
4#include <linux/clk.h>
5#include <linux/delay.h>
6#include <linux/gpio/consumer.h>
7#include <linux/i2c.h>
8#include <linux/module.h>
9#include <linux/pm_runtime.h>
10#include <linux/regmap.h>
11#include <media/v4l2-ctrls.h>
12#include <media/v4l2-event.h>
13#include <media/v4l2-image-sizes.h>
14#include <media/v4l2-subdev.h>
15
16#define REG_OUTSIZE_LSB 0x34
17
18
19#define REG_GAIN 0x00
20#define REG_BGAIN 0x01
21#define REG_RGAIN 0x02
22#define REG_GGAIN 0x03
23#define REG_REG04 0x04
24#define REG_BAVG 0x05
25#define REG_GAVG 0x06
26#define REG_RAVG 0x07
27
28#define REG_REG0C 0x0C
29#define REG0C_IMG_FLIP 0x80
30#define REG0C_IMG_MIRROR 0x40
31
32#define REG_REG0E 0x0E
33#define REG_HAEC 0x0F
34#define REG_AEC 0x10
35
36#define REG_CLK 0x11
37#define REG_REG55 0x55
38
39#define REG_REG12 0x12
40
41#define REG_REG13 0x13
42#define REG13_AEC_EN 0x01
43#define REG13_AGC_EN 0x04
44
45#define REG_REG14 0x14
46#define REG_CTRL15 0x15
47#define REG15_GAIN_MSB 0x03
48
49#define REG_REG16 0x16
50
51#define REG_MIDH 0x1C
52#define REG_MIDL 0x1D
53#define REG_PIDH 0x0A
54#define REG_PIDL 0x0B
55
56#define REG_84 0x84
57#define REG_REG38 0x38
58
59#define REG_AHSTART 0x17
60#define REG_AHSIZE 0x18
61#define REG_AVSTART 0x19
62#define REG_AVSIZE 0x1A
63#define REG_PSHFT 0x1b
64
65#define REG_HOUTSIZE 0x31
66#define REG_VOUTSIZE 0x32
67#define REG_HVSIZEOFF 0x33
68#define REG_REG34 0x34
69
70#define REG_ISP_CTRL00 0x80
71#define ISPCTRL00_AWB_EN 0x10
72#define ISPCTRL00_AWB_GAIN_EN 0x04
73
74#define REG_YGAIN 0xE2
75
76#define REG_YBRIGHT 0xE3
77#define REG_SGNSET 0xE4
78#define SGNSET_YBRIGHT_MASK 0x08
79
80#define REG_USAT 0xDD
81#define REG_VSAT 0xDE
82
83
84struct ov7740 {
85 struct v4l2_subdev subdev;
86#if defined(CONFIG_MEDIA_CONTROLLER)
87 struct media_pad pad;
88#endif
89 struct v4l2_mbus_framefmt format;
90 const struct ov7740_pixfmt *fmt;
91 const struct ov7740_framesize *frmsize;
92 struct regmap *regmap;
93 struct clk *xvclk;
94 struct v4l2_ctrl_handler ctrl_handler;
95 struct {
96
97 struct v4l2_ctrl *auto_gain;
98 struct v4l2_ctrl *gain;
99 };
100 struct {
101 struct v4l2_ctrl *auto_wb;
102 struct v4l2_ctrl *blue_balance;
103 struct v4l2_ctrl *red_balance;
104 };
105 struct {
106 struct v4l2_ctrl *hflip;
107 struct v4l2_ctrl *vflip;
108 };
109 struct {
110
111 struct v4l2_ctrl *auto_exposure;
112 struct v4l2_ctrl *exposure;
113 };
114 struct {
115
116 struct v4l2_ctrl *saturation;
117 struct v4l2_ctrl *hue;
118 };
119 struct v4l2_ctrl *brightness;
120 struct v4l2_ctrl *contrast;
121
122 struct mutex mutex;
123 bool streaming;
124
125 struct gpio_desc *resetb_gpio;
126 struct gpio_desc *pwdn_gpio;
127};
128
129struct ov7740_pixfmt {
130 u32 mbus_code;
131 enum v4l2_colorspace colorspace;
132 const struct reg_sequence *regs;
133 u32 reg_num;
134};
135
136struct ov7740_framesize {
137 u16 width;
138 u16 height;
139 const struct reg_sequence *regs;
140 u32 reg_num;
141};
142
143static const struct reg_sequence ov7740_vga[] = {
144 {0x55, 0x40},
145 {0x11, 0x02},
146
147 {0xd5, 0x10},
148 {0x0c, 0x12},
149 {0x0d, 0x34},
150 {0x17, 0x25},
151 {0x18, 0xa0},
152 {0x19, 0x03},
153 {0x1a, 0xf0},
154 {0x1b, 0x89},
155 {0x22, 0x03},
156 {0x29, 0x18},
157 {0x2b, 0xf8},
158 {0x2c, 0x01},
159 {REG_HOUTSIZE, 0xa0},
160 {REG_VOUTSIZE, 0xf0},
161 {0x33, 0xc4},
162 {REG_OUTSIZE_LSB, 0x0},
163 {0x35, 0x05},
164 {0x04, 0x60},
165 {0x27, 0x80},
166 {0x3d, 0x0f},
167 {0x3e, 0x80},
168 {0x3f, 0x40},
169 {0x40, 0x7f},
170 {0x41, 0x6a},
171 {0x42, 0x29},
172 {0x44, 0x22},
173 {0x45, 0x41},
174 {0x47, 0x02},
175 {0x49, 0x64},
176 {0x4a, 0xa1},
177 {0x4b, 0x40},
178 {0x4c, 0x1a},
179 {0x4d, 0x50},
180 {0x4e, 0x13},
181 {0x64, 0x00},
182 {0x67, 0x88},
183 {0x68, 0x1a},
184
185 {0x14, 0x28},
186 {0x24, 0x3c},
187 {0x25, 0x30},
188 {0x26, 0x72},
189 {0x50, 0x97},
190 {0x51, 0x1f},
191 {0x52, 0x00},
192 {0x53, 0x00},
193 {0x20, 0x00},
194 {0x21, 0xcf},
195 {0x50, 0x4b},
196 {0x38, 0x14},
197 {0xe9, 0x00},
198 {0x56, 0x55},
199 {0x57, 0xff},
200 {0x58, 0xff},
201 {0x59, 0xff},
202 {0x5f, 0x04},
203 {0xec, 0x00},
204 {0x13, 0xff},
205
206 {0x81, 0x3f},
207 {0x82, 0x32},
208 {0x38, 0x11},
209 {0x84, 0x70},
210 {0x85, 0x00},
211 {0x86, 0x03},
212 {0x87, 0x01},
213 {0x88, 0x05},
214 {0x89, 0x30},
215 {0x8d, 0x30},
216 {0x8f, 0x85},
217 {0x93, 0x30},
218 {0x95, 0x85},
219 {0x99, 0x30},
220 {0x9b, 0x85},
221
222 {0x9c, 0x08},
223 {0x9d, 0x12},
224 {0x9e, 0x23},
225 {0x9f, 0x45},
226 {0xa0, 0x55},
227 {0xa1, 0x64},
228 {0xa2, 0x72},
229 {0xa3, 0x7f},
230 {0xa4, 0x8b},
231 {0xa5, 0x95},
232 {0xa6, 0xa7},
233 {0xa7, 0xb5},
234 {0xa8, 0xcb},
235 {0xa9, 0xdd},
236 {0xaa, 0xec},
237 {0xab, 0x1a},
238
239 {0xce, 0x78},
240 {0xcf, 0x6e},
241 {0xd0, 0x0a},
242 {0xd1, 0x0c},
243 {0xd2, 0x84},
244 {0xd3, 0x90},
245 {0xd4, 0x1e},
246
247 {0x5a, 0x24},
248 {0x5b, 0x1f},
249 {0x5c, 0x88},
250 {0x5d, 0x60},
251
252 {0xac, 0x6e},
253 {0xbe, 0xff},
254 {0xbf, 0x00},
255
256 {0x0f, 0x1d},
257 {0x0f, 0x1f},
258};
259
260static const struct ov7740_framesize ov7740_framesizes[] = {
261 {
262 .width = VGA_WIDTH,
263 .height = VGA_HEIGHT,
264 .regs = ov7740_vga,
265 .reg_num = ARRAY_SIZE(ov7740_vga),
266 },
267};
268
269#ifdef CONFIG_VIDEO_ADV_DEBUG
270static int ov7740_get_register(struct v4l2_subdev *sd,
271 struct v4l2_dbg_register *reg)
272{
273 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
274 struct regmap *regmap = ov7740->regmap;
275 unsigned int val = 0;
276 int ret;
277
278 ret = regmap_read(regmap, reg->reg & 0xff, &val);
279 reg->val = val;
280 reg->size = 1;
281
282 return ret;
283}
284
285static int ov7740_set_register(struct v4l2_subdev *sd,
286 const struct v4l2_dbg_register *reg)
287{
288 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
289 struct regmap *regmap = ov7740->regmap;
290
291 regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff);
292
293 return 0;
294}
295#endif
296
297static int ov7740_set_power(struct ov7740 *ov7740, int on)
298{
299 int ret;
300
301 if (on) {
302 ret = clk_prepare_enable(ov7740->xvclk);
303 if (ret)
304 return ret;
305
306 if (ov7740->pwdn_gpio)
307 gpiod_direction_output(ov7740->pwdn_gpio, 0);
308
309 if (ov7740->resetb_gpio) {
310 gpiod_set_value(ov7740->resetb_gpio, 1);
311 usleep_range(500, 1000);
312 gpiod_set_value(ov7740->resetb_gpio, 0);
313 usleep_range(3000, 5000);
314 }
315 } else {
316 clk_disable_unprepare(ov7740->xvclk);
317
318 if (ov7740->pwdn_gpio)
319 gpiod_direction_output(ov7740->pwdn_gpio, 0);
320 }
321
322 return 0;
323}
324
325static const struct v4l2_subdev_core_ops ov7740_subdev_core_ops = {
326 .log_status = v4l2_ctrl_subdev_log_status,
327#ifdef CONFIG_VIDEO_ADV_DEBUG
328 .g_register = ov7740_get_register,
329 .s_register = ov7740_set_register,
330#endif
331 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
332 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
333};
334
335static int ov7740_set_white_balance(struct ov7740 *ov7740, int awb)
336{
337 struct regmap *regmap = ov7740->regmap;
338 unsigned int value;
339 int ret;
340
341 ret = regmap_read(regmap, REG_ISP_CTRL00, &value);
342 if (!ret) {
343 if (awb)
344 value |= (ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
345 else
346 value &= ~(ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
347 ret = regmap_write(regmap, REG_ISP_CTRL00, value);
348 if (ret)
349 return ret;
350 }
351
352 if (!awb) {
353 ret = regmap_write(regmap, REG_BGAIN,
354 ov7740->blue_balance->val);
355 if (ret)
356 return ret;
357
358 ret = regmap_write(regmap, REG_RGAIN, ov7740->red_balance->val);
359 if (ret)
360 return ret;
361 }
362
363 return 0;
364}
365
366static int ov7740_set_saturation(struct regmap *regmap, int value)
367{
368 int ret;
369
370 ret = regmap_write(regmap, REG_USAT, (unsigned char)value);
371 if (ret)
372 return ret;
373
374 return regmap_write(regmap, REG_VSAT, (unsigned char)value);
375}
376
377static int ov7740_set_gain(struct regmap *regmap, int value)
378{
379 int ret;
380
381 ret = regmap_write(regmap, REG_GAIN, value & 0xff);
382 if (ret)
383 return ret;
384
385 ret = regmap_update_bits(regmap, REG_CTRL15,
386 REG15_GAIN_MSB, (value >> 8) & 0x3);
387 if (!ret)
388 ret = regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
389
390 return ret;
391}
392
393static int ov7740_set_autogain(struct regmap *regmap, int value)
394{
395 unsigned int reg;
396 int ret;
397
398 ret = regmap_read(regmap, REG_REG13, ®);
399 if (ret)
400 return ret;
401 if (value)
402 reg |= REG13_AGC_EN;
403 else
404 reg &= ~REG13_AGC_EN;
405 return regmap_write(regmap, REG_REG13, reg);
406}
407
408static int ov7740_set_brightness(struct regmap *regmap, int value)
409{
410
411 regmap_update_bits(regmap, REG_REG13, REG13_AEC_EN, 0);
412 regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
413
414 if (value >= 0) {
415 regmap_write(regmap, REG_YBRIGHT, (unsigned char)value);
416 regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 0);
417 } else{
418 regmap_write(regmap, REG_YBRIGHT, (unsigned char)(-value));
419 regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 1);
420 }
421
422 return 0;
423}
424
425static int ov7740_set_contrast(struct regmap *regmap, int value)
426{
427 return regmap_write(regmap, REG_YGAIN, (unsigned char)value);
428}
429
430static int ov7740_get_gain(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl)
431{
432 struct regmap *regmap = ov7740->regmap;
433 unsigned int value0, value1;
434 int ret;
435
436 if (!ctrl->val)
437 return 0;
438
439 ret = regmap_read(regmap, REG_GAIN, &value0);
440 if (ret)
441 return ret;
442 ret = regmap_read(regmap, REG_CTRL15, &value1);
443 if (ret)
444 return ret;
445
446 ov7740->gain->val = (value1 << 8) | (value0 & 0xff);
447
448 return 0;
449}
450
451static int ov7740_get_exp(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl)
452{
453 struct regmap *regmap = ov7740->regmap;
454 unsigned int value0, value1;
455 int ret;
456
457 if (ctrl->val == V4L2_EXPOSURE_MANUAL)
458 return 0;
459
460 ret = regmap_read(regmap, REG_AEC, &value0);
461 if (ret)
462 return ret;
463 ret = regmap_read(regmap, REG_HAEC, &value1);
464 if (ret)
465 return ret;
466
467 ov7740->exposure->val = (value1 << 8) | (value0 & 0xff);
468
469 return 0;
470}
471
472static int ov7740_set_exp(struct regmap *regmap, int value)
473{
474 int ret;
475
476
477 ret = regmap_update_bits(regmap, REG_REG13,
478 REG13_AEC_EN | REG13_AGC_EN, 0);
479 if (ret)
480 return ret;
481
482 ret = regmap_write(regmap, REG_AEC, (unsigned char)value);
483 if (ret)
484 return ret;
485
486 return regmap_write(regmap, REG_HAEC, (unsigned char)(value >> 8));
487}
488
489static int ov7740_set_autoexp(struct regmap *regmap,
490 enum v4l2_exposure_auto_type value)
491{
492 unsigned int reg;
493 int ret;
494
495 ret = regmap_read(regmap, REG_REG13, ®);
496 if (!ret) {
497 if (value == V4L2_EXPOSURE_AUTO)
498 reg |= (REG13_AEC_EN | REG13_AGC_EN);
499 else
500 reg &= ~(REG13_AEC_EN | REG13_AGC_EN);
501 ret = regmap_write(regmap, REG_REG13, reg);
502 }
503
504 return ret;
505}
506
507
508static int ov7740_get_volatile_ctrl(struct v4l2_ctrl *ctrl)
509{
510 struct ov7740 *ov7740 = container_of(ctrl->handler,
511 struct ov7740, ctrl_handler);
512 int ret;
513
514 switch (ctrl->id) {
515 case V4L2_CID_AUTOGAIN:
516 ret = ov7740_get_gain(ov7740, ctrl);
517 break;
518 case V4L2_CID_EXPOSURE_AUTO:
519 ret = ov7740_get_exp(ov7740, ctrl);
520 break;
521 default:
522 ret = -EINVAL;
523 break;
524 }
525 return ret;
526}
527
528static int ov7740_set_ctrl(struct v4l2_ctrl *ctrl)
529{
530 struct ov7740 *ov7740 = container_of(ctrl->handler,
531 struct ov7740, ctrl_handler);
532 struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
533 struct regmap *regmap = ov7740->regmap;
534 int ret;
535 u8 val;
536
537 if (!pm_runtime_get_if_in_use(&client->dev))
538 return 0;
539
540 switch (ctrl->id) {
541 case V4L2_CID_AUTO_WHITE_BALANCE:
542 ret = ov7740_set_white_balance(ov7740, ctrl->val);
543 break;
544 case V4L2_CID_SATURATION:
545 ret = ov7740_set_saturation(regmap, ctrl->val);
546 break;
547 case V4L2_CID_BRIGHTNESS:
548 ret = ov7740_set_brightness(regmap, ctrl->val);
549 break;
550 case V4L2_CID_CONTRAST:
551 ret = ov7740_set_contrast(regmap, ctrl->val);
552 break;
553 case V4L2_CID_VFLIP:
554 val = ctrl->val ? REG0C_IMG_FLIP : 0x00;
555 ret = regmap_update_bits(regmap, REG_REG0C,
556 REG0C_IMG_FLIP, val);
557 break;
558 case V4L2_CID_HFLIP:
559 val = ctrl->val ? REG0C_IMG_MIRROR : 0x00;
560 ret = regmap_update_bits(regmap, REG_REG0C,
561 REG0C_IMG_MIRROR, val);
562 break;
563 case V4L2_CID_AUTOGAIN:
564 if (!ctrl->val)
565 ret = ov7740_set_gain(regmap, ov7740->gain->val);
566 else
567 ret = ov7740_set_autogain(regmap, ctrl->val);
568 break;
569
570 case V4L2_CID_EXPOSURE_AUTO:
571 if (ctrl->val == V4L2_EXPOSURE_MANUAL)
572 ret = ov7740_set_exp(regmap, ov7740->exposure->val);
573 else
574 ret = ov7740_set_autoexp(regmap, ctrl->val);
575 break;
576 default:
577 ret = -EINVAL;
578 break;
579 }
580
581 pm_runtime_put(&client->dev);
582
583 return ret;
584}
585
586static const struct v4l2_ctrl_ops ov7740_ctrl_ops = {
587 .g_volatile_ctrl = ov7740_get_volatile_ctrl,
588 .s_ctrl = ov7740_set_ctrl,
589};
590
591static int ov7740_start_streaming(struct ov7740 *ov7740)
592{
593 int ret;
594
595 if (ov7740->fmt) {
596 ret = regmap_multi_reg_write(ov7740->regmap,
597 ov7740->fmt->regs,
598 ov7740->fmt->reg_num);
599 if (ret)
600 return ret;
601 }
602
603 if (ov7740->frmsize) {
604 ret = regmap_multi_reg_write(ov7740->regmap,
605 ov7740->frmsize->regs,
606 ov7740->frmsize->reg_num);
607 if (ret)
608 return ret;
609 }
610
611 return __v4l2_ctrl_handler_setup(ov7740->subdev.ctrl_handler);
612}
613
614static int ov7740_set_stream(struct v4l2_subdev *sd, int enable)
615{
616 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
617 struct i2c_client *client = v4l2_get_subdevdata(sd);
618 int ret = 0;
619
620 mutex_lock(&ov7740->mutex);
621 if (ov7740->streaming == enable) {
622 mutex_unlock(&ov7740->mutex);
623 return 0;
624 }
625
626 if (enable) {
627 ret = pm_runtime_get_sync(&client->dev);
628 if (ret < 0) {
629 pm_runtime_put_noidle(&client->dev);
630 goto err_unlock;
631 }
632
633 ret = ov7740_start_streaming(ov7740);
634 if (ret)
635 goto err_rpm_put;
636 } else {
637 pm_runtime_put(&client->dev);
638 }
639
640 ov7740->streaming = enable;
641
642 mutex_unlock(&ov7740->mutex);
643 return ret;
644
645err_rpm_put:
646 pm_runtime_put(&client->dev);
647err_unlock:
648 mutex_unlock(&ov7740->mutex);
649 return ret;
650}
651
652static int ov7740_g_frame_interval(struct v4l2_subdev *sd,
653 struct v4l2_subdev_frame_interval *ival)
654{
655 struct v4l2_fract *tpf = &ival->interval;
656
657
658 tpf->numerator = 1;
659 tpf->denominator = 60;
660
661 return 0;
662}
663
664static int ov7740_s_frame_interval(struct v4l2_subdev *sd,
665 struct v4l2_subdev_frame_interval *ival)
666{
667 struct v4l2_fract *tpf = &ival->interval;
668
669
670 tpf->numerator = 1;
671 tpf->denominator = 60;
672
673 return 0;
674}
675
676static const struct v4l2_subdev_video_ops ov7740_subdev_video_ops = {
677 .s_stream = ov7740_set_stream,
678 .s_frame_interval = ov7740_s_frame_interval,
679 .g_frame_interval = ov7740_g_frame_interval,
680};
681
682static const struct reg_sequence ov7740_format_yuyv[] = {
683 {0x12, 0x00},
684 {0x36, 0x3f},
685 {0x80, 0x7f},
686 {0x83, 0x01},
687};
688
689static const struct reg_sequence ov7740_format_bggr8[] = {
690 {0x36, 0x2f},
691 {0x80, 0x01},
692 {0x83, 0x04},
693};
694
695static const struct ov7740_pixfmt ov7740_formats[] = {
696 {
697 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
698 .colorspace = V4L2_COLORSPACE_SRGB,
699 .regs = ov7740_format_yuyv,
700 .reg_num = ARRAY_SIZE(ov7740_format_yuyv),
701 },
702 {
703 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
704 .colorspace = V4L2_COLORSPACE_SRGB,
705 .regs = ov7740_format_bggr8,
706 .reg_num = ARRAY_SIZE(ov7740_format_bggr8),
707 }
708};
709#define N_OV7740_FMTS ARRAY_SIZE(ov7740_formats)
710
711static int ov7740_enum_mbus_code(struct v4l2_subdev *sd,
712 struct v4l2_subdev_pad_config *cfg,
713 struct v4l2_subdev_mbus_code_enum *code)
714{
715 if (code->pad || code->index >= N_OV7740_FMTS)
716 return -EINVAL;
717
718 code->code = ov7740_formats[code->index].mbus_code;
719
720 return 0;
721}
722
723static int ov7740_enum_frame_interval(struct v4l2_subdev *sd,
724 struct v4l2_subdev_pad_config *cfg,
725 struct v4l2_subdev_frame_interval_enum *fie)
726{
727 if (fie->pad)
728 return -EINVAL;
729
730 if (fie->index >= 1)
731 return -EINVAL;
732
733 if ((fie->width != VGA_WIDTH) || (fie->height != VGA_HEIGHT))
734 return -EINVAL;
735
736 fie->interval.numerator = 1;
737 fie->interval.denominator = 60;
738
739 return 0;
740}
741
742static int ov7740_enum_frame_size(struct v4l2_subdev *sd,
743 struct v4l2_subdev_pad_config *cfg,
744 struct v4l2_subdev_frame_size_enum *fse)
745{
746 if (fse->pad)
747 return -EINVAL;
748
749 if (fse->index > 0)
750 return -EINVAL;
751
752 fse->min_width = fse->max_width = VGA_WIDTH;
753 fse->min_height = fse->max_height = VGA_HEIGHT;
754
755 return 0;
756}
757
758static int ov7740_try_fmt_internal(struct v4l2_subdev *sd,
759 struct v4l2_mbus_framefmt *fmt,
760 const struct ov7740_pixfmt **ret_fmt,
761 const struct ov7740_framesize **ret_frmsize)
762{
763 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
764 const struct ov7740_framesize *fsize = &ov7740_framesizes[0];
765 int index, i;
766
767 for (index = 0; index < N_OV7740_FMTS; index++) {
768 if (ov7740_formats[index].mbus_code == fmt->code)
769 break;
770 }
771 if (index >= N_OV7740_FMTS) {
772
773 index = 0;
774 fmt->code = ov7740_formats[0].mbus_code;
775 }
776 if (ret_fmt != NULL)
777 *ret_fmt = ov7740_formats + index;
778
779 for (i = 0; i < ARRAY_SIZE(ov7740_framesizes); i++) {
780 if ((fsize->width >= fmt->width) &&
781 (fsize->height >= fmt->height)) {
782 fmt->width = fsize->width;
783 fmt->height = fsize->height;
784 break;
785 }
786
787 fsize++;
788 }
789 if (i >= ARRAY_SIZE(ov7740_framesizes)) {
790 fsize = &ov7740_framesizes[0];
791 fmt->width = fsize->width;
792 fmt->height = fsize->height;
793 }
794 if (ret_frmsize != NULL)
795 *ret_frmsize = fsize;
796
797 fmt->field = V4L2_FIELD_NONE;
798 fmt->colorspace = ov7740_formats[index].colorspace;
799
800 ov7740->format = *fmt;
801
802 return 0;
803}
804
805static int ov7740_set_fmt(struct v4l2_subdev *sd,
806 struct v4l2_subdev_pad_config *cfg,
807 struct v4l2_subdev_format *format)
808{
809 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
810 const struct ov7740_pixfmt *ovfmt;
811 const struct ov7740_framesize *fsize;
812#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
813 struct v4l2_mbus_framefmt *mbus_fmt;
814#endif
815 int ret;
816
817 mutex_lock(&ov7740->mutex);
818 if (format->pad) {
819 ret = -EINVAL;
820 goto error;
821 }
822
823 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
824 ret = ov7740_try_fmt_internal(sd, &format->format, NULL, NULL);
825 if (ret)
826 goto error;
827#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
828 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
829 *mbus_fmt = format->format;
830
831 mutex_unlock(&ov7740->mutex);
832 return 0;
833#else
834 ret = -ENOTTY;
835 goto error;
836#endif
837 }
838
839 ret = ov7740_try_fmt_internal(sd, &format->format, &ovfmt, &fsize);
840 if (ret)
841 goto error;
842
843 ov7740->fmt = ovfmt;
844 ov7740->frmsize = fsize;
845
846 mutex_unlock(&ov7740->mutex);
847 return 0;
848
849error:
850 mutex_unlock(&ov7740->mutex);
851 return ret;
852}
853
854static int ov7740_get_fmt(struct v4l2_subdev *sd,
855 struct v4l2_subdev_pad_config *cfg,
856 struct v4l2_subdev_format *format)
857{
858 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
859#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
860 struct v4l2_mbus_framefmt *mbus_fmt;
861#endif
862 int ret = 0;
863
864 mutex_lock(&ov7740->mutex);
865 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
866#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
867 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
868 format->format = *mbus_fmt;
869 ret = 0;
870#else
871 ret = -ENOTTY;
872#endif
873 } else {
874 format->format = ov7740->format;
875 }
876 mutex_unlock(&ov7740->mutex);
877
878 return ret;
879}
880
881static const struct v4l2_subdev_pad_ops ov7740_subdev_pad_ops = {
882 .enum_frame_interval = ov7740_enum_frame_interval,
883 .enum_frame_size = ov7740_enum_frame_size,
884 .enum_mbus_code = ov7740_enum_mbus_code,
885 .get_fmt = ov7740_get_fmt,
886 .set_fmt = ov7740_set_fmt,
887};
888
889static const struct v4l2_subdev_ops ov7740_subdev_ops = {
890 .core = &ov7740_subdev_core_ops,
891 .video = &ov7740_subdev_video_ops,
892 .pad = &ov7740_subdev_pad_ops,
893};
894
895static void ov7740_get_default_format(struct v4l2_subdev *sd,
896 struct v4l2_mbus_framefmt *format)
897{
898 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
899
900 format->width = ov7740->frmsize->width;
901 format->height = ov7740->frmsize->height;
902 format->colorspace = ov7740->fmt->colorspace;
903 format->code = ov7740->fmt->mbus_code;
904 format->field = V4L2_FIELD_NONE;
905}
906
907#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
908static int ov7740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
909{
910 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
911 struct v4l2_mbus_framefmt *format =
912 v4l2_subdev_get_try_format(sd, fh->pad, 0);
913
914 mutex_lock(&ov7740->mutex);
915 ov7740_get_default_format(sd, format);
916 mutex_unlock(&ov7740->mutex);
917
918 return 0;
919}
920
921static const struct v4l2_subdev_internal_ops ov7740_subdev_internal_ops = {
922 .open = ov7740_open,
923};
924#endif
925
926static int ov7740_probe_dt(struct i2c_client *client,
927 struct ov7740 *ov7740)
928{
929 ov7740->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
930 GPIOD_OUT_HIGH);
931 if (IS_ERR(ov7740->resetb_gpio)) {
932 dev_info(&client->dev, "can't get %s GPIO\n", "reset");
933 return PTR_ERR(ov7740->resetb_gpio);
934 }
935
936 ov7740->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
937 GPIOD_OUT_LOW);
938 if (IS_ERR(ov7740->pwdn_gpio)) {
939 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
940 return PTR_ERR(ov7740->pwdn_gpio);
941 }
942
943 return 0;
944}
945
946static int ov7740_detect(struct ov7740 *ov7740)
947{
948 struct regmap *regmap = ov7740->regmap;
949 unsigned int midh, midl, pidh, pidl;
950 int ret;
951
952 ret = regmap_read(regmap, REG_MIDH, &midh);
953 if (ret)
954 return ret;
955 if (midh != 0x7f)
956 return -ENODEV;
957
958 ret = regmap_read(regmap, REG_MIDL, &midl);
959 if (ret)
960 return ret;
961 if (midl != 0xa2)
962 return -ENODEV;
963
964 ret = regmap_read(regmap, REG_PIDH, &pidh);
965 if (ret)
966 return ret;
967 if (pidh != 0x77)
968 return -ENODEV;
969
970 ret = regmap_read(regmap, REG_PIDL, &pidl);
971 if (ret)
972 return ret;
973 if ((pidl != 0x40) && (pidl != 0x41) && (pidl != 0x42))
974 return -ENODEV;
975
976 return 0;
977}
978
979static int ov7740_init_controls(struct ov7740 *ov7740)
980{
981 struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
982 struct v4l2_ctrl_handler *ctrl_hdlr = &ov7740->ctrl_handler;
983 int ret;
984
985 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
986 if (ret < 0)
987 return ret;
988
989 ctrl_hdlr->lock = &ov7740->mutex;
990 ov7740->auto_wb = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
991 V4L2_CID_AUTO_WHITE_BALANCE,
992 0, 1, 1, 1);
993 ov7740->blue_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
994 V4L2_CID_BLUE_BALANCE,
995 0, 0xff, 1, 0x80);
996 ov7740->red_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
997 V4L2_CID_RED_BALANCE,
998 0, 0xff, 1, 0x80);
999
1000 ov7740->brightness = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1001 V4L2_CID_BRIGHTNESS,
1002 -255, 255, 1, 0);
1003 ov7740->contrast = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1004 V4L2_CID_CONTRAST,
1005 0, 127, 1, 0x20);
1006 ov7740->saturation = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1007 V4L2_CID_SATURATION, 0, 256, 1, 0x80);
1008 ov7740->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1009 V4L2_CID_HFLIP, 0, 1, 1, 0);
1010 ov7740->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1011 V4L2_CID_VFLIP, 0, 1, 1, 0);
1012
1013 ov7740->gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1014 V4L2_CID_GAIN, 0, 1023, 1, 500);
1015
1016 ov7740->auto_gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1017 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1018
1019 ov7740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
1020 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1021
1022 ov7740->auto_exposure = v4l2_ctrl_new_std_menu(ctrl_hdlr,
1023 &ov7740_ctrl_ops,
1024 V4L2_CID_EXPOSURE_AUTO,
1025 V4L2_EXPOSURE_MANUAL, 0,
1026 V4L2_EXPOSURE_AUTO);
1027
1028 v4l2_ctrl_auto_cluster(3, &ov7740->auto_wb, 0, false);
1029 v4l2_ctrl_auto_cluster(2, &ov7740->auto_gain, 0, true);
1030 v4l2_ctrl_auto_cluster(2, &ov7740->auto_exposure,
1031 V4L2_EXPOSURE_MANUAL, true);
1032
1033 if (ctrl_hdlr->error) {
1034 ret = ctrl_hdlr->error;
1035 dev_err(&client->dev, "controls initialisation failed (%d)\n",
1036 ret);
1037 goto error;
1038 }
1039
1040 ret = v4l2_ctrl_handler_setup(ctrl_hdlr);
1041 if (ret) {
1042 dev_err(&client->dev, "%s control init failed (%d)\n",
1043 __func__, ret);
1044 goto error;
1045 }
1046
1047 ov7740->subdev.ctrl_handler = ctrl_hdlr;
1048 return 0;
1049
1050error:
1051 v4l2_ctrl_handler_free(ctrl_hdlr);
1052 mutex_destroy(&ov7740->mutex);
1053 return ret;
1054}
1055
1056static void ov7740_free_controls(struct ov7740 *ov7740)
1057{
1058 v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
1059 mutex_destroy(&ov7740->mutex);
1060}
1061
1062#define OV7740_MAX_REGISTER 0xff
1063static const struct regmap_config ov7740_regmap_config = {
1064 .reg_bits = 8,
1065 .val_bits = 8,
1066 .max_register = OV7740_MAX_REGISTER,
1067};
1068
1069static int ov7740_probe(struct i2c_client *client,
1070 const struct i2c_device_id *id)
1071{
1072 struct ov7740 *ov7740;
1073 struct v4l2_subdev *sd;
1074 int ret;
1075
1076 if (!i2c_check_functionality(client->adapter,
1077 I2C_FUNC_SMBUS_BYTE_DATA)) {
1078 dev_err(&client->dev,
1079 "OV7740: I2C-Adapter doesn't support SMBUS\n");
1080 return -EIO;
1081 }
1082
1083 ov7740 = devm_kzalloc(&client->dev, sizeof(*ov7740), GFP_KERNEL);
1084 if (!ov7740)
1085 return -ENOMEM;
1086
1087 ov7740->xvclk = devm_clk_get(&client->dev, "xvclk");
1088 if (IS_ERR(ov7740->xvclk)) {
1089 ret = PTR_ERR(ov7740->xvclk);
1090 dev_err(&client->dev,
1091 "OV7740: fail to get xvclk: %d\n", ret);
1092 return ret;
1093 }
1094
1095 ret = ov7740_probe_dt(client, ov7740);
1096 if (ret)
1097 return ret;
1098
1099 ov7740->regmap = devm_regmap_init_i2c(client, &ov7740_regmap_config);
1100 if (IS_ERR(ov7740->regmap)) {
1101 ret = PTR_ERR(ov7740->regmap);
1102 dev_err(&client->dev, "Failed to allocate register map: %d\n",
1103 ret);
1104 return ret;
1105 }
1106
1107 sd = &ov7740->subdev;
1108 client->flags |= I2C_CLIENT_SCCB;
1109 v4l2_i2c_subdev_init(sd, client, &ov7740_subdev_ops);
1110
1111#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1112 sd->internal_ops = &ov7740_subdev_internal_ops;
1113 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1114#endif
1115
1116#if defined(CONFIG_MEDIA_CONTROLLER)
1117 ov7740->pad.flags = MEDIA_PAD_FL_SOURCE;
1118 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1119 ret = media_entity_pads_init(&sd->entity, 1, &ov7740->pad);
1120 if (ret)
1121 return ret;
1122#endif
1123
1124 ret = ov7740_set_power(ov7740, 1);
1125 if (ret)
1126 return ret;
1127
1128 pm_runtime_set_active(&client->dev);
1129 pm_runtime_enable(&client->dev);
1130
1131 ret = ov7740_detect(ov7740);
1132 if (ret)
1133 goto error_detect;
1134
1135 mutex_init(&ov7740->mutex);
1136
1137 ret = ov7740_init_controls(ov7740);
1138 if (ret)
1139 goto error_init_controls;
1140
1141 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1142 client->addr << 1, client->adapter->name);
1143
1144 ov7740->fmt = &ov7740_formats[0];
1145 ov7740->frmsize = &ov7740_framesizes[0];
1146
1147 ov7740_get_default_format(sd, &ov7740->format);
1148
1149 ret = v4l2_async_register_subdev(sd);
1150 if (ret)
1151 goto error_async_register;
1152
1153 pm_runtime_idle(&client->dev);
1154
1155 return 0;
1156
1157error_async_register:
1158 v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
1159error_init_controls:
1160 ov7740_free_controls(ov7740);
1161error_detect:
1162 pm_runtime_disable(&client->dev);
1163 pm_runtime_set_suspended(&client->dev);
1164 ov7740_set_power(ov7740, 0);
1165 media_entity_cleanup(&ov7740->subdev.entity);
1166
1167 return ret;
1168}
1169
1170static int ov7740_remove(struct i2c_client *client)
1171{
1172 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1173 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
1174
1175 mutex_destroy(&ov7740->mutex);
1176 v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
1177 media_entity_cleanup(&ov7740->subdev.entity);
1178 v4l2_async_unregister_subdev(sd);
1179 ov7740_free_controls(ov7740);
1180
1181 pm_runtime_get_sync(&client->dev);
1182 pm_runtime_disable(&client->dev);
1183 pm_runtime_set_suspended(&client->dev);
1184 pm_runtime_put_noidle(&client->dev);
1185
1186 ov7740_set_power(ov7740, 0);
1187 return 0;
1188}
1189
1190static int __maybe_unused ov7740_runtime_suspend(struct device *dev)
1191{
1192 struct i2c_client *client = to_i2c_client(dev);
1193 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1194 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
1195
1196 ov7740_set_power(ov7740, 0);
1197
1198 return 0;
1199}
1200
1201static int __maybe_unused ov7740_runtime_resume(struct device *dev)
1202{
1203 struct i2c_client *client = to_i2c_client(dev);
1204 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1205 struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
1206
1207 return ov7740_set_power(ov7740, 1);
1208}
1209
1210static const struct i2c_device_id ov7740_id[] = {
1211 { "ov7740", 0 },
1212 { }
1213};
1214MODULE_DEVICE_TABLE(i2c, ov7740_id);
1215
1216static const struct dev_pm_ops ov7740_pm_ops = {
1217 SET_RUNTIME_PM_OPS(ov7740_runtime_suspend, ov7740_runtime_resume, NULL)
1218};
1219
1220static const struct of_device_id ov7740_of_match[] = {
1221 {.compatible = "ovti,ov7740", },
1222 { },
1223};
1224MODULE_DEVICE_TABLE(of, ov7740_of_match);
1225
1226static struct i2c_driver ov7740_i2c_driver = {
1227 .driver = {
1228 .name = "ov7740",
1229 .pm = &ov7740_pm_ops,
1230 .of_match_table = of_match_ptr(ov7740_of_match),
1231 },
1232 .probe = ov7740_probe,
1233 .remove = ov7740_remove,
1234 .id_table = ov7740_id,
1235};
1236module_i2c_driver(ov7740_i2c_driver);
1237
1238MODULE_DESCRIPTION("The V4L2 driver for Omnivision 7740 sensor");
1239MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
1240MODULE_LICENSE("GPL v2");
1241
