LXR linux/drivers/media/pci/tw68/tw68-core.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  tw68-core.c
   4 *  Core functions for the Techwell 68xx driver
   5 *
   6 *  Much of this code is derived from the cx88 and sa7134 drivers, which
   7 *  were in turn derived from the bt87x driver.  The original work was by
   8 *  Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
   9 *  Hans Verkuil, Andy Walls and many others.  Their work is gratefully
  10 *  acknowledged.  Full credit goes to them - any problems within this code
  11 *  are mine.
  12 *
  13 *  Copyright (C) 2009  William M. Brack
  14 *
  15 *  Refactored and updated to the latest v4l core frameworks:
  16 *
  17 *  Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/list.h>
  22#include <linux/module.h>
  23#include <linux/kernel.h>
  24#include <linux/slab.h>
  25#include <linux/kmod.h>
  26#include <linux/sound.h>
  27#include <linux/interrupt.h>
  28#include <linux/delay.h>
  29#include <linux/mutex.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/pci_ids.h>
  32#include <linux/pm.h>
  33
  34#include <media/v4l2-dev.h>
  35#include "tw68.h"
  36#include "tw68-reg.h"
  37
  38MODULE_DESCRIPTION("v4l2 driver module for tw6800 based video capture cards");
  39MODULE_AUTHOR("William M. Brack");
  40MODULE_AUTHOR("Hans Verkuil <hverkuil@xs4all.nl>");
  41MODULE_LICENSE("GPL");
  42
  43static unsigned int latency = UNSET;
  44module_param(latency, int, 0444);
  45MODULE_PARM_DESC(latency, "pci latency timer");
  46
  47static unsigned int video_nr[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET };
  48module_param_array(video_nr, int, NULL, 0444);
  49MODULE_PARM_DESC(video_nr, "video device number");
  50
  51static unsigned int card[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET };
  52module_param_array(card, int, NULL, 0444);
  53MODULE_PARM_DESC(card, "card type");
  54
  55static atomic_t tw68_instance = ATOMIC_INIT(0);
  56
  57/* ------------------------------------------------------------------ */
  58
  59/*
  60 * Please add any new PCI IDs to: http://pci-ids.ucw.cz.  This keeps
  61 * the PCI ID database up to date.  Note that the entries must be
  62 * added under vendor 0x1797 (Techwell Inc.) as subsystem IDs.
  63 */
  64static const struct pci_device_id tw68_pci_tbl[] = {
  65        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6800)},
  66        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6801)},
  67        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6804)},
  68        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_1)},
  69        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_2)},
  70        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_3)},
  71        {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_6816_4)},
  72        {0,}
  73};
  74
  75/* ------------------------------------------------------------------ */
  76
  77
  78/*
  79 * The device is given a "soft reset". According to the specifications,
  80 * after this "all register content remain unchanged", so we also write
  81 * to all specified registers manually as well (mostly to manufacturer's
  82 * specified reset values)
  83 */
  84static int tw68_hw_init1(struct tw68_dev *dev)
  85{
  86        /* Assure all interrupts are disabled */
  87        tw_writel(TW68_INTMASK, 0);             /* 020 */
  88        /* Clear any pending interrupts */
  89        tw_writel(TW68_INTSTAT, 0xffffffff);    /* 01C */
  90        /* Stop risc processor, set default buffer level */
  91        tw_writel(TW68_DMAC, 0x1600);
  92
  93        tw_writeb(TW68_ACNTL, 0x80);    /* 218  soft reset */
  94        msleep(100);
  95
  96        tw_writeb(TW68_INFORM, 0x40);   /* 208  mux0, 27mhz xtal */
  97        tw_writeb(TW68_OPFORM, 0x04);   /* 20C  analog line-lock */
  98        tw_writeb(TW68_HSYNC, 0);       /* 210  color-killer high sens */
  99        tw_writeb(TW68_ACNTL, 0x42);    /* 218  int vref #2, chroma adc off */
 100
 101        tw_writeb(TW68_CROP_HI, 0x02);  /* 21C  Hactive m.s. bits */
 102        tw_writeb(TW68_VDELAY_LO, 0x12);/* 220  Mfg specified reset value */
 103        tw_writeb(TW68_VACTIVE_LO, 0xf0);
 104        tw_writeb(TW68_HDELAY_LO, 0x0f);
 105        tw_writeb(TW68_HACTIVE_LO, 0xd0);
 106
 107        tw_writeb(TW68_CNTRL1, 0xcd);   /* 230  Wide Chroma BPF B/W
 108                                         *      Secam reduction, Adap comb for
 109                                         *      NTSC, Op Mode 1 */
 110
 111        tw_writeb(TW68_VSCALE_LO, 0);   /* 234 */
 112        tw_writeb(TW68_SCALE_HI, 0x11); /* 238 */
 113        tw_writeb(TW68_HSCALE_LO, 0);   /* 23c */
 114        tw_writeb(TW68_BRIGHT, 0);      /* 240 */
 115        tw_writeb(TW68_CONTRAST, 0x5c); /* 244 */
 116        tw_writeb(TW68_SHARPNESS, 0x51);/* 248 */
 117        tw_writeb(TW68_SAT_U, 0x80);    /* 24C */
 118        tw_writeb(TW68_SAT_V, 0x80);    /* 250 */
 119        tw_writeb(TW68_HUE, 0x00);      /* 254 */
 120
 121        /* TODO - Check that none of these are set by control defaults */
 122        tw_writeb(TW68_SHARP2, 0x53);   /* 258  Mfg specified reset val */
 123        tw_writeb(TW68_VSHARP, 0x80);   /* 25C  Sharpness Coring val 8 */
 124        tw_writeb(TW68_CORING, 0x44);   /* 260  CTI and Vert Peak coring */
 125        tw_writeb(TW68_CNTRL2, 0x00);   /* 268  No power saving enabled */
 126        tw_writeb(TW68_SDT, 0x07);      /* 270  Enable shadow reg, auto-det */
 127        tw_writeb(TW68_SDTR, 0x7f);     /* 274  All stds recog, don't start */
 128        tw_writeb(TW68_CLMPG, 0x50);    /* 280  Clamp end at 40 sys clocks */
 129        tw_writeb(TW68_IAGC, 0x22);     /* 284  Mfg specified reset val */
 130        tw_writeb(TW68_AGCGAIN, 0xf0);  /* 288  AGC gain when loop disabled */
 131        tw_writeb(TW68_PEAKWT, 0xd8);   /* 28C  White peak threshold */
 132        tw_writeb(TW68_CLMPL, 0x3c);    /* 290  Y channel clamp level */
 133/*      tw_writeb(TW68_SYNCT, 0x38);*/  /* 294  Sync amplitude */
 134        tw_writeb(TW68_SYNCT, 0x30);    /* 294  Sync amplitude */
 135        tw_writeb(TW68_MISSCNT, 0x44);  /* 298  Horiz sync, VCR detect sens */
 136        tw_writeb(TW68_PCLAMP, 0x28);   /* 29C  Clamp pos from PLL sync */
 137        /* Bit DETV of VCNTL1 helps sync multi cams/chip board */
 138        tw_writeb(TW68_VCNTL1, 0x04);   /* 2A0 */
 139        tw_writeb(TW68_VCNTL2, 0);      /* 2A4 */
 140        tw_writeb(TW68_CKILL, 0x68);    /* 2A8  Mfg specified reset val */
 141        tw_writeb(TW68_COMB, 0x44);     /* 2AC  Mfg specified reset val */
 142        tw_writeb(TW68_LDLY, 0x30);     /* 2B0  Max positive luma delay */
 143        tw_writeb(TW68_MISC1, 0x14);    /* 2B4  Mfg specified reset val */
 144        tw_writeb(TW68_LOOP, 0xa5);     /* 2B8  Mfg specified reset val */
 145        tw_writeb(TW68_MISC2, 0xe0);    /* 2BC  Enable colour killer */
 146        tw_writeb(TW68_MVSN, 0);        /* 2C0 */
 147        tw_writeb(TW68_CLMD, 0x05);     /* 2CC  slice level auto, clamp med. */
 148        tw_writeb(TW68_IDCNTL, 0);      /* 2D0  Writing zero to this register
 149                                         *      selects NTSC ID detection,
 150                                         *      but doesn't change the
 151                                         *      sensitivity (which has a reset
 152                                         *      value of 1E).  Since we are
 153                                         *      not doing auto-detection, it
 154                                         *      has no real effect */
 155        tw_writeb(TW68_CLCNTL1, 0);     /* 2D4 */
 156        tw_writel(TW68_VBIC, 0x03);     /* 010 */
 157        tw_writel(TW68_CAP_CTL, 0x03);  /* 040  Enable both even & odd flds */
 158        tw_writel(TW68_DMAC, 0x2000);   /* patch set had 0x2080 */
 159        tw_writel(TW68_TESTREG, 0);     /* 02C */
 160
 161        /*
 162         * Some common boards, especially inexpensive single-chip models,
 163         * use the GPIO bits 0-3 to control an on-board video-output mux.
 164         * For these boards, we need to set up the GPIO register into
 165         * "normal" mode, set bits 0-3 as output, and then set those bits
 166         * zero.
 167         *
 168         * Eventually, it would be nice if we could identify these boards
 169         * uniquely, and only do this initialisation if the board has been
 170         * identify.  For the moment, however, it shouldn't hurt anything
 171         * to do these steps.
 172         */
 173        tw_writel(TW68_GPIOC, 0);       /* Set the GPIO to "normal", no ints */
 174        tw_writel(TW68_GPOE, 0x0f);     /* Set bits 0-3 to "output" */
 175        tw_writel(TW68_GPDATA, 0);      /* Set all bits to low state */
 176
 177        /* Initialize the device control structures */
 178        mutex_init(&dev->lock);
 179        spin_lock_init(&dev->slock);
 180
 181        /* Initialize any subsystems */
 182        tw68_video_init1(dev);
 183        return 0;
 184}
 185
 186static irqreturn_t tw68_irq(int irq, void *dev_id)
 187{
 188        struct tw68_dev *dev = dev_id;
 189        u32 status, orig;
 190        int loop;
 191
 192        status = orig = tw_readl(TW68_INTSTAT) & dev->pci_irqmask;
 193        /* Check if anything to do */
 194        if (0 == status)
 195                return IRQ_NONE;        /* Nope - return */
 196        for (loop = 0; loop < 10; loop++) {
 197                if (status & dev->board_virqmask)       /* video interrupt */
 198                        tw68_irq_video_done(dev, status);
 199                status = tw_readl(TW68_INTSTAT) & dev->pci_irqmask;
 200                if (0 == status)
 201                        return IRQ_HANDLED;
 202        }
 203        dev_dbg(&dev->pci->dev, "%s: **** INTERRUPT NOT HANDLED - clearing mask (orig 0x%08x, cur 0x%08x)",
 204                        dev->name, orig, tw_readl(TW68_INTSTAT));
 205        dev_dbg(&dev->pci->dev, "%s: pci_irqmask 0x%08x; board_virqmask 0x%08x ****\n",
 206                        dev->name, dev->pci_irqmask, dev->board_virqmask);
 207        tw_clearl(TW68_INTMASK, dev->pci_irqmask);
 208        return IRQ_HANDLED;
 209}
 210
 211static int tw68_initdev(struct pci_dev *pci_dev,
 212                                     const struct pci_device_id *pci_id)
 213{
 214        struct tw68_dev *dev;
 215        int vidnr = -1;
 216        int err;
 217
 218        dev = devm_kzalloc(&pci_dev->dev, sizeof(*dev), GFP_KERNEL);
 219        if (NULL == dev)
 220                return -ENOMEM;
 221
 222        dev->instance = v4l2_device_set_name(&dev->v4l2_dev, "tw68",
 223                                                &tw68_instance);
 224
 225        err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
 226        if (err)
 227                return err;
 228
 229        /* pci init */
 230        dev->pci = pci_dev;
 231        if (pci_enable_device(pci_dev)) {
 232                err = -EIO;
 233                goto fail1;
 234        }
 235
 236        dev->name = dev->v4l2_dev.name;
 237
 238        if (UNSET != latency) {
 239                pr_info("%s: setting pci latency timer to %d\n",
 240                       dev->name, latency);
 241                pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);
 242        }
 243
 244        /* print pci info */
 245        pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
 246        pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
 247        pr_info("%s: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
 248                dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
 249                dev->pci_lat, (u64)pci_resource_start(pci_dev, 0));
 250        pci_set_master(pci_dev);
 251        err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
 252        if (err) {
 253                pr_info("%s: Oops: no 32bit PCI DMA ???\n", dev->name);
 254                goto fail1;
 255        }
 256
 257        switch (pci_id->device) {
 258        case PCI_DEVICE_ID_TECHWELL_6800:       /* TW6800 */
 259                dev->vdecoder = TW6800;
 260                dev->board_virqmask = TW68_VID_INTS;
 261                break;
 262        case PCI_DEVICE_ID_TECHWELL_6801:       /* Video decoder for TW6802 */
 263                dev->vdecoder = TW6801;
 264                dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX;
 265                break;
 266        case PCI_DEVICE_ID_TECHWELL_6804:       /* Video decoder for TW6804 */
 267                dev->vdecoder = TW6804;
 268                dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX;
 269                break;
 270        default:
 271                dev->vdecoder = TWXXXX; /* To be announced */
 272                dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX;
 273                break;
 274        }
 275
 276        /* get mmio */
 277        if (!request_mem_region(pci_resource_start(pci_dev, 0),
 278                                pci_resource_len(pci_dev, 0),
 279                                dev->name)) {
 280                err = -EBUSY;
 281                pr_err("%s: can't get MMIO memory @ 0x%llx\n",
 282                        dev->name,
 283                        (unsigned long long)pci_resource_start(pci_dev, 0));
 284                goto fail1;
 285        }
 286        dev->lmmio = ioremap(pci_resource_start(pci_dev, 0),
 287                             pci_resource_len(pci_dev, 0));
 288        dev->bmmio = (__u8 __iomem *)dev->lmmio;
 289        if (NULL == dev->lmmio) {
 290                err = -EIO;
 291                pr_err("%s: can't ioremap() MMIO memory\n",
 292                       dev->name);
 293                goto fail2;
 294        }
 295        /* initialize hardware #1 */
 296        /* Then do any initialisation wanted before interrupts are on */
 297        tw68_hw_init1(dev);
 298
 299        /* get irq */
 300        err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw68_irq,
 301                          IRQF_SHARED, dev->name, dev);
 302        if (err < 0) {
 303                pr_err("%s: can't get IRQ %d\n",
 304                       dev->name, pci_dev->irq);
 305                goto fail3;
 306        }
 307
 308        /*
 309         *  Now do remainder of initialisation, first for
 310         *  things unique for this card, then for general board
 311         */
 312        if (dev->instance < TW68_MAXBOARDS)
 313                vidnr = video_nr[dev->instance];
 314        /* initialise video function first */
 315        err = tw68_video_init2(dev, vidnr);
 316        if (err < 0) {
 317                pr_err("%s: can't register video device\n",
 318                       dev->name);
 319                goto fail4;
 320        }
 321        tw_setl(TW68_INTMASK, dev->pci_irqmask);
 322
 323        pr_info("%s: registered device %s\n",
 324               dev->name, video_device_node_name(&dev->vdev));
 325
 326        return 0;
 327
 328fail4:
 329        video_unregister_device(&dev->vdev);
 330fail3:
 331        iounmap(dev->lmmio);
 332fail2:
 333        release_mem_region(pci_resource_start(pci_dev, 0),
 334                           pci_resource_len(pci_dev, 0));
 335fail1:
 336        v4l2_device_unregister(&dev->v4l2_dev);
 337        return err;
 338}
 339
 340static void tw68_finidev(struct pci_dev *pci_dev)
 341{
 342        struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
 343        struct tw68_dev *dev =
 344                container_of(v4l2_dev, struct tw68_dev, v4l2_dev);
 345
 346        /* shutdown subsystems */
 347        tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN);
 348        tw_writel(TW68_INTMASK, 0);
 349
 350        /* unregister */
 351        video_unregister_device(&dev->vdev);
 352        v4l2_ctrl_handler_free(&dev->hdl);
 353
 354        /* release resources */
 355        iounmap(dev->lmmio);
 356        release_mem_region(pci_resource_start(pci_dev, 0),
 357                           pci_resource_len(pci_dev, 0));
 358
 359        v4l2_device_unregister(&dev->v4l2_dev);
 360}
 361
 362#ifdef CONFIG_PM
 363
 364static int tw68_suspend(struct pci_dev *pci_dev , pm_message_t state)
 365{
 366        struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
 367        struct tw68_dev *dev = container_of(v4l2_dev,
 368                                struct tw68_dev, v4l2_dev);
 369
 370        tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN);
 371        dev->pci_irqmask &= ~TW68_VID_INTS;
 372        tw_writel(TW68_INTMASK, 0);
 373
 374        synchronize_irq(pci_dev->irq);
 375
 376        pci_save_state(pci_dev);
 377        pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
 378        vb2_discard_done(&dev->vidq);
 379
 380        return 0;
 381}
 382
 383static int tw68_resume(struct pci_dev *pci_dev)
 384{
 385        struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
 386        struct tw68_dev *dev = container_of(v4l2_dev,
 387                                            struct tw68_dev, v4l2_dev);
 388        struct tw68_buf *buf;
 389        unsigned long flags;
 390
 391        pci_set_power_state(pci_dev, PCI_D0);
 392        pci_restore_state(pci_dev);
 393
 394        /* Do things that are done in tw68_initdev ,
 395                except of initializing memory structures.*/
 396
 397        msleep(100);
 398
 399        tw68_set_tvnorm_hw(dev);
 400
 401        /*resume unfinished buffer(s)*/
 402        spin_lock_irqsave(&dev->slock, flags);
 403        buf = container_of(dev->active.next, struct tw68_buf, list);
 404
 405        tw68_video_start_dma(dev, buf);
 406
 407        spin_unlock_irqrestore(&dev->slock, flags);
 408
 409        return 0;
 410}
 411#endif
 412
 413/* ----------------------------------------------------------- */
 414
 415static struct pci_driver tw68_pci_driver = {
 416        .name     = "tw68",
 417        .id_table = tw68_pci_tbl,
 418        .probe    = tw68_initdev,
 419        .remove   = tw68_finidev,
 420#ifdef CONFIG_PM
 421        .suspend  = tw68_suspend,
 422        .resume   = tw68_resume
 423#endif
 424};
 425
 426module_pci_driver(tw68_pci_driver);
 427