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6#ifndef FIMC_CORE_H_
7#define FIMC_CORE_H_
8
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10
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13#include <linux/sched.h>
14#include <linux/spinlock.h>
15#include <linux/mfd/syscon.h>
16#include <linux/types.h>
17#include <linux/videodev2.h>
18#include <linux/io.h>
19#include <linux/sizes.h>
20
21#include <media/media-entity.h>
22#include <media/videobuf2-v4l2.h>
23#include <media/v4l2-ctrls.h>
24#include <media/v4l2-device.h>
25#include <media/v4l2-mem2mem.h>
26#include <media/v4l2-mediabus.h>
27#include <media/drv-intf/exynos-fimc.h>
28
29#define dbg(fmt, args...) \
30 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
31
32
33#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
34#define MAX_FIMC_CLOCKS 2
35#define FIMC_DRIVER_NAME "exynos4-fimc"
36#define FIMC_MAX_DEVS 4
37#define FIMC_MAX_OUT_BUFS 4
38#define SCALER_MAX_HRATIO 64
39#define SCALER_MAX_VRATIO 64
40#define DMA_MIN_SIZE 8
41#define FIMC_CAMIF_MAX_HEIGHT 0x2000
42#define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
43#define FIMC_MAX_PLANES 3
44#define FIMC_PIX_LIMITS_MAX 4
45#define FIMC_DEF_MIN_SIZE 16
46#define FIMC_DEF_HEIGHT_ALIGN 2
47#define FIMC_DEF_HOR_OFFS_ALIGN 1
48#define FIMC_DEFAULT_WIDTH 640
49#define FIMC_DEFAULT_HEIGHT 480
50
51
52enum {
53 CLK_BUS,
54 CLK_GATE,
55};
56
57enum fimc_dev_flags {
58 ST_LPM,
59
60 ST_M2M_RUN,
61 ST_M2M_PEND,
62 ST_M2M_SUSPENDING,
63 ST_M2M_SUSPENDED,
64
65 ST_CAPT_PEND,
66 ST_CAPT_RUN,
67 ST_CAPT_STREAM,
68 ST_CAPT_ISP_STREAM,
69 ST_CAPT_SUSPENDED,
70 ST_CAPT_SHUT,
71 ST_CAPT_BUSY,
72 ST_CAPT_APPLY_CFG,
73 ST_CAPT_JPEG,
74};
75
76#define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
77#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
78
79#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
80#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
81#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
82
83enum fimc_datapath {
84 FIMC_IO_NONE,
85 FIMC_IO_CAMERA,
86 FIMC_IO_DMA,
87 FIMC_IO_LCDFIFO,
88 FIMC_IO_WRITEBACK,
89 FIMC_IO_ISP,
90};
91
92enum fimc_color_fmt {
93 FIMC_FMT_RGB444 = 0x10,
94 FIMC_FMT_RGB555,
95 FIMC_FMT_RGB565,
96 FIMC_FMT_RGB666,
97 FIMC_FMT_RGB888,
98 FIMC_FMT_RGB30_LOCAL,
99 FIMC_FMT_YCBCR420 = 0x20,
100 FIMC_FMT_YCBYCR422,
101 FIMC_FMT_YCRYCB422,
102 FIMC_FMT_CBYCRY422,
103 FIMC_FMT_CRYCBY422,
104 FIMC_FMT_YCBCR444_LOCAL,
105 FIMC_FMT_RAW8 = 0x40,
106 FIMC_FMT_RAW10,
107 FIMC_FMT_RAW12,
108 FIMC_FMT_JPEG = 0x80,
109 FIMC_FMT_YUYV_JPEG = 0x100,
110};
111
112#define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
113#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
114
115#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
116 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
117
118
119#define FIMC_PARAMS (1 << 0)
120#define FIMC_COMPOSE (1 << 1)
121#define FIMC_CTX_M2M (1 << 16)
122#define FIMC_CTX_CAP (1 << 17)
123#define FIMC_CTX_SHUT (1 << 18)
124
125
126#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
127#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
128#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
129#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
130#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
131#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
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135#define FIMC_COLOR_RANGE_WIDE (0 << 3)
136
137#define FIMC_COLOR_RANGE_NARROW (1 << 3)
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148struct fimc_dma_offset {
149 int y_h;
150 int y_v;
151 int cb_h;
152 int cb_v;
153 int cr_h;
154 int cr_v;
155};
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163struct fimc_effect {
164 u32 type;
165 u8 pat_cb;
166 u8 pat_cr;
167};
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187struct fimc_scaler {
188 unsigned int scaleup_h:1;
189 unsigned int scaleup_v:1;
190 unsigned int copy_mode:1;
191 unsigned int enabled:1;
192 u32 hfactor;
193 u32 vfactor;
194 u32 pre_hratio;
195 u32 pre_vratio;
196 u32 pre_dst_width;
197 u32 pre_dst_height;
198 u32 main_hratio;
199 u32 main_vratio;
200 u32 real_width;
201 u32 real_height;
202};
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210struct fimc_addr {
211 u32 y;
212 u32 cb;
213 u32 cr;
214};
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223struct fimc_vid_buffer {
224 struct vb2_v4l2_buffer vb;
225 struct list_head list;
226 struct fimc_addr paddr;
227 int index;
228};
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246struct fimc_frame {
247 u32 f_width;
248 u32 f_height;
249 u32 o_width;
250 u32 o_height;
251 u32 offs_h;
252 u32 offs_v;
253 u32 width;
254 u32 height;
255 unsigned int payload[VIDEO_MAX_PLANES];
256 unsigned int bytesperline[VIDEO_MAX_PLANES];
257 struct fimc_addr paddr;
258 struct fimc_dma_offset dma_offset;
259 struct fimc_fmt *fmt;
260 u8 alpha;
261};
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270struct fimc_m2m_device {
271 struct video_device vfd;
272 struct v4l2_m2m_dev *m2m_dev;
273 struct fimc_ctx *ctx;
274 int refcnt;
275};
276
277#define FIMC_SD_PAD_SINK_CAM 0
278#define FIMC_SD_PAD_SINK_FIFO 1
279#define FIMC_SD_PAD_SOURCE 2
280#define FIMC_SD_PADS_NUM 3
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305struct fimc_vid_cap {
306 struct fimc_ctx *ctx;
307 struct v4l2_subdev subdev;
308 struct exynos_video_entity ve;
309 struct media_pad vd_pad;
310 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
311 struct v4l2_mbus_framefmt ci_fmt;
312 struct v4l2_mbus_framefmt wb_fmt;
313 struct fimc_source_info source_config;
314 struct list_head pending_buf_q;
315 struct list_head active_buf_q;
316 struct vb2_queue vbq;
317 int active_buf_cnt;
318 int buf_index;
319 unsigned int frame_count;
320 unsigned int reqbufs_count;
321 bool streaming;
322 int input_index;
323 u32 input;
324 bool user_subdev_api;
325 bool inh_sensor_ctrls;
326};
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338struct fimc_pix_limit {
339 u16 scaler_en_w;
340 u16 scaler_dis_w;
341 u16 in_rot_en_h;
342 u16 in_rot_dis_w;
343 u16 out_rot_en_w;
344 u16 out_rot_dis_w;
345};
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361struct fimc_variant {
362 unsigned int has_inp_rot:1;
363 unsigned int has_out_rot:1;
364 unsigned int has_mainscaler_ext:1;
365 unsigned int has_cam_if:1;
366 unsigned int has_isp_wb:1;
367 const struct fimc_pix_limit *pix_limit;
368 u16 min_inp_pixsize;
369 u16 min_out_pixsize;
370 u16 hor_offs_align;
371 u16 min_vsize_align;
372};
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384struct fimc_drvdata {
385 const struct fimc_variant *variant[FIMC_MAX_DEVS];
386 int num_entities;
387 unsigned long lclk_frequency;
388
389 u8 cistatus2;
390 u8 dma_pix_hoff;
391 u8 alpha_color;
392 u8 out_buf_count;
393};
394
395#define fimc_get_drvdata(_pdev) \
396 ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
397
398struct fimc_ctx;
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418struct fimc_dev {
419 spinlock_t slock;
420 struct mutex lock;
421 struct platform_device *pdev;
422 struct s5p_platform_fimc *pdata;
423 struct regmap *sysreg;
424 const struct fimc_variant *variant;
425 const struct fimc_drvdata *drv_data;
426 int id;
427 struct clk *clock[MAX_FIMC_CLOCKS];
428 void __iomem *regs;
429 wait_queue_head_t irq_queue;
430 struct v4l2_device *v4l2_dev;
431 struct fimc_m2m_device m2m;
432 struct fimc_vid_cap vid_cap;
433 unsigned long state;
434};
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447struct fimc_ctrls {
448 struct v4l2_ctrl_handler handler;
449 struct {
450 struct v4l2_ctrl *colorfx;
451 struct v4l2_ctrl *colorfx_cbcr;
452 };
453 struct v4l2_ctrl *rotate;
454 struct v4l2_ctrl *hflip;
455 struct v4l2_ctrl *vflip;
456 struct v4l2_ctrl *alpha;
457 bool ready;
458};
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481struct fimc_ctx {
482 struct fimc_frame s_frame;
483 struct fimc_frame d_frame;
484 u32 out_order_1p;
485 u32 out_order_2p;
486 u32 in_order_1p;
487 u32 in_order_2p;
488 enum fimc_datapath in_path;
489 enum fimc_datapath out_path;
490 struct fimc_scaler scaler;
491 struct fimc_effect effect;
492 int rotation;
493 unsigned int hflip:1;
494 unsigned int vflip:1;
495 u32 flags;
496 u32 state;
497 struct fimc_dev *fimc_dev;
498 struct v4l2_fh fh;
499 struct fimc_ctrls ctrls;
500};
501
502#define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
503
504static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
505{
506 f->o_width = width;
507 f->o_height = height;
508 f->f_width = width;
509 f->f_height = height;
510}
511
512static inline void set_frame_crop(struct fimc_frame *f,
513 u32 left, u32 top, u32 width, u32 height)
514{
515 f->offs_h = left;
516 f->offs_v = top;
517 f->width = width;
518 f->height = height;
519}
520
521static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
522{
523 u32 i, depth = 0;
524
525 if (ff != NULL)
526 for (i = 0; i < ff->colplanes; i++)
527 depth += ff->depth[i];
528 return depth;
529}
530
531static inline bool fimc_capture_active(struct fimc_dev *fimc)
532{
533 unsigned long flags;
534 bool ret;
535
536 spin_lock_irqsave(&fimc->slock, flags);
537 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
538 fimc->state & (1 << ST_CAPT_PEND));
539 spin_unlock_irqrestore(&fimc->slock, flags);
540 return ret;
541}
542
543static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
544{
545 unsigned long flags;
546
547 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
548 ctx->state |= state;
549 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
550}
551
552static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
553{
554 unsigned long flags;
555 bool ret;
556
557 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
558 ret = (ctx->state & mask) == mask;
559 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
560 return ret;
561}
562
563static inline int tiled_fmt(struct fimc_fmt *fmt)
564{
565 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
566}
567
568static inline bool fimc_jpeg_fourcc(u32 pixelformat)
569{
570 return (pixelformat == V4L2_PIX_FMT_JPEG ||
571 pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
572}
573
574static inline bool fimc_user_defined_mbus_fmt(u32 code)
575{
576 return (code == MEDIA_BUS_FMT_JPEG_1X8 ||
577 code == MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8);
578}
579
580
581static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
582{
583 switch (fmt->color) {
584 case FIMC_FMT_RGB444: return 0x0f;
585 case FIMC_FMT_RGB555: return 0x01;
586 case FIMC_FMT_RGB888: return 0xff;
587 default: return 0;
588 };
589}
590
591static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
592 enum v4l2_buf_type type)
593{
594 struct fimc_frame *frame;
595
596 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ||
597 type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
598 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
599 frame = &ctx->s_frame;
600 else
601 return ERR_PTR(-EINVAL);
602 } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
603 type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
604 frame = &ctx->d_frame;
605 } else {
606 v4l2_err(ctx->fimc_dev->v4l2_dev,
607 "Wrong buffer/video queue type (%d)\n", type);
608 return ERR_PTR(-EINVAL);
609 }
610
611 return frame;
612}
613
614
615
616int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
617 struct v4l2_fmtdesc *f);
618int fimc_ctrls_create(struct fimc_ctx *ctx);
619void fimc_ctrls_delete(struct fimc_ctx *ctx);
620void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
621void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
622void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
623void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
624 struct v4l2_pix_format_mplane *pix);
625struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
626 unsigned int mask, int index);
627struct fimc_fmt *fimc_get_format(unsigned int index);
628
629int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
630 int dw, int dh, int rotation);
631int fimc_set_scaler_info(struct fimc_ctx *ctx);
632int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
633int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
634 struct fimc_frame *frame, struct fimc_addr *paddr);
635void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
636void fimc_set_yuv_order(struct fimc_ctx *ctx);
637void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
638
639int fimc_register_m2m_device(struct fimc_dev *fimc,
640 struct v4l2_device *v4l2_dev);
641void fimc_unregister_m2m_device(struct fimc_dev *fimc);
642int fimc_register_driver(void);
643void fimc_unregister_driver(void);
644
645#ifdef CONFIG_MFD_SYSCON
646static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
647{
648 return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
649}
650#else
651#define fimc_get_sysreg_regmap(node) (NULL)
652#endif
653
654
655
656void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
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659
660int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
661void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
662int fimc_capture_ctrls_create(struct fimc_dev *fimc);
663void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
664 void *arg);
665int fimc_capture_suspend(struct fimc_dev *fimc);
666int fimc_capture_resume(struct fimc_dev *fimc);
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676static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
677 struct fimc_vid_buffer *buf)
678{
679 list_add_tail(&buf->list, &vid_cap->active_buf_q);
680 vid_cap->active_buf_cnt++;
681}
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687
688static inline struct fimc_vid_buffer *fimc_active_queue_pop(
689 struct fimc_vid_cap *vid_cap)
690{
691 struct fimc_vid_buffer *buf;
692 buf = list_entry(vid_cap->active_buf_q.next,
693 struct fimc_vid_buffer, list);
694 list_del(&buf->list);
695 vid_cap->active_buf_cnt--;
696 return buf;
697}
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703static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
704 struct fimc_vid_buffer *buf)
705{
706 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
707}
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714static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
715 struct fimc_vid_cap *vid_cap)
716{
717 struct fimc_vid_buffer *buf;
718 buf = list_entry(vid_cap->pending_buf_q.next,
719 struct fimc_vid_buffer, list);
720 list_del(&buf->list);
721 return buf;
722}
723
724#endif
725