1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Houlong Wei <houlong.wei@mediatek.com> 5 * Ming Hsiu Tsai <minghsiu.tsai@mediatek.com> 6 */ 7 8#ifndef __MTK_MDP_CORE_H__ 9#define __MTK_MDP_CORE_H__ 10 11#include <linux/videodev2.h> 12#include <media/v4l2-ctrls.h> 13#include <media/v4l2-device.h> 14#include <media/v4l2-mem2mem.h> 15#include <media/videobuf2-core.h> 16#include <media/videobuf2-dma-contig.h> 17 18#include "mtk_mdp_vpu.h" 19#include "mtk_mdp_comp.h" 20 21 22#define MTK_MDP_MODULE_NAME "mtk-mdp" 23 24#define MTK_MDP_SHUTDOWN_TIMEOUT ((100*HZ)/1000) /* 100ms */ 25#define MTK_MDP_MAX_CTRL_NUM 10 26 27#define MTK_MDP_FMT_FLAG_OUTPUT BIT(0) 28#define MTK_MDP_FMT_FLAG_CAPTURE BIT(1) 29 30#define MTK_MDP_VPU_INIT BIT(0) 31#define MTK_MDP_SRC_FMT BIT(1) 32#define MTK_MDP_DST_FMT BIT(2) 33#define MTK_MDP_CTX_ERROR BIT(5) 34 35/** 36 * struct mtk_mdp_pix_align - alignment of image 37 * @org_w: source alignment of width 38 * @org_h: source alignment of height 39 * @target_w: dst alignment of width 40 * @target_h: dst alignment of height 41 */ 42struct mtk_mdp_pix_align { 43 u16 org_w; 44 u16 org_h; 45 u16 target_w; 46 u16 target_h; 47}; 48 49/** 50 * struct mtk_mdp_fmt - the driver's internal color format data 51 * @pixelformat: the fourcc code for this format, 0 if not applicable 52 * @num_planes: number of physically non-contiguous data planes 53 * @num_comp: number of logical data planes 54 * @depth: per plane driver's private 'number of bits per pixel' 55 * @row_depth: per plane driver's private 'number of bits per pixel per row' 56 * @flags: flags indicating which operation mode format applies to 57 MTK_MDP_FMT_FLAG_OUTPUT is used in OUTPUT stream 58 MTK_MDP_FMT_FLAG_CAPTURE is used in CAPTURE stream 59 * @align: pointer to a pixel alignment struct, NULL if using default value 60 */ 61struct mtk_mdp_fmt { 62 u32 pixelformat; 63 u16 num_planes; 64 u16 num_comp; 65 u8 depth[VIDEO_MAX_PLANES]; 66 u8 row_depth[VIDEO_MAX_PLANES]; 67 u32 flags; 68 struct mtk_mdp_pix_align *align; 69}; 70 71/** 72 * struct mtk_mdp_addr - the image processor physical address set 73 * @addr: address of planes 74 */ 75struct mtk_mdp_addr { 76 dma_addr_t addr[MTK_MDP_MAX_NUM_PLANE]; 77}; 78 79/* struct mtk_mdp_ctrls - the image processor control set 80 * @rotate: rotation degree 81 * @hflip: horizontal flip 82 * @vflip: vertical flip 83 * @global_alpha: the alpha value of current frame 84 */ 85struct mtk_mdp_ctrls { 86 struct v4l2_ctrl *rotate; 87 struct v4l2_ctrl *hflip; 88 struct v4l2_ctrl *vflip; 89 struct v4l2_ctrl *global_alpha; 90}; 91 92/** 93 * struct mtk_mdp_frame - source/target frame properties 94 * @width: SRC : SRCIMG_WIDTH, DST : OUTPUTDMA_WHOLE_IMG_WIDTH 95 * @height: SRC : SRCIMG_HEIGHT, DST : OUTPUTDMA_WHOLE_IMG_HEIGHT 96 * @crop: cropped(source)/scaled(destination) size 97 * @payload: image size in bytes (w x h x bpp) 98 * @pitch: bytes per line of image in memory 99 * @addr: image frame buffer physical addresses 100 * @fmt: color format pointer 101 * @alpha: frame's alpha value 102 */ 103struct mtk_mdp_frame { 104 u32 width; 105 u32 height; 106 struct v4l2_rect crop; 107 unsigned long payload[VIDEO_MAX_PLANES]; 108 unsigned int pitch[VIDEO_MAX_PLANES]; 109 struct mtk_mdp_addr addr; 110 const struct mtk_mdp_fmt *fmt; 111 u8 alpha; 112}; 113 114/** 115 * struct mtk_mdp_variant - image processor variant information 116 * @pix_max: maximum limit of image size 117 * @pix_min: minimum limit of image size 118 * @pix_align: alignment of image 119 * @h_scale_up_max: maximum scale-up in horizontal 120 * @v_scale_up_max: maximum scale-up in vertical 121 * @h_scale_down_max: maximum scale-down in horizontal 122 * @v_scale_down_max: maximum scale-down in vertical 123 */ 124struct mtk_mdp_variant { 125 struct mtk_mdp_pix_limit *pix_max; 126 struct mtk_mdp_pix_limit *pix_min; 127 struct mtk_mdp_pix_align *pix_align; 128 u16 h_scale_up_max; 129 u16 v_scale_up_max; 130 u16 h_scale_down_max; 131 u16 v_scale_down_max; 132}; 133 134/** 135 * struct mtk_mdp_dev - abstraction for image processor entity 136 * @lock: the mutex protecting this data structure 137 * @vpulock: the mutex protecting the communication with VPU 138 * @pdev: pointer to the image processor platform device 139 * @variant: the IP variant information 140 * @id: image processor device index (0..MTK_MDP_MAX_DEVS) 141 * @comp: MDP function components 142 * @m2m_dev: v4l2 memory-to-memory device data 143 * @ctx_list: list of struct mtk_mdp_ctx 144 * @vdev: video device for image processor driver 145 * @v4l2_dev: V4L2 device to register video devices for. 146 * @job_wq: processor work queue 147 * @vpu_dev: VPU platform device 148 * @ctx_num: counter of active MTK MDP context 149 * @id_counter: An integer id given to the next opened context 150 * @wdt_wq: work queue for VPU watchdog 151 * @wdt_work: worker for VPU watchdog 152 */ 153struct mtk_mdp_dev { 154 struct mutex lock; 155 struct mutex vpulock; 156 struct platform_device *pdev; 157 struct mtk_mdp_variant *variant; 158 u16 id; 159 struct mtk_mdp_comp *comp[MTK_MDP_COMP_ID_MAX]; 160 struct v4l2_m2m_dev *m2m_dev; 161 struct list_head ctx_list; 162 struct video_device *vdev; 163 struct v4l2_device v4l2_dev; 164 struct workqueue_struct *job_wq; 165 struct platform_device *vpu_dev; 166 int ctx_num; 167 unsigned long id_counter; 168 struct workqueue_struct *wdt_wq; 169 struct work_struct wdt_work; 170}; 171 172/** 173 * mtk_mdp_ctx - the device context data 174 * @list: link to ctx_list of mtk_mdp_dev 175 * @s_frame: source frame properties 176 * @d_frame: destination frame properties 177 * @id: index of the context that this structure describes 178 * @flags: additional flags for image conversion 179 * @state: flags to keep track of user configuration 180 Protected by slock 181 * @rotation: rotates the image by specified angle 182 * @hflip: mirror the picture horizontally 183 * @vflip: mirror the picture vertically 184 * @mdp_dev: the image processor device this context applies to 185 * @m2m_ctx: memory-to-memory device context 186 * @fh: v4l2 file handle 187 * @ctrl_handler: v4l2 controls handler 188 * @ctrls image processor control set 189 * @ctrls_rdy: true if the control handler is initialized 190 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat 191 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding 192 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function 193 * @quant: enum v4l2_quantization, colorspace quantization 194 * @vpu: VPU instance 195 * @slock: the mutex protecting mtp_mdp_ctx.state 196 * @work: worker for image processing 197 */ 198struct mtk_mdp_ctx { 199 struct list_head list; 200 struct mtk_mdp_frame s_frame; 201 struct mtk_mdp_frame d_frame; 202 u32 flags; 203 u32 state; 204 int id; 205 int rotation; 206 u32 hflip:1; 207 u32 vflip:1; 208 struct mtk_mdp_dev *mdp_dev; 209 struct v4l2_m2m_ctx *m2m_ctx; 210 struct v4l2_fh fh; 211 struct v4l2_ctrl_handler ctrl_handler; 212 struct mtk_mdp_ctrls ctrls; 213 bool ctrls_rdy; 214 enum v4l2_colorspace colorspace; 215 enum v4l2_ycbcr_encoding ycbcr_enc; 216 enum v4l2_xfer_func xfer_func; 217 enum v4l2_quantization quant; 218 219 struct mtk_mdp_vpu vpu; 220 struct mutex slock; 221 struct work_struct work; 222}; 223 224extern int mtk_mdp_dbg_level; 225 226#if defined(DEBUG) 227 228#define mtk_mdp_dbg(level, fmt, args...) \ 229 do { \ 230 if (mtk_mdp_dbg_level >= level) \ 231 pr_info("[MTK_MDP] level=%d %s(),%d: " fmt "\n", \ 232 level, __func__, __LINE__, ##args); \ 233 } while (0) 234 235#define mtk_mdp_err(fmt, args...) \ 236 pr_err("[MTK_MDP][ERROR] %s:%d: " fmt "\n", __func__, __LINE__, \ 237 ##args) 238 239 240#define mtk_mdp_dbg_enter() mtk_mdp_dbg(3, "+") 241#define mtk_mdp_dbg_leave() mtk_mdp_dbg(3, "-") 242 243#else 244 245#define mtk_mdp_dbg(level, fmt, args...) {} 246#define mtk_mdp_err(fmt, args...) 247#define mtk_mdp_dbg_enter() 248#define mtk_mdp_dbg_leave() 249 250#endif 251 252#endif /* __MTK_MDP_CORE_H__ */ 253