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10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <media/media-entity.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-subdev.h>
22
23#include "camss-ispif.h"
24#include "camss.h"
25
26#define MSM_ISPIF_NAME "msm_ispif"
27
28#define ISPIF_RST_CMD_0 0x008
29#define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
30#define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
31#define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
32#define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
33#define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
34#define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
35#define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
36#define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
37#define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
38#define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
39#define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
40#define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
41#define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
42#define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
43#define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
44#define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
45#define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
46#define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
47#define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
48#define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
49#define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
50#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
51#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
52#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
53#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
54#define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
55#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
56#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
57#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
58#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
59#define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
60#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
61#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
62#define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
63#define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
64#define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
65#define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
66#define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
67#define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
68#define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
69#define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
70#define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
71#define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
72#define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
73#define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
74#define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
75#define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
76#define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
77 (0x254 + 0x200 * (m) + 0x4 * (n))
78#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
79 (0x264 + 0x200 * (m) + 0x4 * (n))
80
81#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
82 (0x270 + 0x200 * (m) + 0x4 * (n))
83#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
84 (0x27c + 0x200 * (m) + 0x4 * (n))
85#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
86 (1 << ((cid % 8) * 4))
87#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
88 (0x2c0 + 0x200 * (m) + 0x4 * (n))
89#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
90 (0x2d0 + 0x200 * (m) + 0x4 * (n))
91
92#define CSI_PIX_CLK_MUX_SEL 0x000
93#define CSI_RDI_CLK_MUX_SEL 0x008
94
95#define ISPIF_TIMEOUT_SLEEP_US 1000
96#define ISPIF_TIMEOUT_ALL_US 1000000
97#define ISPIF_RESET_TIMEOUT_MS 500
98
99enum ispif_intf_cmd {
100 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
101 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
102 CMD_DISABLE_IMMEDIATELY = 0x2,
103 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
104 CMD_ALL_NO_CHANGE = 0xffffffff,
105};
106
107static const u32 ispif_formats_8x16[] = {
108 MEDIA_BUS_FMT_UYVY8_2X8,
109 MEDIA_BUS_FMT_VYUY8_2X8,
110 MEDIA_BUS_FMT_YUYV8_2X8,
111 MEDIA_BUS_FMT_YVYU8_2X8,
112 MEDIA_BUS_FMT_SBGGR8_1X8,
113 MEDIA_BUS_FMT_SGBRG8_1X8,
114 MEDIA_BUS_FMT_SGRBG8_1X8,
115 MEDIA_BUS_FMT_SRGGB8_1X8,
116 MEDIA_BUS_FMT_SBGGR10_1X10,
117 MEDIA_BUS_FMT_SGBRG10_1X10,
118 MEDIA_BUS_FMT_SGRBG10_1X10,
119 MEDIA_BUS_FMT_SRGGB10_1X10,
120 MEDIA_BUS_FMT_SBGGR12_1X12,
121 MEDIA_BUS_FMT_SGBRG12_1X12,
122 MEDIA_BUS_FMT_SGRBG12_1X12,
123 MEDIA_BUS_FMT_SRGGB12_1X12,
124 MEDIA_BUS_FMT_Y10_1X10,
125};
126
127static const u32 ispif_formats_8x96[] = {
128 MEDIA_BUS_FMT_UYVY8_2X8,
129 MEDIA_BUS_FMT_VYUY8_2X8,
130 MEDIA_BUS_FMT_YUYV8_2X8,
131 MEDIA_BUS_FMT_YVYU8_2X8,
132 MEDIA_BUS_FMT_SBGGR8_1X8,
133 MEDIA_BUS_FMT_SGBRG8_1X8,
134 MEDIA_BUS_FMT_SGRBG8_1X8,
135 MEDIA_BUS_FMT_SRGGB8_1X8,
136 MEDIA_BUS_FMT_SBGGR10_1X10,
137 MEDIA_BUS_FMT_SGBRG10_1X10,
138 MEDIA_BUS_FMT_SGRBG10_1X10,
139 MEDIA_BUS_FMT_SRGGB10_1X10,
140 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
141 MEDIA_BUS_FMT_SBGGR12_1X12,
142 MEDIA_BUS_FMT_SGBRG12_1X12,
143 MEDIA_BUS_FMT_SGRBG12_1X12,
144 MEDIA_BUS_FMT_SRGGB12_1X12,
145 MEDIA_BUS_FMT_SBGGR14_1X14,
146 MEDIA_BUS_FMT_SGBRG14_1X14,
147 MEDIA_BUS_FMT_SGRBG14_1X14,
148 MEDIA_BUS_FMT_SRGGB14_1X14,
149 MEDIA_BUS_FMT_Y10_1X10,
150 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
151};
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158
159
160static irqreturn_t ispif_isr_8x96(int irq, void *dev)
161{
162 struct ispif_device *ispif = dev;
163 u32 value0, value1, value2, value3, value4, value5;
164
165 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
166 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
167 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
168 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
169 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
170 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
171
172 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
173 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
174 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
175 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
176 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
177 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
178
179 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
180
181 if ((value0 >> 27) & 0x1)
182 complete(&ispif->reset_complete);
183
184 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
185 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
186
187 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
188 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n");
189
190 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
191 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n");
192
193 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
194 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n");
195
196 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
197 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n");
198
199 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
200 dev_err_ratelimited(to_device(ispif), "VFE1 pix0 overflow\n");
201
202 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
203 dev_err_ratelimited(to_device(ispif), "VFE1 rdi0 overflow\n");
204
205 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
206 dev_err_ratelimited(to_device(ispif), "VFE1 pix1 overflow\n");
207
208 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
209 dev_err_ratelimited(to_device(ispif), "VFE1 rdi1 overflow\n");
210
211 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
212 dev_err_ratelimited(to_device(ispif), "VFE1 rdi2 overflow\n");
213
214 return IRQ_HANDLED;
215}
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220
221
222
223
224static irqreturn_t ispif_isr_8x16(int irq, void *dev)
225{
226 struct ispif_device *ispif = dev;
227 u32 value0, value1, value2;
228
229 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
230 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
231 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
232
233 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
234 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
235 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
236
237 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
238
239 if ((value0 >> 27) & 0x1)
240 complete(&ispif->reset_complete);
241
242 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
243 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
244
245 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
246 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n");
247
248 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
249 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n");
250
251 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
252 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n");
253
254 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
255 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n");
256
257 return IRQ_HANDLED;
258}
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260
261
262
263
264
265
266static int ispif_reset(struct ispif_device *ispif)
267{
268 unsigned long time;
269 u32 val;
270 int ret;
271
272 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0);
273 if (ret < 0)
274 return ret;
275
276 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1);
277 if (ret < 0)
278 return ret;
279
280 ret = camss_enable_clocks(ispif->nclocks_for_reset,
281 ispif->clock_for_reset,
282 to_device(ispif));
283 if (ret < 0)
284 return ret;
285
286 reinit_completion(&ispif->reset_complete);
287
288 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
289 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
290 ISPIF_RST_CMD_0_SW_REG_RST |
291 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
292 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
293 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
294 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
295 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
296 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
297 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
298 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
299 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
300 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
301 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
302 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
303 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
304 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
305
306 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
307
308 time = wait_for_completion_timeout(&ispif->reset_complete,
309 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
310 if (!time) {
311 dev_err(to_device(ispif), "ISPIF reset timeout\n");
312 ret = -EIO;
313 }
314
315 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
316
317 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE0);
318 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE1);
319
320 return ret;
321}
322
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325
326
327
328
329
330static int ispif_set_power(struct v4l2_subdev *sd, int on)
331{
332 struct ispif_line *line = v4l2_get_subdevdata(sd);
333 struct ispif_device *ispif = line->ispif;
334 struct device *dev = to_device(ispif);
335 int ret = 0;
336
337 mutex_lock(&ispif->power_lock);
338
339 if (on) {
340 if (ispif->power_count) {
341
342 ispif->power_count++;
343 goto exit;
344 }
345
346 ret = pm_runtime_get_sync(dev);
347 if (ret < 0)
348 goto exit;
349
350 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
351 if (ret < 0) {
352 pm_runtime_put_sync(dev);
353 goto exit;
354 }
355
356 ret = ispif_reset(ispif);
357 if (ret < 0) {
358 pm_runtime_put_sync(dev);
359 camss_disable_clocks(ispif->nclocks, ispif->clock);
360 goto exit;
361 }
362
363 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
364 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
365
366 ispif->power_count++;
367 } else {
368 if (ispif->power_count == 0) {
369 dev_err(dev, "ispif power off on power_count == 0\n");
370 goto exit;
371 } else if (ispif->power_count == 1) {
372 camss_disable_clocks(ispif->nclocks, ispif->clock);
373 pm_runtime_put_sync(dev);
374 }
375
376 ispif->power_count--;
377 }
378
379exit:
380 mutex_unlock(&ispif->power_lock);
381
382 return ret;
383}
384
385
386
387
388
389
390
391
392
393static void ispif_select_clk_mux(struct ispif_device *ispif,
394 enum ispif_intf intf, u8 csid,
395 u8 vfe, u8 enable)
396{
397 u32 val;
398
399 switch (intf) {
400 case PIX0:
401 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
402 val &= ~(0xf << (vfe * 8));
403 if (enable)
404 val |= (csid << (vfe * 8));
405 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
406 break;
407
408 case RDI0:
409 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
410 val &= ~(0xf << (vfe * 12));
411 if (enable)
412 val |= (csid << (vfe * 12));
413 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
414 break;
415
416 case PIX1:
417 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
418 val &= ~(0xf << (4 + (vfe * 8)));
419 if (enable)
420 val |= (csid << (4 + (vfe * 8)));
421 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
422 break;
423
424 case RDI1:
425 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
426 val &= ~(0xf << (4 + (vfe * 12)));
427 if (enable)
428 val |= (csid << (4 + (vfe * 12)));
429 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
430 break;
431
432 case RDI2:
433 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
434 val &= ~(0xf << (8 + (vfe * 12)));
435 if (enable)
436 val |= (csid << (8 + (vfe * 12)));
437 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
438 break;
439 }
440
441 mb();
442}
443
444
445
446
447
448
449
450
451
452static int ispif_validate_intf_status(struct ispif_device *ispif,
453 enum ispif_intf intf, u8 vfe)
454{
455 int ret = 0;
456 u32 val = 0;
457
458 switch (intf) {
459 case PIX0:
460 val = readl_relaxed(ispif->base +
461 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
462 break;
463 case RDI0:
464 val = readl_relaxed(ispif->base +
465 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
466 break;
467 case PIX1:
468 val = readl_relaxed(ispif->base +
469 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
470 break;
471 case RDI1:
472 val = readl_relaxed(ispif->base +
473 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
474 break;
475 case RDI2:
476 val = readl_relaxed(ispif->base +
477 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
478 break;
479 }
480
481 if ((val & 0xf) != 0xf) {
482 dev_err(to_device(ispif), "%s: ispif is busy: 0x%x\n",
483 __func__, val);
484 ret = -EBUSY;
485 }
486
487 return ret;
488}
489
490
491
492
493
494
495
496
497
498static int ispif_wait_for_stop(struct ispif_device *ispif,
499 enum ispif_intf intf, u8 vfe)
500{
501 u32 addr = 0;
502 u32 stop_flag = 0;
503 int ret;
504
505 switch (intf) {
506 case PIX0:
507 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
508 break;
509 case RDI0:
510 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
511 break;
512 case PIX1:
513 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
514 break;
515 case RDI1:
516 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
517 break;
518 case RDI2:
519 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
520 break;
521 }
522
523 ret = readl_poll_timeout(ispif->base + addr,
524 stop_flag,
525 (stop_flag & 0xf) == 0xf,
526 ISPIF_TIMEOUT_SLEEP_US,
527 ISPIF_TIMEOUT_ALL_US);
528 if (ret < 0)
529 dev_err(to_device(ispif), "%s: ispif stop timeout\n",
530 __func__);
531
532 return ret;
533}
534
535
536
537
538
539
540
541
542
543static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
544 u8 csid, u8 vfe, u8 enable)
545{
546 u32 val;
547
548 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
549 switch (intf) {
550 case PIX0:
551 val &= ~(BIT(1) | BIT(0));
552 if (enable)
553 val |= csid;
554 break;
555 case RDI0:
556 val &= ~(BIT(5) | BIT(4));
557 if (enable)
558 val |= (csid << 4);
559 break;
560 case PIX1:
561 val &= ~(BIT(9) | BIT(8));
562 if (enable)
563 val |= (csid << 8);
564 break;
565 case RDI1:
566 val &= ~(BIT(13) | BIT(12));
567 if (enable)
568 val |= (csid << 12);
569 break;
570 case RDI2:
571 val &= ~(BIT(21) | BIT(20));
572 if (enable)
573 val |= (csid << 20);
574 break;
575 }
576
577 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
578}
579
580
581
582
583
584
585
586
587
588static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
589 u8 cid, u8 vfe, u8 enable)
590{
591 u32 cid_mask = 1 << cid;
592 u32 addr = 0;
593 u32 val;
594
595 switch (intf) {
596 case PIX0:
597 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
598 break;
599 case RDI0:
600 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
601 break;
602 case PIX1:
603 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
604 break;
605 case RDI1:
606 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
607 break;
608 case RDI2:
609 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
610 break;
611 }
612
613 val = readl_relaxed(ispif->base + addr);
614 if (enable)
615 val |= cid_mask;
616 else
617 val &= ~cid_mask;
618
619 writel(val, ispif->base + addr);
620}
621
622
623
624
625
626
627
628
629static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
630 u8 vfe, u8 enable)
631{
632 u32 val;
633
634 switch (intf) {
635 case PIX0:
636 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
637 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
638 if (enable)
639 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
640 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
641 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
642 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
643 break;
644 case RDI0:
645 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
646 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
647 if (enable)
648 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
649 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
650 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
651 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
652 break;
653 case PIX1:
654 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
655 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
656 if (enable)
657 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
658 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
659 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
660 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
661 break;
662 case RDI1:
663 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
664 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
665 if (enable)
666 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
667 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
668 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
669 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
670 break;
671 case RDI2:
672 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
673 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
674 if (enable)
675 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
676 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
677 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
678 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
679 break;
680 }
681
682 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
683}
684
685
686
687
688
689
690
691
692
693
694static void ispif_config_pack(struct ispif_device *ispif, u32 code,
695 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
696{
697 u32 addr, val;
698
699 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
700 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
701 return;
702
703 switch (intf) {
704 case RDI0:
705 if (cid < 8)
706 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
707 else
708 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
709 break;
710 case RDI1:
711 if (cid < 8)
712 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
713 else
714 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
715 break;
716 case RDI2:
717 if (cid < 8)
718 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
719 else
720 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
721 break;
722 default:
723 return;
724 }
725
726 if (enable)
727 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
728 else
729 val = 0;
730
731 writel_relaxed(val, ispif->base + addr);
732}
733
734
735
736
737
738
739
740
741
742static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
743 enum ispif_intf intf, u8 vfe, u8 vc)
744{
745 u32 *val;
746
747 if (intf == RDI2) {
748 val = &ispif->intf_cmd[vfe].cmd_1;
749 *val &= ~(0x3 << (vc * 2 + 8));
750 *val |= (cmd << (vc * 2 + 8));
751 wmb();
752 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
753 wmb();
754 } else {
755 val = &ispif->intf_cmd[vfe].cmd_0;
756 *val &= ~(0x3 << (vc * 2 + intf * 8));
757 *val |= (cmd << (vc * 2 + intf * 8));
758 wmb();
759 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
760 wmb();
761 }
762}
763
764
765
766
767
768
769
770
771
772
773static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
774{
775 struct ispif_line *line = v4l2_get_subdevdata(sd);
776 struct ispif_device *ispif = line->ispif;
777 enum ispif_intf intf = line->interface;
778 u8 csid = line->csid_id;
779 u8 vfe = line->vfe_id;
780 u8 vc = 0;
781 u8 cid = vc * 4;
782 int ret;
783
784 if (enable) {
785 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))
786 return -ENOLINK;
787
788
789
790 mutex_lock(&ispif->config_lock);
791 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
792
793 ret = ispif_validate_intf_status(ispif, intf, vfe);
794 if (ret < 0) {
795 mutex_unlock(&ispif->config_lock);
796 return ret;
797 }
798
799 ispif_select_csid(ispif, intf, csid, vfe, 1);
800 ispif_select_cid(ispif, intf, cid, vfe, 1);
801 ispif_config_irq(ispif, intf, vfe, 1);
802 if (to_camss(ispif)->version == CAMSS_8x96)
803 ispif_config_pack(ispif,
804 line->fmt[MSM_ISPIF_PAD_SINK].code,
805 intf, cid, vfe, 1);
806 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
807 intf, vfe, vc);
808 } else {
809 mutex_lock(&ispif->config_lock);
810 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
811 intf, vfe, vc);
812 mutex_unlock(&ispif->config_lock);
813
814 ret = ispif_wait_for_stop(ispif, intf, vfe);
815 if (ret < 0)
816 return ret;
817
818 mutex_lock(&ispif->config_lock);
819 if (to_camss(ispif)->version == CAMSS_8x96)
820 ispif_config_pack(ispif,
821 line->fmt[MSM_ISPIF_PAD_SINK].code,
822 intf, cid, vfe, 0);
823 ispif_config_irq(ispif, intf, vfe, 0);
824 ispif_select_cid(ispif, intf, cid, vfe, 0);
825 ispif_select_csid(ispif, intf, csid, vfe, 0);
826 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
827 }
828
829 mutex_unlock(&ispif->config_lock);
830
831 return 0;
832}
833
834
835
836
837
838
839
840
841
842
843static struct v4l2_mbus_framefmt *
844__ispif_get_format(struct ispif_line *line,
845 struct v4l2_subdev_pad_config *cfg,
846 unsigned int pad,
847 enum v4l2_subdev_format_whence which)
848{
849 if (which == V4L2_SUBDEV_FORMAT_TRY)
850 return v4l2_subdev_get_try_format(&line->subdev, cfg, pad);
851
852 return &line->fmt[pad];
853}
854
855
856
857
858
859
860
861
862
863static void ispif_try_format(struct ispif_line *line,
864 struct v4l2_subdev_pad_config *cfg,
865 unsigned int pad,
866 struct v4l2_mbus_framefmt *fmt,
867 enum v4l2_subdev_format_whence which)
868{
869 unsigned int i;
870
871 switch (pad) {
872 case MSM_ISPIF_PAD_SINK:
873
874
875 for (i = 0; i < line->nformats; i++)
876 if (fmt->code == line->formats[i])
877 break;
878
879
880 if (i >= line->nformats)
881 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
882
883 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
884 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
885
886 fmt->field = V4L2_FIELD_NONE;
887 fmt->colorspace = V4L2_COLORSPACE_SRGB;
888
889 break;
890
891 case MSM_ISPIF_PAD_SRC:
892
893
894 *fmt = *__ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
895 which);
896
897 break;
898 }
899
900 fmt->colorspace = V4L2_COLORSPACE_SRGB;
901}
902
903
904
905
906
907
908
909
910static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
911 struct v4l2_subdev_pad_config *cfg,
912 struct v4l2_subdev_mbus_code_enum *code)
913{
914 struct ispif_line *line = v4l2_get_subdevdata(sd);
915 struct v4l2_mbus_framefmt *format;
916
917 if (code->pad == MSM_ISPIF_PAD_SINK) {
918 if (code->index >= line->nformats)
919 return -EINVAL;
920
921 code->code = line->formats[code->index];
922 } else {
923 if (code->index > 0)
924 return -EINVAL;
925
926 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
927 code->which);
928
929 code->code = format->code;
930 }
931
932 return 0;
933}
934
935
936
937
938
939
940
941
942static int ispif_enum_frame_size(struct v4l2_subdev *sd,
943 struct v4l2_subdev_pad_config *cfg,
944 struct v4l2_subdev_frame_size_enum *fse)
945{
946 struct ispif_line *line = v4l2_get_subdevdata(sd);
947 struct v4l2_mbus_framefmt format;
948
949 if (fse->index != 0)
950 return -EINVAL;
951
952 format.code = fse->code;
953 format.width = 1;
954 format.height = 1;
955 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
956 fse->min_width = format.width;
957 fse->min_height = format.height;
958
959 if (format.code != fse->code)
960 return -EINVAL;
961
962 format.code = fse->code;
963 format.width = -1;
964 format.height = -1;
965 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
966 fse->max_width = format.width;
967 fse->max_height = format.height;
968
969 return 0;
970}
971
972
973
974
975
976
977
978
979
980static int ispif_get_format(struct v4l2_subdev *sd,
981 struct v4l2_subdev_pad_config *cfg,
982 struct v4l2_subdev_format *fmt)
983{
984 struct ispif_line *line = v4l2_get_subdevdata(sd);
985 struct v4l2_mbus_framefmt *format;
986
987 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
988 if (format == NULL)
989 return -EINVAL;
990
991 fmt->format = *format;
992
993 return 0;
994}
995
996
997
998
999
1000
1001
1002
1003
1004static int ispif_set_format(struct v4l2_subdev *sd,
1005 struct v4l2_subdev_pad_config *cfg,
1006 struct v4l2_subdev_format *fmt)
1007{
1008 struct ispif_line *line = v4l2_get_subdevdata(sd);
1009 struct v4l2_mbus_framefmt *format;
1010
1011 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
1012 if (format == NULL)
1013 return -EINVAL;
1014
1015 ispif_try_format(line, cfg, fmt->pad, &fmt->format, fmt->which);
1016 *format = fmt->format;
1017
1018
1019 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1020 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SRC,
1021 fmt->which);
1022
1023 *format = fmt->format;
1024 ispif_try_format(line, cfg, MSM_ISPIF_PAD_SRC, format,
1025 fmt->which);
1026 }
1027
1028 return 0;
1029}
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1041{
1042 struct v4l2_subdev_format format = {
1043 .pad = MSM_ISPIF_PAD_SINK,
1044 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1045 V4L2_SUBDEV_FORMAT_ACTIVE,
1046 .format = {
1047 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1048 .width = 1920,
1049 .height = 1080
1050 }
1051 };
1052
1053 return ispif_set_format(sd, fh ? fh->pad : NULL, &format);
1054}
1055
1056
1057
1058
1059
1060
1061
1062
1063int msm_ispif_subdev_init(struct ispif_device *ispif,
1064 const struct resources_ispif *res)
1065{
1066 struct device *dev = to_device(ispif);
1067 struct platform_device *pdev = to_platform_device(dev);
1068 struct resource *r;
1069 int i;
1070 int ret;
1071
1072
1073 if (to_camss(ispif)->version == CAMSS_8x16)
1074 ispif->line_num = 2;
1075 else if (to_camss(ispif)->version == CAMSS_8x96)
1076 ispif->line_num = 4;
1077 else
1078 return -EINVAL;
1079
1080 ispif->line = devm_kcalloc(dev, ispif->line_num, sizeof(*ispif->line),
1081 GFP_KERNEL);
1082 if (!ispif->line)
1083 return -ENOMEM;
1084
1085 for (i = 0; i < ispif->line_num; i++) {
1086 ispif->line[i].ispif = ispif;
1087 ispif->line[i].id = i;
1088
1089 if (to_camss(ispif)->version == CAMSS_8x16) {
1090 ispif->line[i].formats = ispif_formats_8x16;
1091 ispif->line[i].nformats =
1092 ARRAY_SIZE(ispif_formats_8x16);
1093 } else if (to_camss(ispif)->version == CAMSS_8x96) {
1094 ispif->line[i].formats = ispif_formats_8x96;
1095 ispif->line[i].nformats =
1096 ARRAY_SIZE(ispif_formats_8x96);
1097 } else {
1098 return -EINVAL;
1099 }
1100 }
1101
1102
1103
1104 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
1105 ispif->base = devm_ioremap_resource(dev, r);
1106 if (IS_ERR(ispif->base)) {
1107 dev_err(dev, "could not map memory\n");
1108 return PTR_ERR(ispif->base);
1109 }
1110
1111 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
1112 ispif->base_clk_mux = devm_ioremap_resource(dev, r);
1113 if (IS_ERR(ispif->base_clk_mux)) {
1114 dev_err(dev, "could not map memory\n");
1115 return PTR_ERR(ispif->base_clk_mux);
1116 }
1117
1118
1119
1120 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt);
1121
1122 if (!r) {
1123 dev_err(dev, "missing IRQ\n");
1124 return -EINVAL;
1125 }
1126
1127 ispif->irq = r->start;
1128 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1129 dev_name(dev), MSM_ISPIF_NAME);
1130 if (to_camss(ispif)->version == CAMSS_8x16)
1131 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1132 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1133 else if (to_camss(ispif)->version == CAMSS_8x96)
1134 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1135 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1136 else
1137 ret = -EINVAL;
1138 if (ret < 0) {
1139 dev_err(dev, "request_irq failed: %d\n", ret);
1140 return ret;
1141 }
1142
1143
1144
1145 ispif->nclocks = 0;
1146 while (res->clock[ispif->nclocks])
1147 ispif->nclocks++;
1148
1149 ispif->clock = devm_kcalloc(dev,
1150 ispif->nclocks, sizeof(*ispif->clock),
1151 GFP_KERNEL);
1152 if (!ispif->clock)
1153 return -ENOMEM;
1154
1155 for (i = 0; i < ispif->nclocks; i++) {
1156 struct camss_clock *clock = &ispif->clock[i];
1157
1158 clock->clk = devm_clk_get(dev, res->clock[i]);
1159 if (IS_ERR(clock->clk))
1160 return PTR_ERR(clock->clk);
1161
1162 clock->freq = NULL;
1163 clock->nfreqs = 0;
1164 }
1165
1166 ispif->nclocks_for_reset = 0;
1167 while (res->clock_for_reset[ispif->nclocks_for_reset])
1168 ispif->nclocks_for_reset++;
1169
1170 ispif->clock_for_reset = devm_kcalloc(dev,
1171 ispif->nclocks_for_reset,
1172 sizeof(*ispif->clock_for_reset),
1173 GFP_KERNEL);
1174 if (!ispif->clock_for_reset)
1175 return -ENOMEM;
1176
1177 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1178 struct camss_clock *clock = &ispif->clock_for_reset[i];
1179
1180 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1181 if (IS_ERR(clock->clk))
1182 return PTR_ERR(clock->clk);
1183
1184 clock->freq = NULL;
1185 clock->nfreqs = 0;
1186 }
1187
1188 mutex_init(&ispif->power_lock);
1189 ispif->power_count = 0;
1190
1191 mutex_init(&ispif->config_lock);
1192
1193 init_completion(&ispif->reset_complete);
1194
1195 return 0;
1196}
1197
1198
1199
1200
1201
1202
1203
1204static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1205{
1206 switch (line_id) {
1207 case (VFE_LINE_RDI0):
1208 return RDI0;
1209 case (VFE_LINE_RDI1):
1210 return RDI1;
1211 case (VFE_LINE_RDI2):
1212 return RDI2;
1213 case (VFE_LINE_PIX):
1214 return PIX0;
1215 default:
1216 return RDI0;
1217 }
1218}
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229static int ispif_link_setup(struct media_entity *entity,
1230 const struct media_pad *local,
1231 const struct media_pad *remote, u32 flags)
1232{
1233 if (flags & MEDIA_LNK_FL_ENABLED) {
1234 if (media_entity_remote_pad(local))
1235 return -EBUSY;
1236
1237 if (local->flags & MEDIA_PAD_FL_SINK) {
1238 struct v4l2_subdev *sd;
1239 struct ispif_line *line;
1240
1241 sd = media_entity_to_v4l2_subdev(entity);
1242 line = v4l2_get_subdevdata(sd);
1243
1244 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1245 } else {
1246 struct v4l2_subdev *sd;
1247 struct ispif_line *line;
1248 enum vfe_line_id id;
1249
1250 sd = media_entity_to_v4l2_subdev(entity);
1251 line = v4l2_get_subdevdata(sd);
1252
1253 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id);
1254 msm_vfe_get_vfe_line_id(remote->entity, &id);
1255 line->interface = ispif_get_intf(id);
1256 }
1257 }
1258
1259 return 0;
1260}
1261
1262static const struct v4l2_subdev_core_ops ispif_core_ops = {
1263 .s_power = ispif_set_power,
1264};
1265
1266static const struct v4l2_subdev_video_ops ispif_video_ops = {
1267 .s_stream = ispif_set_stream,
1268};
1269
1270static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1271 .enum_mbus_code = ispif_enum_mbus_code,
1272 .enum_frame_size = ispif_enum_frame_size,
1273 .get_fmt = ispif_get_format,
1274 .set_fmt = ispif_set_format,
1275};
1276
1277static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1278 .core = &ispif_core_ops,
1279 .video = &ispif_video_ops,
1280 .pad = &ispif_pad_ops,
1281};
1282
1283static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1284 .open = ispif_init_formats,
1285};
1286
1287static const struct media_entity_operations ispif_media_ops = {
1288 .link_setup = ispif_link_setup,
1289 .link_validate = v4l2_subdev_link_validate,
1290};
1291
1292
1293
1294
1295
1296
1297
1298
1299int msm_ispif_register_entities(struct ispif_device *ispif,
1300 struct v4l2_device *v4l2_dev)
1301{
1302 struct device *dev = to_device(ispif);
1303 int ret;
1304 int i;
1305
1306 for (i = 0; i < ispif->line_num; i++) {
1307 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1308 struct media_pad *pads = ispif->line[i].pads;
1309
1310 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1311 sd->internal_ops = &ispif_v4l2_internal_ops;
1312 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1313 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1314 MSM_ISPIF_NAME, i);
1315 v4l2_set_subdevdata(sd, &ispif->line[i]);
1316
1317 ret = ispif_init_formats(sd, NULL);
1318 if (ret < 0) {
1319 dev_err(dev, "Failed to init format: %d\n", ret);
1320 goto error;
1321 }
1322
1323 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1324 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1325
1326 sd->entity.function = MEDIA_ENT_F_IO_V4L;
1327 sd->entity.ops = &ispif_media_ops;
1328 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1329 pads);
1330 if (ret < 0) {
1331 dev_err(dev, "Failed to init media entity: %d\n", ret);
1332 goto error;
1333 }
1334
1335 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1336 if (ret < 0) {
1337 dev_err(dev, "Failed to register subdev: %d\n", ret);
1338 media_entity_cleanup(&sd->entity);
1339 goto error;
1340 }
1341 }
1342
1343 return 0;
1344
1345error:
1346 for (i--; i >= 0; i--) {
1347 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1348
1349 v4l2_device_unregister_subdev(sd);
1350 media_entity_cleanup(&sd->entity);
1351 }
1352
1353 return ret;
1354}
1355
1356
1357
1358
1359
1360void msm_ispif_unregister_entities(struct ispif_device *ispif)
1361{
1362 int i;
1363
1364 mutex_destroy(&ispif->power_lock);
1365 mutex_destroy(&ispif->config_lock);
1366
1367 for (i = 0; i < ispif->line_num; i++) {
1368 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1369
1370 v4l2_device_unregister_subdev(sd);
1371 media_entity_cleanup(&sd->entity);
1372 }
1373}
1374
