linux/drivers/media/platform/s3c-camif/camif-core.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * s3c24xx/s3c64xx SoC series Camera Interface (CAMIF) driver
   4 *
   5 * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
   6 * Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
   7*/
   8
   9#ifndef CAMIF_CORE_H_
  10#define CAMIF_CORE_H_
  11
  12#include <linux/io.h>
  13#include <linux/irq.h>
  14#include <linux/platform_device.h>
  15#include <linux/sched.h>
  16#include <linux/spinlock.h>
  17#include <linux/types.h>
  18#include <linux/videodev2.h>
  19
  20#include <media/media-entity.h>
  21#include <media/v4l2-ctrls.h>
  22#include <media/v4l2-dev.h>
  23#include <media/v4l2-device.h>
  24#include <media/v4l2-mediabus.h>
  25#include <media/videobuf2-v4l2.h>
  26#include <media/drv-intf/s3c_camif.h>
  27
  28#define S3C_CAMIF_DRIVER_NAME   "s3c-camif"
  29#define CAMIF_REQ_BUFS_MIN      3
  30#define CAMIF_MAX_OUT_BUFS      4
  31#define CAMIF_MAX_PIX_WIDTH     4096
  32#define CAMIF_MAX_PIX_HEIGHT    4096
  33#define SCALER_MAX_RATIO        64
  34#define CAMIF_DEF_WIDTH         640
  35#define CAMIF_DEF_HEIGHT        480
  36#define CAMIF_STOP_TIMEOUT      1500 /* ms */
  37
  38#define S3C244X_CAMIF_IP_REV    0x20 /* 2.0 */
  39#define S3C2450_CAMIF_IP_REV    0x30 /* 3.0 - not implemented, not tested */
  40#define S3C6400_CAMIF_IP_REV    0x31 /* 3.1 - not implemented, not tested */
  41#define S3C6410_CAMIF_IP_REV    0x32 /* 3.2 */
  42
  43/* struct camif_vp::state */
  44
  45#define ST_VP_PENDING           (1 << 0)
  46#define ST_VP_RUNNING           (1 << 1)
  47#define ST_VP_STREAMING         (1 << 2)
  48#define ST_VP_SENSOR_STREAMING  (1 << 3)
  49
  50#define ST_VP_ABORTING          (1 << 4)
  51#define ST_VP_OFF               (1 << 5)
  52#define ST_VP_LASTIRQ           (1 << 6)
  53
  54#define ST_VP_CONFIG            (1 << 8)
  55
  56#define CAMIF_SD_PAD_SINK       0
  57#define CAMIF_SD_PAD_SOURCE_C   1
  58#define CAMIF_SD_PAD_SOURCE_P   2
  59#define CAMIF_SD_PADS_NUM       3
  60
  61enum img_fmt {
  62        IMG_FMT_RGB565 = 0x0010,
  63        IMG_FMT_RGB666,
  64        IMG_FMT_XRGB8888,
  65        IMG_FMT_YCBCR420 = 0x0020,
  66        IMG_FMT_YCRCB420,
  67        IMG_FMT_YCBCR422P,
  68        IMG_FMT_YCBYCR422 = 0x0040,
  69        IMG_FMT_YCRYCB422,
  70        IMG_FMT_CBYCRY422,
  71        IMG_FMT_CRYCBY422,
  72};
  73
  74#define img_fmt_is_rgb(x) ((x) & 0x10)
  75#define img_fmt_is_ycbcr(x) ((x) & 0x60)
  76
  77/* Possible values for struct camif_fmt::flags */
  78#define FMT_FL_S3C24XX_CODEC    (1 << 0)
  79#define FMT_FL_S3C24XX_PREVIEW  (1 << 1)
  80#define FMT_FL_S3C64XX          (1 << 2)
  81
  82/**
  83 * struct camif_fmt - pixel format description
  84 * @fourcc:    fourcc code for this format, 0 if not applicable
  85 * @color:     a corresponding enum img_fmt
  86 * @colplanes: number of physically contiguous data planes
  87 * @flags:     indicate for which SoCs revisions this format is valid
  88 * @depth:     bits per pixel (total)
  89 * @ybpp:      number of luminance bytes per pixel
  90 */
  91struct camif_fmt {
  92        char *name;
  93        u32 fourcc;
  94        u32 color;
  95        u16 colplanes;
  96        u16 flags;
  97        u8 depth;
  98        u8 ybpp;
  99};
 100
 101/**
 102 * struct camif_dma_offset - pixel offset information for DMA
 103 * @initial: offset (in pixels) to first pixel
 104 * @line: offset (in pixels) from end of line to start of next line
 105 */
 106struct camif_dma_offset {
 107        int     initial;
 108        int     line;
 109};
 110
 111/**
 112 * struct camif_frame - source/target frame properties
 113 * @f_width: full pixel width
 114 * @f_height: full pixel height
 115 * @rect: crop/composition rectangle
 116 * @dma_offset: DMA offset configuration
 117 */
 118struct camif_frame {
 119        u16 f_width;
 120        u16 f_height;
 121        struct v4l2_rect rect;
 122        struct camif_dma_offset dma_offset;
 123};
 124
 125/* CAMIF clocks enumeration */
 126enum {
 127        CLK_GATE,
 128        CLK_CAM,
 129        CLK_MAX_NUM,
 130};
 131
 132struct vp_pix_limits {
 133        u16 max_out_width;
 134        u16 max_sc_out_width;
 135        u16 out_width_align;
 136        u16 max_height;
 137        u8 min_out_width;
 138        u16 out_hor_offset_align;
 139};
 140
 141struct camif_pix_limits {
 142        u16 win_hor_offset_align;
 143};
 144
 145/**
 146 * struct s3c_camif_variant - CAMIF variant structure
 147 * @vp_pix_limits:    pixel limits for the codec and preview paths
 148 * @camif_pix_limits: pixel limits for the camera input interface
 149 * @ip_revision:      the CAMIF IP revision: 0x20 for s3c244x, 0x32 for s3c6410
 150 */
 151struct s3c_camif_variant {
 152        struct vp_pix_limits vp_pix_limits[2];
 153        struct camif_pix_limits pix_limits;
 154        u8 ip_revision;
 155        u8 has_img_effect;
 156        unsigned int vp_offset;
 157};
 158
 159struct s3c_camif_drvdata {
 160        const struct s3c_camif_variant *variant;
 161        unsigned long bus_clk_freq;
 162};
 163
 164struct camif_scaler {
 165        u8 scaleup_h;
 166        u8 scaleup_v;
 167        u8 copy;
 168        u8 enable;
 169        u32 h_shift;
 170        u32 v_shift;
 171        u32 pre_h_ratio;
 172        u32 pre_v_ratio;
 173        u32 pre_dst_width;
 174        u32 pre_dst_height;
 175        u32 main_h_ratio;
 176        u32 main_v_ratio;
 177};
 178
 179struct camif_dev;
 180
 181/**
 182 * struct camif_vp - CAMIF data processing path structure (codec/preview)
 183 * @irq_queue:      interrupt handling waitqueue
 184 * @irq:            interrupt number for this data path
 185 * @camif:          pointer to the camif structure
 186 * @pad:            media pad for the video node
 187 * @vdev            video device
 188 * @ctrl_handler:   video node controls handler
 189 * @owner:          file handle that own the streaming
 190 * @pending_buf_q:  pending (empty) buffers queue head
 191 * @active_buf_q:   active (being written) buffers queue head
 192 * @active_buffers: counter of buffer set up at the DMA engine
 193 * @buf_index:      identifier of a last empty buffer set up in H/W
 194 * @frame_sequence: image frame sequence counter
 195 * @reqbufs_count:  the number of buffers requested
 196 * @scaler:         the scaler structure
 197 * @out_fmt:        pixel format at this video path output
 198 * @payload:        the output data frame payload size
 199 * @out_frame:      the output pixel resolution
 200 * @state:          the video path's state
 201 * @fmt_flags:      flags determining supported pixel formats
 202 * @id:             CAMIF id, 0 - codec, 1 - preview
 203 * @rotation:       current image rotation value
 204 * @hflip:          apply horizontal flip if set
 205 * @vflip:          apply vertical flip if set
 206 */
 207struct camif_vp {
 208        wait_queue_head_t       irq_queue;
 209        int                     irq;
 210        struct camif_dev        *camif;
 211        struct media_pad        pad;
 212        struct video_device     vdev;
 213        struct v4l2_ctrl_handler ctrl_handler;
 214        struct v4l2_fh          *owner;
 215        struct vb2_queue        vb_queue;
 216        struct list_head        pending_buf_q;
 217        struct list_head        active_buf_q;
 218        unsigned int            active_buffers;
 219        unsigned int            buf_index;
 220        unsigned int            frame_sequence;
 221        unsigned int            reqbufs_count;
 222        struct camif_scaler     scaler;
 223        const struct camif_fmt  *out_fmt;
 224        unsigned int            payload;
 225        struct camif_frame      out_frame;
 226        unsigned int            state;
 227        u16                     fmt_flags;
 228        u8                      id;
 229        u16                     rotation;
 230        u8                      hflip;
 231        u8                      vflip;
 232        unsigned int            offset;
 233};
 234
 235/* Video processing path enumeration */
 236#define VP_CODEC        0
 237#define VP_PREVIEW      1
 238#define CAMIF_VP_NUM    2
 239
 240/**
 241 * struct camif_dev - the CAMIF driver private data structure
 242 * @media_dev:    top-level media device structure
 243 * @v4l2_dev:     root v4l2_device
 244 * @subdev:       camera interface ("catchcam") subdev
 245 * @mbus_fmt:     camera input media bus format
 246 * @camif_crop:   camera input interface crop rectangle
 247 * @pads:         the camif subdev's media pads
 248 * @stream_count: the camera interface streaming reference counter
 249 * @sensor:       image sensor data structure
 250 * @m_pipeline:   video entity pipeline description
 251 * @ctrl_handler: v4l2 control handler (owned by @subdev)
 252 * @test_pattern: test pattern controls
 253 * @vp:           video path (DMA) description (codec/preview)
 254 * @variant:      variant information for this device
 255 * @dev:          pointer to the CAMIF device struct
 256 * @pdata:        a copy of the driver's platform data
 257 * @clock:        clocks required for the CAMIF operation
 258 * @lock:         mutex protecting this data structure
 259 * @slock:        spinlock protecting CAMIF registers
 260 * @io_base:      start address of the mmapped CAMIF registers
 261 */
 262struct camif_dev {
 263        struct media_device             media_dev;
 264        struct v4l2_device              v4l2_dev;
 265        struct v4l2_subdev              subdev;
 266        struct v4l2_mbus_framefmt       mbus_fmt;
 267        struct v4l2_rect                camif_crop;
 268        struct media_pad                pads[CAMIF_SD_PADS_NUM];
 269        int                             stream_count;
 270
 271        struct cam_sensor {
 272                struct v4l2_subdev      *sd;
 273                short                   power_count;
 274                short                   stream_count;
 275        } sensor;
 276        struct media_pipeline           *m_pipeline;
 277
 278        struct v4l2_ctrl_handler        ctrl_handler;
 279        struct v4l2_ctrl                *ctrl_test_pattern;
 280        struct {
 281                struct v4l2_ctrl        *ctrl_colorfx;
 282                struct v4l2_ctrl        *ctrl_colorfx_cbcr;
 283        };
 284        u8                              test_pattern;
 285        u8                              colorfx;
 286        u8                              colorfx_cb;
 287        u8                              colorfx_cr;
 288
 289        struct camif_vp                 vp[CAMIF_VP_NUM];
 290
 291        const struct s3c_camif_variant  *variant;
 292        struct device                   *dev;
 293        struct s3c_camif_plat_data      pdata;
 294        struct clk                      *clock[CLK_MAX_NUM];
 295        struct mutex                    lock;
 296        spinlock_t                      slock;
 297        void __iomem                    *io_base;
 298};
 299
 300/**
 301 * struct camif_addr - Y/Cb/Cr DMA start address structure
 302 * @y:   luminance plane dma address
 303 * @cb:  Cb plane dma address
 304 * @cr:  Cr plane dma address
 305 */
 306struct camif_addr {
 307        dma_addr_t y;
 308        dma_addr_t cb;
 309        dma_addr_t cr;
 310};
 311
 312/**
 313 * struct camif_buffer - the camif video buffer structure
 314 * @vb:    vb2 buffer
 315 * @list:  list head for the buffers queue
 316 * @paddr: DMA start addresses
 317 * @index: an identifier of this buffer at the DMA engine
 318 */
 319struct camif_buffer {
 320        struct vb2_v4l2_buffer vb;
 321        struct list_head list;
 322        struct camif_addr paddr;
 323        unsigned int index;
 324};
 325
 326const struct camif_fmt *s3c_camif_find_format(struct camif_vp *vp,
 327              const u32 *pixelformat, int index);
 328int s3c_camif_register_video_node(struct camif_dev *camif, int idx);
 329void s3c_camif_unregister_video_node(struct camif_dev *camif, int idx);
 330irqreturn_t s3c_camif_irq_handler(int irq, void *priv);
 331int s3c_camif_create_subdev(struct camif_dev *camif);
 332void s3c_camif_unregister_subdev(struct camif_dev *camif);
 333int s3c_camif_set_defaults(struct camif_dev *camif);
 334int s3c_camif_get_scaler_config(struct camif_vp *vp,
 335                                struct camif_scaler *scaler);
 336
 337static inline void camif_active_queue_add(struct camif_vp *vp,
 338                                          struct camif_buffer *buf)
 339{
 340        list_add_tail(&buf->list, &vp->active_buf_q);
 341        vp->active_buffers++;
 342}
 343
 344static inline struct camif_buffer *camif_active_queue_pop(
 345                                        struct camif_vp *vp)
 346{
 347        struct camif_buffer *buf = list_first_entry(&vp->active_buf_q,
 348                                              struct camif_buffer, list);
 349        list_del(&buf->list);
 350        vp->active_buffers--;
 351        return buf;
 352}
 353
 354static inline struct camif_buffer *camif_active_queue_peek(
 355                           struct camif_vp *vp, int index)
 356{
 357        struct camif_buffer *tmp, *buf;
 358
 359        if (WARN_ON(list_empty(&vp->active_buf_q)))
 360                return NULL;
 361
 362        list_for_each_entry_safe(buf, tmp, &vp->active_buf_q, list) {
 363                if (buf->index == index) {
 364                        list_del(&buf->list);
 365                        vp->active_buffers--;
 366                        return buf;
 367                }
 368        }
 369
 370        return NULL;
 371}
 372
 373static inline void camif_pending_queue_add(struct camif_vp *vp,
 374                                           struct camif_buffer *buf)
 375{
 376        list_add_tail(&buf->list, &vp->pending_buf_q);
 377}
 378
 379static inline struct camif_buffer *camif_pending_queue_pop(
 380                                        struct camif_vp *vp)
 381{
 382        struct camif_buffer *buf = list_first_entry(&vp->pending_buf_q,
 383                                              struct camif_buffer, list);
 384        list_del(&buf->list);
 385        return buf;
 386}
 387
 388#endif /* CAMIF_CORE_H_ */
 389