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17#include <linux/delay.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/fs.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioctl.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/sched.h>
29#include <linux/slab.h>
30#include <linux/videodev2.h>
31#include <linux/log2.h>
32#include <linux/sizes.h>
33
34#include <media/v4l2-common.h>
35#include <media/v4l2-ctrls.h>
36#include <media/v4l2-device.h>
37#include <media/v4l2-event.h>
38#include <media/v4l2-ioctl.h>
39#include <media/v4l2-mem2mem.h>
40#include <media/videobuf2-v4l2.h>
41#include <media/videobuf2-dma-contig.h>
42
43#include "vpdma.h"
44#include "vpdma_priv.h"
45#include "vpe_regs.h"
46#include "sc.h"
47#include "csc.h"
48
49#define VPE_MODULE_NAME "vpe"
50
51
52#define MIN_W 32
53#define MIN_H 32
54#define MAX_W 2048
55#define MAX_H 1184
56
57
58#define S_ALIGN 0
59#define H_ALIGN 1
60
61
62#define VPE_FMT_TYPE_CAPTURE (1 << 0)
63#define VPE_FMT_TYPE_OUTPUT (1 << 1)
64
65
66#define VPE_MAX_PLANES 2
67#define VPE_LUMA 0
68#define VPE_CHROMA 1
69
70
71#define VPE_MAX_SRC_BUFS 3
72
73#define VPE_DEF_BUFS_PER_JOB 1
74
75
76
77
78
79#define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
80 13 * VPDMA_CFD_CTD_DESC_SIZE)
81
82#define vpe_dbg(vpedev, fmt, arg...) \
83 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
84#define vpe_err(vpedev, fmt, arg...) \
85 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
86
87struct vpe_us_coeffs {
88 unsigned short anchor_fid0_c0;
89 unsigned short anchor_fid0_c1;
90 unsigned short anchor_fid0_c2;
91 unsigned short anchor_fid0_c3;
92 unsigned short interp_fid0_c0;
93 unsigned short interp_fid0_c1;
94 unsigned short interp_fid0_c2;
95 unsigned short interp_fid0_c3;
96 unsigned short anchor_fid1_c0;
97 unsigned short anchor_fid1_c1;
98 unsigned short anchor_fid1_c2;
99 unsigned short anchor_fid1_c3;
100 unsigned short interp_fid1_c0;
101 unsigned short interp_fid1_c1;
102 unsigned short interp_fid1_c2;
103 unsigned short interp_fid1_c3;
104};
105
106
107
108
109static const struct vpe_us_coeffs us_coeffs[] = {
110 {
111
112 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
113 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
114 },
115 {
116
117 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
118
119 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
120 },
121};
122
123
124
125
126
127
128struct vpe_dei_regs {
129 unsigned long mdt_spacial_freq_thr_reg;
130 unsigned long edi_config_reg;
131 unsigned long edi_lut_reg0;
132 unsigned long edi_lut_reg1;
133 unsigned long edi_lut_reg2;
134 unsigned long edi_lut_reg3;
135};
136
137
138
139
140static const struct vpe_dei_regs dei_regs = {
141 .mdt_spacial_freq_thr_reg = 0x020C0804u,
142 .edi_config_reg = 0x0118100Cu,
143 .edi_lut_reg0 = 0x08040200u,
144 .edi_lut_reg1 = 0x1010100Cu,
145 .edi_lut_reg2 = 0x10101010u,
146 .edi_lut_reg3 = 0x10101010u,
147};
148
149
150
151
152struct vpe_port_data {
153 enum vpdma_channel channel;
154 u8 vb_index;
155 u8 vb_part;
156};
157
158
159
160
161#define VPE_PORT_LUMA1_IN 0
162#define VPE_PORT_CHROMA1_IN 1
163#define VPE_PORT_LUMA2_IN 2
164#define VPE_PORT_CHROMA2_IN 3
165#define VPE_PORT_LUMA3_IN 4
166#define VPE_PORT_CHROMA3_IN 5
167#define VPE_PORT_MV_IN 6
168#define VPE_PORT_MV_OUT 7
169#define VPE_PORT_LUMA_OUT 8
170#define VPE_PORT_CHROMA_OUT 9
171#define VPE_PORT_RGB_OUT 10
172
173static const struct vpe_port_data port_data[11] = {
174 [VPE_PORT_LUMA1_IN] = {
175 .channel = VPE_CHAN_LUMA1_IN,
176 .vb_index = 0,
177 .vb_part = VPE_LUMA,
178 },
179 [VPE_PORT_CHROMA1_IN] = {
180 .channel = VPE_CHAN_CHROMA1_IN,
181 .vb_index = 0,
182 .vb_part = VPE_CHROMA,
183 },
184 [VPE_PORT_LUMA2_IN] = {
185 .channel = VPE_CHAN_LUMA2_IN,
186 .vb_index = 1,
187 .vb_part = VPE_LUMA,
188 },
189 [VPE_PORT_CHROMA2_IN] = {
190 .channel = VPE_CHAN_CHROMA2_IN,
191 .vb_index = 1,
192 .vb_part = VPE_CHROMA,
193 },
194 [VPE_PORT_LUMA3_IN] = {
195 .channel = VPE_CHAN_LUMA3_IN,
196 .vb_index = 2,
197 .vb_part = VPE_LUMA,
198 },
199 [VPE_PORT_CHROMA3_IN] = {
200 .channel = VPE_CHAN_CHROMA3_IN,
201 .vb_index = 2,
202 .vb_part = VPE_CHROMA,
203 },
204 [VPE_PORT_MV_IN] = {
205 .channel = VPE_CHAN_MV_IN,
206 },
207 [VPE_PORT_MV_OUT] = {
208 .channel = VPE_CHAN_MV_OUT,
209 },
210 [VPE_PORT_LUMA_OUT] = {
211 .channel = VPE_CHAN_LUMA_OUT,
212 .vb_part = VPE_LUMA,
213 },
214 [VPE_PORT_CHROMA_OUT] = {
215 .channel = VPE_CHAN_CHROMA_OUT,
216 .vb_part = VPE_CHROMA,
217 },
218 [VPE_PORT_RGB_OUT] = {
219 .channel = VPE_CHAN_RGB_OUT,
220 .vb_part = VPE_LUMA,
221 },
222};
223
224
225
226struct vpe_fmt {
227 char *name;
228 u32 fourcc;
229 u8 types;
230 u8 coplanar;
231
232 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
233};
234
235static struct vpe_fmt vpe_formats[] = {
236 {
237 .name = "NV16 YUV 422 co-planar",
238 .fourcc = V4L2_PIX_FMT_NV16,
239 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
240 .coplanar = 1,
241 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
242 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
243 },
244 },
245 {
246 .name = "NV12 YUV 420 co-planar",
247 .fourcc = V4L2_PIX_FMT_NV12,
248 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
249 .coplanar = 1,
250 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
251 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
252 },
253 },
254 {
255 .name = "YUYV 422 packed",
256 .fourcc = V4L2_PIX_FMT_YUYV,
257 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
258 .coplanar = 0,
259 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
260 },
261 },
262 {
263 .name = "UYVY 422 packed",
264 .fourcc = V4L2_PIX_FMT_UYVY,
265 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
266 .coplanar = 0,
267 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
268 },
269 },
270 {
271 .name = "RGB888 packed",
272 .fourcc = V4L2_PIX_FMT_RGB24,
273 .types = VPE_FMT_TYPE_CAPTURE,
274 .coplanar = 0,
275 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
276 },
277 },
278 {
279 .name = "ARGB32",
280 .fourcc = V4L2_PIX_FMT_RGB32,
281 .types = VPE_FMT_TYPE_CAPTURE,
282 .coplanar = 0,
283 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
284 },
285 },
286 {
287 .name = "BGR888 packed",
288 .fourcc = V4L2_PIX_FMT_BGR24,
289 .types = VPE_FMT_TYPE_CAPTURE,
290 .coplanar = 0,
291 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
292 },
293 },
294 {
295 .name = "ABGR32",
296 .fourcc = V4L2_PIX_FMT_BGR32,
297 .types = VPE_FMT_TYPE_CAPTURE,
298 .coplanar = 0,
299 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
300 },
301 },
302 {
303 .name = "RGB565",
304 .fourcc = V4L2_PIX_FMT_RGB565,
305 .types = VPE_FMT_TYPE_CAPTURE,
306 .coplanar = 0,
307 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
308 },
309 },
310 {
311 .name = "RGB5551",
312 .fourcc = V4L2_PIX_FMT_RGB555,
313 .types = VPE_FMT_TYPE_CAPTURE,
314 .coplanar = 0,
315 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
316 },
317 },
318};
319
320
321
322
323
324struct vpe_q_data {
325 unsigned int width;
326 unsigned int height;
327 unsigned int nplanes;
328 unsigned int bytesperline[VPE_MAX_PLANES];
329 enum v4l2_colorspace colorspace;
330 enum v4l2_field field;
331 unsigned int flags;
332 unsigned int sizeimage[VPE_MAX_PLANES];
333 struct v4l2_rect c_rect;
334 struct vpe_fmt *fmt;
335};
336
337
338#define Q_DATA_FRAME_1D BIT(0)
339#define Q_DATA_MODE_TILED BIT(1)
340#define Q_DATA_INTERLACED_ALTERNATE BIT(2)
341#define Q_DATA_INTERLACED_SEQ_TB BIT(3)
342
343#define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \
344 Q_DATA_INTERLACED_SEQ_TB)
345
346enum {
347 Q_DATA_SRC = 0,
348 Q_DATA_DST = 1,
349};
350
351
352static struct vpe_fmt *find_format(struct v4l2_format *f)
353{
354 struct vpe_fmt *fmt;
355 unsigned int k;
356
357 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
358 fmt = &vpe_formats[k];
359 if (fmt->fourcc == f->fmt.pix.pixelformat)
360 return fmt;
361 }
362
363 return NULL;
364}
365
366
367
368
369
370struct vpe_dev {
371 struct v4l2_device v4l2_dev;
372 struct video_device vfd;
373 struct v4l2_m2m_dev *m2m_dev;
374
375 atomic_t num_instances;
376 dma_addr_t loaded_mmrs;
377 struct mutex dev_mutex;
378 spinlock_t lock;
379
380 int irq;
381 void __iomem *base;
382 struct resource *res;
383
384 struct vpdma_data vpdma_data;
385 struct vpdma_data *vpdma;
386 struct sc_data *sc;
387 struct csc_data *csc;
388};
389
390
391
392
393struct vpe_ctx {
394 struct v4l2_fh fh;
395 struct vpe_dev *dev;
396 struct v4l2_ctrl_handler hdl;
397
398 unsigned int field;
399 unsigned int sequence;
400 unsigned int aborting;
401
402 unsigned int bufs_per_job;
403 unsigned int bufs_completed;
404
405 struct vpe_q_data q_data[2];
406 struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
407 struct vb2_v4l2_buffer *dst_vb;
408
409 dma_addr_t mv_buf_dma[2];
410 void *mv_buf[2];
411 size_t mv_buf_size;
412 struct vpdma_buf mmr_adb;
413 struct vpdma_buf sc_coeff_h;
414 struct vpdma_buf sc_coeff_v;
415 struct vpdma_desc_list desc_list;
416
417 bool deinterlacing;
418 bool load_mmrs;
419
420 unsigned int src_mv_buf_selector;
421};
422
423
424
425
426
427
428static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
429 enum v4l2_buf_type type)
430{
431 switch (type) {
432 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
433 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
434 return &ctx->q_data[Q_DATA_SRC];
435 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
436 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
437 return &ctx->q_data[Q_DATA_DST];
438 default:
439 return NULL;
440 }
441 return NULL;
442}
443
444static u32 read_reg(struct vpe_dev *dev, int offset)
445{
446 return ioread32(dev->base + offset);
447}
448
449static void write_reg(struct vpe_dev *dev, int offset, u32 value)
450{
451 iowrite32(value, dev->base + offset);
452}
453
454
455static int get_field(u32 value, u32 mask, int shift)
456{
457 return (value & (mask << shift)) >> shift;
458}
459
460static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
461{
462 return get_field(read_reg(dev, offset), mask, shift);
463}
464
465static void write_field(u32 *valp, u32 field, u32 mask, int shift)
466{
467 u32 val = *valp;
468
469 val &= ~(mask << shift);
470 val |= (field & mask) << shift;
471 *valp = val;
472}
473
474static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
475 u32 mask, int shift)
476{
477 u32 val = read_reg(dev, offset);
478
479 write_field(&val, field, mask, shift);
480
481 write_reg(dev, offset, val);
482}
483
484
485
486
487struct vpe_mmr_adb {
488 struct vpdma_adb_hdr out_fmt_hdr;
489 u32 out_fmt_reg[1];
490 u32 out_fmt_pad[3];
491 struct vpdma_adb_hdr us1_hdr;
492 u32 us1_regs[8];
493 struct vpdma_adb_hdr us2_hdr;
494 u32 us2_regs[8];
495 struct vpdma_adb_hdr us3_hdr;
496 u32 us3_regs[8];
497 struct vpdma_adb_hdr dei_hdr;
498 u32 dei_regs[8];
499 struct vpdma_adb_hdr sc_hdr0;
500 u32 sc_regs0[7];
501 u32 sc_pad0[1];
502 struct vpdma_adb_hdr sc_hdr8;
503 u32 sc_regs8[6];
504 u32 sc_pad8[2];
505 struct vpdma_adb_hdr sc_hdr17;
506 u32 sc_regs17[9];
507 u32 sc_pad17[3];
508 struct vpdma_adb_hdr csc_hdr;
509 u32 csc_regs[6];
510 u32 csc_pad[2];
511};
512
513#define GET_OFFSET_TOP(ctx, obj, reg) \
514 ((obj)->res->start - ctx->dev->res->start + reg)
515
516#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
517 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
518
519
520
521static void init_adb_hdrs(struct vpe_ctx *ctx)
522{
523 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
524 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
525 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
526 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
527 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
528 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
529 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
530 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
531 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
532 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
533 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
534 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
535 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
536};
537
538
539
540
541
542
543
544
545static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
546{
547 struct device *dev = ctx->dev->v4l2_dev.dev;
548
549 if (ctx->mv_buf_size == size)
550 return 0;
551
552 if (ctx->mv_buf[0])
553 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
554 ctx->mv_buf_dma[0]);
555
556 if (ctx->mv_buf[1])
557 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
558 ctx->mv_buf_dma[1]);
559
560 if (size == 0)
561 return 0;
562
563 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
564 GFP_KERNEL);
565 if (!ctx->mv_buf[0]) {
566 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
567 return -ENOMEM;
568 }
569
570 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
571 GFP_KERNEL);
572 if (!ctx->mv_buf[1]) {
573 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
574 dma_free_coherent(dev, size, ctx->mv_buf[0],
575 ctx->mv_buf_dma[0]);
576
577 return -ENOMEM;
578 }
579
580 ctx->mv_buf_size = size;
581 ctx->src_mv_buf_selector = 0;
582
583 return 0;
584}
585
586static void free_mv_buffers(struct vpe_ctx *ctx)
587{
588 realloc_mv_buffers(ctx, 0);
589}
590
591
592
593
594
595
596static void free_vbs(struct vpe_ctx *ctx)
597{
598 struct vpe_dev *dev = ctx->dev;
599 unsigned long flags;
600
601 if (ctx->src_vbs[2] == NULL)
602 return;
603
604 spin_lock_irqsave(&dev->lock, flags);
605 if (ctx->src_vbs[2]) {
606 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
607 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
608 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
609 ctx->src_vbs[2] = NULL;
610 ctx->src_vbs[1] = NULL;
611 }
612 spin_unlock_irqrestore(&dev->lock, flags);
613}
614
615
616
617
618static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
619{
620 u32 val = 0;
621
622 if (on)
623 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
624 write_reg(dev, VPE_CLK_ENABLE, val);
625}
626
627static void vpe_top_reset(struct vpe_dev *dev)
628{
629
630 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
631 VPE_DATA_PATH_CLK_RESET_SHIFT);
632
633 usleep_range(100, 150);
634
635 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
636 VPE_DATA_PATH_CLK_RESET_SHIFT);
637}
638
639static void vpe_top_vpdma_reset(struct vpe_dev *dev)
640{
641 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
642 VPE_VPDMA_CLK_RESET_SHIFT);
643
644 usleep_range(100, 150);
645
646 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
647 VPE_VPDMA_CLK_RESET_SHIFT);
648}
649
650
651
652
653static void set_us_coefficients(struct vpe_ctx *ctx)
654{
655 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
656 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
657 u32 *us1_reg = &mmr_adb->us1_regs[0];
658 u32 *us2_reg = &mmr_adb->us2_regs[0];
659 u32 *us3_reg = &mmr_adb->us3_regs[0];
660 const unsigned short *cp, *end_cp;
661
662 cp = &us_coeffs[0].anchor_fid0_c0;
663
664 if (s_q_data->flags & Q_IS_INTERLACED)
665 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
666
667 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
668
669 while (cp < end_cp) {
670 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
671 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
672 *us2_reg++ = *us1_reg;
673 *us3_reg++ = *us1_reg++;
674 }
675 ctx->load_mmrs = true;
676}
677
678
679
680
681static void set_cfg_modes(struct vpe_ctx *ctx)
682{
683 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
684 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
685 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
686 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
687 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
688 int cfg_mode = 1;
689
690
691
692
693
694
695 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
696 cfg_mode = 0;
697
698 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
699 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
700 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
701
702 ctx->load_mmrs = true;
703}
704
705static void set_line_modes(struct vpe_ctx *ctx)
706{
707 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
708 int line_mode = 1;
709
710 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
711 line_mode = 0;
712
713
714 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
715 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
716 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
717
718
719 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
720 VPE_CHAN_LUMA1_IN);
721 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
722 VPE_CHAN_LUMA2_IN);
723 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
724 VPE_CHAN_LUMA3_IN);
725
726
727 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
728 VPE_CHAN_CHROMA1_IN);
729 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
730 VPE_CHAN_CHROMA2_IN);
731 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
732 VPE_CHAN_CHROMA3_IN);
733
734
735 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
736 VPE_CHAN_MV_IN);
737}
738
739
740
741
742
743static void set_src_registers(struct vpe_ctx *ctx)
744{
745 set_us_coefficients(ctx);
746}
747
748
749
750
751
752static void set_dst_registers(struct vpe_ctx *ctx)
753{
754 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
755 enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
756 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
757 u32 val = 0;
758
759 if (clrspc == V4L2_COLORSPACE_SRGB) {
760 val |= VPE_RGB_OUT_SELECT;
761 vpdma_set_bg_color(ctx->dev->vpdma,
762 (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
763 } else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
764 val |= VPE_COLOR_SEPARATE_422;
765
766
767
768
769
770 val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
771
772 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
773 val |= VPE_DS_BYPASS;
774
775 mmr_adb->out_fmt_reg[0] = val;
776
777 ctx->load_mmrs = true;
778}
779
780
781
782
783static void set_dei_regs(struct vpe_ctx *ctx)
784{
785 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
786 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
787 unsigned int src_h = s_q_data->c_rect.height;
788 unsigned int src_w = s_q_data->c_rect.width;
789 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
790 bool deinterlace = true;
791 u32 val = 0;
792
793
794
795
796
797
798
799 if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
800 deinterlace = false;
801 val = VPE_DEI_INTERLACE_BYPASS;
802 }
803
804 src_h = deinterlace ? src_h * 2 : src_h;
805
806 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
807 (src_w << VPE_DEI_WIDTH_SHIFT) |
808 VPE_DEI_FIELD_FLUSH;
809
810 *dei_mmr0 = val;
811
812 ctx->load_mmrs = true;
813}
814
815static void set_dei_shadow_registers(struct vpe_ctx *ctx)
816{
817 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
818 u32 *dei_mmr = &mmr_adb->dei_regs[0];
819 const struct vpe_dei_regs *cur = &dei_regs;
820
821 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
822 dei_mmr[3] = cur->edi_config_reg;
823 dei_mmr[4] = cur->edi_lut_reg0;
824 dei_mmr[5] = cur->edi_lut_reg1;
825 dei_mmr[6] = cur->edi_lut_reg2;
826 dei_mmr[7] = cur->edi_lut_reg3;
827
828 ctx->load_mmrs = true;
829}
830
831static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
832{
833 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
834 u32 *edi_config_reg = &mmr_adb->dei_regs[3];
835
836 if (mode & 0x2)
837 write_field(edi_config_reg, 1, 1, 2);
838
839 if (mode & 0x3)
840 write_field(edi_config_reg, 1, 1, 3);
841
842 write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
843 VPE_EDI_INP_MODE_SHIFT);
844
845 ctx->load_mmrs = true;
846}
847
848
849
850
851
852static int set_srcdst_params(struct vpe_ctx *ctx)
853{
854 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
855 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
856 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
857 unsigned int src_w = s_q_data->c_rect.width;
858 unsigned int src_h = s_q_data->c_rect.height;
859 unsigned int dst_w = d_q_data->c_rect.width;
860 unsigned int dst_h = d_q_data->c_rect.height;
861 size_t mv_buf_size;
862 int ret;
863
864 ctx->sequence = 0;
865 ctx->field = V4L2_FIELD_TOP;
866
867 if ((s_q_data->flags & Q_IS_INTERLACED) &&
868 !(d_q_data->flags & Q_IS_INTERLACED)) {
869 int bytes_per_line;
870 const struct vpdma_data_format *mv =
871 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
872
873
874
875
876
877
878
879
880 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
881 VPDMA_STRIDE_ALIGN);
882 mv_buf_size = bytes_per_line * s_q_data->height;
883
884 ctx->deinterlacing = true;
885 src_h <<= 1;
886 } else {
887 ctx->deinterlacing = false;
888 mv_buf_size = 0;
889 }
890
891 free_vbs(ctx);
892 ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
893
894 ret = realloc_mv_buffers(ctx, mv_buf_size);
895 if (ret)
896 return ret;
897
898 set_cfg_modes(ctx);
899 set_dei_regs(ctx);
900
901 csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
902 s_q_data->colorspace, d_q_data->colorspace);
903
904 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
905 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
906
907 sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
908 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
909 src_w, src_h, dst_w, dst_h);
910
911 return 0;
912}
913
914
915
916
917static struct vpe_ctx *file2ctx(struct file *file)
918{
919 return container_of(file->private_data, struct vpe_ctx, fh);
920}
921
922
923
924
925
926
927
928
929static int job_ready(void *priv)
930{
931 struct vpe_ctx *ctx = priv;
932
933
934
935
936
937
938 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
939 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
940 return 0;
941
942 return 1;
943}
944
945static void job_abort(void *priv)
946{
947 struct vpe_ctx *ctx = priv;
948
949
950 ctx->aborting = 1;
951}
952
953static void vpe_dump_regs(struct vpe_dev *dev)
954{
955#define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
956
957 vpe_dbg(dev, "VPE Registers:\n");
958
959 DUMPREG(PID);
960 DUMPREG(SYSCONFIG);
961 DUMPREG(INT0_STATUS0_RAW);
962 DUMPREG(INT0_STATUS0);
963 DUMPREG(INT0_ENABLE0);
964 DUMPREG(INT0_STATUS1_RAW);
965 DUMPREG(INT0_STATUS1);
966 DUMPREG(INT0_ENABLE1);
967 DUMPREG(CLK_ENABLE);
968 DUMPREG(CLK_RESET);
969 DUMPREG(CLK_FORMAT_SELECT);
970 DUMPREG(CLK_RANGE_MAP);
971 DUMPREG(US1_R0);
972 DUMPREG(US1_R1);
973 DUMPREG(US1_R2);
974 DUMPREG(US1_R3);
975 DUMPREG(US1_R4);
976 DUMPREG(US1_R5);
977 DUMPREG(US1_R6);
978 DUMPREG(US1_R7);
979 DUMPREG(US2_R0);
980 DUMPREG(US2_R1);
981 DUMPREG(US2_R2);
982 DUMPREG(US2_R3);
983 DUMPREG(US2_R4);
984 DUMPREG(US2_R5);
985 DUMPREG(US2_R6);
986 DUMPREG(US2_R7);
987 DUMPREG(US3_R0);
988 DUMPREG(US3_R1);
989 DUMPREG(US3_R2);
990 DUMPREG(US3_R3);
991 DUMPREG(US3_R4);
992 DUMPREG(US3_R5);
993 DUMPREG(US3_R6);
994 DUMPREG(US3_R7);
995 DUMPREG(DEI_FRAME_SIZE);
996 DUMPREG(MDT_BYPASS);
997 DUMPREG(MDT_SF_THRESHOLD);
998 DUMPREG(EDI_CONFIG);
999 DUMPREG(DEI_EDI_LUT_R0);
1000 DUMPREG(DEI_EDI_LUT_R1);
1001 DUMPREG(DEI_EDI_LUT_R2);
1002 DUMPREG(DEI_EDI_LUT_R3);
1003 DUMPREG(DEI_FMD_WINDOW_R0);
1004 DUMPREG(DEI_FMD_WINDOW_R1);
1005 DUMPREG(DEI_FMD_CONTROL_R0);
1006 DUMPREG(DEI_FMD_CONTROL_R1);
1007 DUMPREG(DEI_FMD_STATUS_R0);
1008 DUMPREG(DEI_FMD_STATUS_R1);
1009 DUMPREG(DEI_FMD_STATUS_R2);
1010#undef DUMPREG
1011
1012 sc_dump_regs(dev->sc);
1013 csc_dump_regs(dev->csc);
1014}
1015
1016static void add_out_dtd(struct vpe_ctx *ctx, int port)
1017{
1018 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1019 const struct vpe_port_data *p_data = &port_data[port];
1020 struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1021 struct vpe_fmt *fmt = q_data->fmt;
1022 const struct vpdma_data_format *vpdma_fmt;
1023 int mv_buf_selector = !ctx->src_mv_buf_selector;
1024 dma_addr_t dma_addr;
1025 u32 flags = 0;
1026 u32 offset = 0;
1027
1028 if (port == VPE_PORT_MV_OUT) {
1029 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1030 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1031 q_data = &ctx->q_data[Q_DATA_SRC];
1032 } else {
1033
1034 int plane = fmt->coplanar ? p_data->vb_part : 0;
1035
1036 vpdma_fmt = fmt->vpdma_fmt[plane];
1037
1038
1039
1040
1041 if (q_data->nplanes == 1 && plane) {
1042 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1043
1044 offset = q_data->bytesperline[0] * q_data->height;
1045 } else {
1046 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1047
1048 offset = 0;
1049 }
1050 if (!dma_addr) {
1051 vpe_err(ctx->dev,
1052 "acquiring output buffer(%d) dma_addr failed\n",
1053 port);
1054 return;
1055 }
1056
1057 dma_addr += offset;
1058 }
1059
1060 if (q_data->flags & Q_DATA_FRAME_1D)
1061 flags |= VPDMA_DATA_FRAME_1D;
1062 if (q_data->flags & Q_DATA_MODE_TILED)
1063 flags |= VPDMA_DATA_MODE_TILED;
1064
1065 vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1066 MAX_W, MAX_H);
1067
1068 vpdma_add_out_dtd(&ctx->desc_list, q_data->width,
1069 q_data->bytesperline[VPE_LUMA], &q_data->c_rect,
1070 vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1071 MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1072}
1073
1074static void add_in_dtd(struct vpe_ctx *ctx, int port)
1075{
1076 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1077 const struct vpe_port_data *p_data = &port_data[port];
1078 struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1079 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1080 struct vpe_fmt *fmt = q_data->fmt;
1081 const struct vpdma_data_format *vpdma_fmt;
1082 int mv_buf_selector = ctx->src_mv_buf_selector;
1083 int field = vbuf->field == V4L2_FIELD_BOTTOM;
1084 int frame_width, frame_height;
1085 dma_addr_t dma_addr;
1086 u32 flags = 0;
1087 u32 offset = 0;
1088
1089 if (port == VPE_PORT_MV_IN) {
1090 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1091 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1092 } else {
1093
1094 int plane = fmt->coplanar ? p_data->vb_part : 0;
1095
1096 vpdma_fmt = fmt->vpdma_fmt[plane];
1097
1098
1099
1100
1101 if (q_data->nplanes == 1 && plane) {
1102 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1103
1104 offset = q_data->bytesperline[0] * q_data->height;
1105 } else {
1106 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1107
1108 offset = 0;
1109 }
1110 if (!dma_addr) {
1111 vpe_err(ctx->dev,
1112 "acquiring output buffer(%d) dma_addr failed\n",
1113 port);
1114 return;
1115 }
1116
1117 dma_addr += offset;
1118
1119 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) {
1120
1121
1122
1123
1124
1125 field = (p_data->vb_index + (ctx->sequence % 2)) % 2;
1126
1127 if (field) {
1128
1129
1130
1131
1132 int height = q_data->height / 2;
1133 int bpp = fmt->fourcc == V4L2_PIX_FMT_NV12 ?
1134 1 : (vpdma_fmt->depth >> 3);
1135 if (plane)
1136 height /= 2;
1137 dma_addr += q_data->width * height * bpp;
1138 }
1139 }
1140 }
1141
1142 if (q_data->flags & Q_DATA_FRAME_1D)
1143 flags |= VPDMA_DATA_FRAME_1D;
1144 if (q_data->flags & Q_DATA_MODE_TILED)
1145 flags |= VPDMA_DATA_MODE_TILED;
1146
1147 frame_width = q_data->c_rect.width;
1148 frame_height = q_data->c_rect.height;
1149
1150 if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1151 frame_height /= 2;
1152
1153 vpdma_add_in_dtd(&ctx->desc_list, q_data->width,
1154 q_data->bytesperline[VPE_LUMA], &q_data->c_rect,
1155 vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width,
1156 frame_height, 0, 0);
1157}
1158
1159
1160
1161
1162static void enable_irqs(struct vpe_ctx *ctx)
1163{
1164 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1165 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1166 VPE_DS1_UV_ERROR_INT);
1167
1168 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1169}
1170
1171static void disable_irqs(struct vpe_ctx *ctx)
1172{
1173 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1174 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1175
1176 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1177}
1178
1179
1180
1181
1182
1183
1184static void device_run(void *priv)
1185{
1186 struct vpe_ctx *ctx = priv;
1187 struct sc_data *sc = ctx->dev->sc;
1188 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1189 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1190
1191 if (ctx->deinterlacing && s_q_data->flags & Q_DATA_INTERLACED_SEQ_TB &&
1192 ctx->sequence % 2 == 0) {
1193
1194
1195
1196
1197
1198 ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1199 WARN_ON(ctx->src_vbs[0] == NULL);
1200 } else {
1201 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1202 WARN_ON(ctx->src_vbs[0] == NULL);
1203 }
1204
1205 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1206 WARN_ON(ctx->dst_vb == NULL);
1207
1208 if (ctx->deinterlacing) {
1209
1210 if (ctx->src_vbs[2] == NULL) {
1211 ctx->src_vbs[2] = ctx->src_vbs[0];
1212 WARN_ON(ctx->src_vbs[2] == NULL);
1213 ctx->src_vbs[1] = ctx->src_vbs[0];
1214 WARN_ON(ctx->src_vbs[1] == NULL);
1215 }
1216
1217
1218
1219
1220
1221 if (ctx->sequence == 2)
1222 config_edi_input_mode(ctx, 0x3);
1223 }
1224
1225
1226 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1227 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1228 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1229
1230 set_line_modes(ctx);
1231
1232 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1233 ctx->load_mmrs = false;
1234 }
1235
1236 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1237 sc->load_coeff_h) {
1238 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1239 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1240 &ctx->sc_coeff_h, 0);
1241
1242 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1243 sc->load_coeff_h = false;
1244 }
1245
1246 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1247 sc->load_coeff_v) {
1248 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1249 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1250 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1251
1252 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1253 sc->load_coeff_v = false;
1254 }
1255
1256
1257 if (ctx->deinterlacing)
1258 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1259
1260 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1261 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1262 } else {
1263 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1264 if (d_q_data->fmt->coplanar)
1265 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1266 }
1267
1268
1269 if (ctx->deinterlacing) {
1270 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1271 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1272
1273 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1274 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1275 }
1276
1277 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1278 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1279
1280 if (ctx->deinterlacing)
1281 add_in_dtd(ctx, VPE_PORT_MV_IN);
1282
1283
1284 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1285 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1286
1287 if (ctx->deinterlacing) {
1288 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1289 VPE_CHAN_LUMA2_IN);
1290 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1291 VPE_CHAN_CHROMA2_IN);
1292
1293 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1294 VPE_CHAN_LUMA3_IN);
1295 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1296 VPE_CHAN_CHROMA3_IN);
1297
1298 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1299 }
1300
1301
1302 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1303 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1304 VPE_CHAN_RGB_OUT);
1305 } else {
1306 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1307 VPE_CHAN_LUMA_OUT);
1308 if (d_q_data->fmt->coplanar)
1309 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1310 VPE_CHAN_CHROMA_OUT);
1311 }
1312
1313 if (ctx->deinterlacing)
1314 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1315
1316 enable_irqs(ctx);
1317
1318 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1319 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1320}
1321
1322static void dei_error(struct vpe_ctx *ctx)
1323{
1324 dev_warn(ctx->dev->v4l2_dev.dev,
1325 "received DEI error interrupt\n");
1326}
1327
1328static void ds1_uv_error(struct vpe_ctx *ctx)
1329{
1330 dev_warn(ctx->dev->v4l2_dev.dev,
1331 "received downsampler error interrupt\n");
1332}
1333
1334static irqreturn_t vpe_irq(int irq_vpe, void *data)
1335{
1336 struct vpe_dev *dev = (struct vpe_dev *)data;
1337 struct vpe_ctx *ctx;
1338 struct vpe_q_data *d_q_data;
1339 struct vb2_v4l2_buffer *s_vb, *d_vb;
1340 unsigned long flags;
1341 u32 irqst0, irqst1;
1342 bool list_complete = false;
1343
1344 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1345 if (irqst0) {
1346 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1347 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1348 }
1349
1350 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1351 if (irqst1) {
1352 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1353 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1354 }
1355
1356 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1357 if (!ctx) {
1358 vpe_err(dev, "instance released before end of transaction\n");
1359 goto handled;
1360 }
1361
1362 if (irqst1) {
1363 if (irqst1 & VPE_DEI_ERROR_INT) {
1364 irqst1 &= ~VPE_DEI_ERROR_INT;
1365 dei_error(ctx);
1366 }
1367 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1368 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1369 ds1_uv_error(ctx);
1370 }
1371 }
1372
1373 if (irqst0) {
1374 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1375 vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1376
1377 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1378 list_complete = true;
1379 }
1380
1381 if (irqst0 | irqst1) {
1382 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1383 irqst0, irqst1);
1384 }
1385
1386
1387
1388
1389
1390 if (!list_complete)
1391 goto handled;
1392
1393 disable_irqs(ctx);
1394
1395 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1396 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1397 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1398 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1399
1400 vpdma_reset_desc_list(&ctx->desc_list);
1401
1402
1403 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1404
1405 if (ctx->aborting)
1406 goto finished;
1407
1408 s_vb = ctx->src_vbs[0];
1409 d_vb = ctx->dst_vb;
1410
1411 d_vb->flags = s_vb->flags;
1412 d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1413
1414 if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1415 d_vb->timecode = s_vb->timecode;
1416
1417 d_vb->sequence = ctx->sequence;
1418
1419 d_q_data = &ctx->q_data[Q_DATA_DST];
1420 if (d_q_data->flags & Q_IS_INTERLACED) {
1421 d_vb->field = ctx->field;
1422 if (ctx->field == V4L2_FIELD_BOTTOM) {
1423 ctx->sequence++;
1424 ctx->field = V4L2_FIELD_TOP;
1425 } else {
1426 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1427 ctx->field = V4L2_FIELD_BOTTOM;
1428 }
1429 } else {
1430 d_vb->field = V4L2_FIELD_NONE;
1431 ctx->sequence++;
1432 }
1433
1434 if (ctx->deinterlacing) {
1435
1436
1437
1438
1439
1440
1441
1442
1443 if (ctx->src_vbs[2] != ctx->src_vbs[1])
1444 s_vb = ctx->src_vbs[2];
1445 else
1446 s_vb = NULL;
1447 }
1448
1449 spin_lock_irqsave(&dev->lock, flags);
1450
1451 if (s_vb)
1452 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1453
1454 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1455
1456 spin_unlock_irqrestore(&dev->lock, flags);
1457
1458 if (ctx->deinterlacing) {
1459 ctx->src_vbs[2] = ctx->src_vbs[1];
1460 ctx->src_vbs[1] = ctx->src_vbs[0];
1461 }
1462
1463
1464
1465
1466
1467
1468 ctx->src_vbs[0] = NULL;
1469 ctx->dst_vb = NULL;
1470
1471 ctx->bufs_completed++;
1472 if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1473 device_run(ctx);
1474 goto handled;
1475 }
1476
1477finished:
1478 vpe_dbg(ctx->dev, "finishing transaction\n");
1479 ctx->bufs_completed = 0;
1480 v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1481handled:
1482 return IRQ_HANDLED;
1483}
1484
1485
1486
1487
1488static int vpe_querycap(struct file *file, void *priv,
1489 struct v4l2_capability *cap)
1490{
1491 strscpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver));
1492 strscpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card));
1493 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1494 VPE_MODULE_NAME);
1495 return 0;
1496}
1497
1498static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1499{
1500 int i, index;
1501 struct vpe_fmt *fmt = NULL;
1502
1503 index = 0;
1504 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1505 if (vpe_formats[i].types & type) {
1506 if (index == f->index) {
1507 fmt = &vpe_formats[i];
1508 break;
1509 }
1510 index++;
1511 }
1512 }
1513
1514 if (!fmt)
1515 return -EINVAL;
1516
1517 strscpy(f->description, fmt->name, sizeof(f->description));
1518 f->pixelformat = fmt->fourcc;
1519 return 0;
1520}
1521
1522static int vpe_enum_fmt(struct file *file, void *priv,
1523 struct v4l2_fmtdesc *f)
1524{
1525 if (V4L2_TYPE_IS_OUTPUT(f->type))
1526 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1527
1528 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1529}
1530
1531static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1532{
1533 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1534 struct vpe_ctx *ctx = file2ctx(file);
1535 struct vb2_queue *vq;
1536 struct vpe_q_data *q_data;
1537 int i;
1538
1539 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1540 if (!vq)
1541 return -EINVAL;
1542
1543 q_data = get_q_data(ctx, f->type);
1544
1545 pix->width = q_data->width;
1546 pix->height = q_data->height;
1547 pix->pixelformat = q_data->fmt->fourcc;
1548 pix->field = q_data->field;
1549
1550 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1551 pix->colorspace = q_data->colorspace;
1552 } else {
1553 struct vpe_q_data *s_q_data;
1554
1555
1556 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1557
1558 pix->colorspace = s_q_data->colorspace;
1559 }
1560
1561 pix->num_planes = q_data->nplanes;
1562
1563 for (i = 0; i < pix->num_planes; i++) {
1564 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1565 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1566 }
1567
1568 return 0;
1569}
1570
1571static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1572 struct vpe_fmt *fmt, int type)
1573{
1574 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1575 struct v4l2_plane_pix_format *plane_fmt;
1576 unsigned int w_align;
1577 int i, depth, depth_bytes, height;
1578 unsigned int stride = 0;
1579
1580 if (!fmt || !(fmt->types & type)) {
1581 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1582 pix->pixelformat);
1583 return -EINVAL;
1584 }
1585
1586 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE
1587 && pix->field != V4L2_FIELD_SEQ_TB)
1588 pix->field = V4L2_FIELD_NONE;
1589
1590 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1591
1592
1593
1594
1595
1596
1597 depth_bytes = depth >> 3;
1598
1599 if (depth_bytes == 3) {
1600
1601
1602
1603
1604 w_align = 4;
1605 } else {
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622 w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes);
1623 w_align = ilog2(w_align);
1624 }
1625
1626 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1627 &pix->height, MIN_H, MAX_H, H_ALIGN,
1628 S_ALIGN);
1629
1630 if (!pix->num_planes)
1631 pix->num_planes = fmt->coplanar ? 2 : 1;
1632 else if (pix->num_planes > 1 && !fmt->coplanar)
1633 pix->num_planes = 1;
1634
1635 pix->pixelformat = fmt->fourcc;
1636
1637
1638
1639
1640
1641 if (pix->field == V4L2_FIELD_SEQ_TB)
1642 height = pix->height / 2;
1643 else
1644 height = pix->height;
1645
1646 if (!pix->colorspace) {
1647 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1648 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1649 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1650 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1651 pix->colorspace = V4L2_COLORSPACE_SRGB;
1652 } else {
1653 if (height > 1280)
1654 pix->colorspace = V4L2_COLORSPACE_REC709;
1655 else
1656 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1657 }
1658 }
1659
1660 memset(pix->reserved, 0, sizeof(pix->reserved));
1661 for (i = 0; i < pix->num_planes; i++) {
1662 plane_fmt = &pix->plane_fmt[i];
1663 depth = fmt->vpdma_fmt[i]->depth;
1664
1665 stride = (pix->width * fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1666 if (stride > plane_fmt->bytesperline)
1667 plane_fmt->bytesperline = stride;
1668
1669 plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline,
1670 VPDMA_STRIDE_ALIGN);
1671
1672 if (i == VPE_LUMA) {
1673 plane_fmt->sizeimage = pix->height *
1674 plane_fmt->bytesperline;
1675
1676 if (pix->num_planes == 1 && fmt->coplanar)
1677 plane_fmt->sizeimage += pix->height *
1678 plane_fmt->bytesperline *
1679 fmt->vpdma_fmt[VPE_CHROMA]->depth >> 3;
1680
1681 } else {
1682 plane_fmt->sizeimage = (pix->height *
1683 plane_fmt->bytesperline *
1684 depth) >> 3;
1685 }
1686 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1687 }
1688
1689 return 0;
1690}
1691
1692static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1693{
1694 struct vpe_ctx *ctx = file2ctx(file);
1695 struct vpe_fmt *fmt = find_format(f);
1696
1697 if (V4L2_TYPE_IS_OUTPUT(f->type))
1698 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1699 else
1700 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1701}
1702
1703static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1704{
1705 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1706 struct v4l2_plane_pix_format *plane_fmt;
1707 struct vpe_q_data *q_data;
1708 struct vb2_queue *vq;
1709 int i;
1710
1711 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1712 if (!vq)
1713 return -EINVAL;
1714
1715 if (vb2_is_busy(vq)) {
1716 vpe_err(ctx->dev, "queue busy\n");
1717 return -EBUSY;
1718 }
1719
1720 q_data = get_q_data(ctx, f->type);
1721 if (!q_data)
1722 return -EINVAL;
1723
1724 q_data->fmt = find_format(f);
1725 q_data->width = pix->width;
1726 q_data->height = pix->height;
1727 q_data->colorspace = pix->colorspace;
1728 q_data->field = pix->field;
1729 q_data->nplanes = pix->num_planes;
1730
1731 for (i = 0; i < pix->num_planes; i++) {
1732 plane_fmt = &pix->plane_fmt[i];
1733
1734 q_data->bytesperline[i] = plane_fmt->bytesperline;
1735 q_data->sizeimage[i] = plane_fmt->sizeimage;
1736 }
1737
1738 q_data->c_rect.left = 0;
1739 q_data->c_rect.top = 0;
1740 q_data->c_rect.width = q_data->width;
1741 q_data->c_rect.height = q_data->height;
1742
1743 if (q_data->field == V4L2_FIELD_ALTERNATE)
1744 q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1745 else if (q_data->field == V4L2_FIELD_SEQ_TB)
1746 q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1747 else
1748 q_data->flags &= ~Q_IS_INTERLACED;
1749
1750
1751 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1752 q_data->c_rect.height /= 2;
1753
1754 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1755 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1756 q_data->bytesperline[VPE_LUMA]);
1757 if (q_data->nplanes == 2)
1758 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1759 q_data->bytesperline[VPE_CHROMA]);
1760
1761 return 0;
1762}
1763
1764static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1765{
1766 int ret;
1767 struct vpe_ctx *ctx = file2ctx(file);
1768
1769 ret = vpe_try_fmt(file, priv, f);
1770 if (ret)
1771 return ret;
1772
1773 ret = __vpe_s_fmt(ctx, f);
1774 if (ret)
1775 return ret;
1776
1777 if (V4L2_TYPE_IS_OUTPUT(f->type))
1778 set_src_registers(ctx);
1779 else
1780 set_dst_registers(ctx);
1781
1782 return set_srcdst_params(ctx);
1783}
1784
1785static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1786{
1787 struct vpe_q_data *q_data;
1788 int height;
1789
1790 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1791 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1792 return -EINVAL;
1793
1794 q_data = get_q_data(ctx, s->type);
1795 if (!q_data)
1796 return -EINVAL;
1797
1798 switch (s->target) {
1799 case V4L2_SEL_TGT_COMPOSE:
1800
1801
1802
1803
1804 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1805 return -EINVAL;
1806 break;
1807 case V4L2_SEL_TGT_CROP:
1808
1809
1810
1811
1812 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1813 return -EINVAL;
1814 break;
1815
1816
1817
1818
1819 default:
1820 return -EINVAL;
1821 }
1822
1823
1824
1825
1826
1827 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1828 height = q_data->height / 2;
1829 else
1830 height = q_data->height;
1831
1832 if (s->r.top < 0 || s->r.left < 0) {
1833 vpe_err(ctx->dev, "negative values for top and left\n");
1834 s->r.top = s->r.left = 0;
1835 }
1836
1837 v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1838 &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1839
1840
1841 if (s->r.left + s->r.width > q_data->width)
1842 s->r.left = q_data->width - s->r.width;
1843 if (s->r.top + s->r.height > q_data->height)
1844 s->r.top = q_data->height - s->r.height;
1845
1846 return 0;
1847}
1848
1849static int vpe_g_selection(struct file *file, void *fh,
1850 struct v4l2_selection *s)
1851{
1852 struct vpe_ctx *ctx = file2ctx(file);
1853 struct vpe_q_data *q_data;
1854 bool use_c_rect = false;
1855
1856 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1857 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1858 return -EINVAL;
1859
1860 q_data = get_q_data(ctx, s->type);
1861 if (!q_data)
1862 return -EINVAL;
1863
1864 switch (s->target) {
1865 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1866 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1867 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1868 return -EINVAL;
1869 break;
1870 case V4L2_SEL_TGT_CROP_BOUNDS:
1871 case V4L2_SEL_TGT_CROP_DEFAULT:
1872 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1873 return -EINVAL;
1874 break;
1875 case V4L2_SEL_TGT_COMPOSE:
1876 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1877 return -EINVAL;
1878 use_c_rect = true;
1879 break;
1880 case V4L2_SEL_TGT_CROP:
1881 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1882 return -EINVAL;
1883 use_c_rect = true;
1884 break;
1885 default:
1886 return -EINVAL;
1887 }
1888
1889 if (use_c_rect) {
1890
1891
1892
1893
1894 s->r = q_data->c_rect;
1895 } else {
1896
1897
1898
1899
1900 s->r.left = 0;
1901 s->r.top = 0;
1902 s->r.width = q_data->width;
1903 s->r.height = q_data->height;
1904 }
1905
1906 return 0;
1907}
1908
1909
1910static int vpe_s_selection(struct file *file, void *fh,
1911 struct v4l2_selection *s)
1912{
1913 struct vpe_ctx *ctx = file2ctx(file);
1914 struct vpe_q_data *q_data;
1915 struct v4l2_selection sel = *s;
1916 int ret;
1917
1918 ret = __vpe_try_selection(ctx, &sel);
1919 if (ret)
1920 return ret;
1921
1922 q_data = get_q_data(ctx, sel.type);
1923 if (!q_data)
1924 return -EINVAL;
1925
1926 if ((q_data->c_rect.left == sel.r.left) &&
1927 (q_data->c_rect.top == sel.r.top) &&
1928 (q_data->c_rect.width == sel.r.width) &&
1929 (q_data->c_rect.height == sel.r.height)) {
1930 vpe_dbg(ctx->dev,
1931 "requested crop/compose values are already set\n");
1932 return 0;
1933 }
1934
1935 q_data->c_rect = sel.r;
1936
1937 return set_srcdst_params(ctx);
1938}
1939
1940
1941
1942
1943
1944#define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1945
1946static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1947{
1948 struct vpe_ctx *ctx =
1949 container_of(ctrl->handler, struct vpe_ctx, hdl);
1950
1951 switch (ctrl->id) {
1952 case V4L2_CID_VPE_BUFS_PER_JOB:
1953 ctx->bufs_per_job = ctrl->val;
1954 break;
1955
1956 default:
1957 vpe_err(ctx->dev, "Invalid control\n");
1958 return -EINVAL;
1959 }
1960
1961 return 0;
1962}
1963
1964static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1965 .s_ctrl = vpe_s_ctrl,
1966};
1967
1968static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1969 .vidioc_querycap = vpe_querycap,
1970
1971 .vidioc_enum_fmt_vid_cap = vpe_enum_fmt,
1972 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1973 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1974 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1975
1976 .vidioc_enum_fmt_vid_out = vpe_enum_fmt,
1977 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1978 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1979 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1980
1981 .vidioc_g_selection = vpe_g_selection,
1982 .vidioc_s_selection = vpe_s_selection,
1983
1984 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1985 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1986 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1987 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1988 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1989 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1990 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1991
1992 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1993 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1994};
1995
1996
1997
1998
1999static int vpe_queue_setup(struct vb2_queue *vq,
2000 unsigned int *nbuffers, unsigned int *nplanes,
2001 unsigned int sizes[], struct device *alloc_devs[])
2002{
2003 int i;
2004 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
2005 struct vpe_q_data *q_data;
2006
2007 q_data = get_q_data(ctx, vq->type);
2008
2009 *nplanes = q_data->nplanes;
2010
2011 for (i = 0; i < *nplanes; i++)
2012 sizes[i] = q_data->sizeimage[i];
2013
2014 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
2015 sizes[VPE_LUMA]);
2016 if (q_data->nplanes == 2)
2017 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
2018
2019 return 0;
2020}
2021
2022static int vpe_buf_prepare(struct vb2_buffer *vb)
2023{
2024 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2025 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2026 struct vpe_q_data *q_data;
2027 int i, num_planes;
2028
2029 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
2030
2031 q_data = get_q_data(ctx, vb->vb2_queue->type);
2032 num_planes = q_data->nplanes;
2033
2034 if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
2035 if (!(q_data->flags & Q_IS_INTERLACED)) {
2036 vbuf->field = V4L2_FIELD_NONE;
2037 } else {
2038 if (vbuf->field != V4L2_FIELD_TOP &&
2039 vbuf->field != V4L2_FIELD_BOTTOM &&
2040 vbuf->field != V4L2_FIELD_SEQ_TB)
2041 return -EINVAL;
2042 }
2043 }
2044
2045 for (i = 0; i < num_planes; i++) {
2046 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
2047 vpe_err(ctx->dev,
2048 "data will not fit into plane (%lu < %lu)\n",
2049 vb2_plane_size(vb, i),
2050 (long) q_data->sizeimage[i]);
2051 return -EINVAL;
2052 }
2053 }
2054
2055 for (i = 0; i < num_planes; i++)
2056 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
2057
2058 return 0;
2059}
2060
2061static void vpe_buf_queue(struct vb2_buffer *vb)
2062{
2063 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2064 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2065
2066 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2067}
2068
2069static int check_srcdst_sizes(struct vpe_ctx *ctx)
2070{
2071 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
2072 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
2073 unsigned int src_w = s_q_data->c_rect.width;
2074 unsigned int src_h = s_q_data->c_rect.height;
2075 unsigned int dst_w = d_q_data->c_rect.width;
2076 unsigned int dst_h = d_q_data->c_rect.height;
2077
2078 if (src_w == dst_w && src_h == dst_h)
2079 return 0;
2080
2081 if (src_h <= SC_MAX_PIXEL_HEIGHT &&
2082 src_w <= SC_MAX_PIXEL_WIDTH &&
2083 dst_h <= SC_MAX_PIXEL_HEIGHT &&
2084 dst_w <= SC_MAX_PIXEL_WIDTH)
2085 return 0;
2086
2087 return -1;
2088}
2089
2090static void vpe_return_all_buffers(struct vpe_ctx *ctx, struct vb2_queue *q,
2091 enum vb2_buffer_state state)
2092{
2093 struct vb2_v4l2_buffer *vb;
2094 unsigned long flags;
2095
2096 for (;;) {
2097 if (V4L2_TYPE_IS_OUTPUT(q->type))
2098 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
2099 else
2100 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2101 if (!vb)
2102 break;
2103 spin_lock_irqsave(&ctx->dev->lock, flags);
2104 v4l2_m2m_buf_done(vb, state);
2105 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2106 }
2107
2108
2109
2110
2111
2112
2113 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2114 spin_lock_irqsave(&ctx->dev->lock, flags);
2115
2116 if (ctx->src_vbs[2])
2117 v4l2_m2m_buf_done(ctx->src_vbs[2], state);
2118
2119 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
2120 v4l2_m2m_buf_done(ctx->src_vbs[1], state);
2121
2122 if (ctx->src_vbs[0] &&
2123 (ctx->src_vbs[0] != ctx->src_vbs[1]) &&
2124 (ctx->src_vbs[0] != ctx->src_vbs[2]))
2125 v4l2_m2m_buf_done(ctx->src_vbs[0], state);
2126
2127 ctx->src_vbs[2] = NULL;
2128 ctx->src_vbs[1] = NULL;
2129 ctx->src_vbs[0] = NULL;
2130
2131 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2132 } else {
2133 if (ctx->dst_vb) {
2134 spin_lock_irqsave(&ctx->dev->lock, flags);
2135
2136 v4l2_m2m_buf_done(ctx->dst_vb, state);
2137 ctx->dst_vb = NULL;
2138 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2139 }
2140 }
2141}
2142
2143static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2144{
2145 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2146
2147
2148 if (check_srcdst_sizes(ctx)) {
2149 vpe_err(ctx->dev,
2150 "Conversion setup failed, check source and destination parameters\n"
2151 );
2152 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED);
2153 return -EINVAL;
2154 }
2155
2156 if (ctx->deinterlacing)
2157 config_edi_input_mode(ctx, 0x0);
2158
2159 if (ctx->sequence != 0)
2160 set_srcdst_params(ctx);
2161
2162 return 0;
2163}
2164
2165static void vpe_stop_streaming(struct vb2_queue *q)
2166{
2167 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2168
2169 vpe_dump_regs(ctx->dev);
2170 vpdma_dump_regs(ctx->dev->vpdma);
2171
2172 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR);
2173}
2174
2175static const struct vb2_ops vpe_qops = {
2176 .queue_setup = vpe_queue_setup,
2177 .buf_prepare = vpe_buf_prepare,
2178 .buf_queue = vpe_buf_queue,
2179 .wait_prepare = vb2_ops_wait_prepare,
2180 .wait_finish = vb2_ops_wait_finish,
2181 .start_streaming = vpe_start_streaming,
2182 .stop_streaming = vpe_stop_streaming,
2183};
2184
2185static int queue_init(void *priv, struct vb2_queue *src_vq,
2186 struct vb2_queue *dst_vq)
2187{
2188 struct vpe_ctx *ctx = priv;
2189 struct vpe_dev *dev = ctx->dev;
2190 int ret;
2191
2192 memset(src_vq, 0, sizeof(*src_vq));
2193 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2194 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2195 src_vq->drv_priv = ctx;
2196 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2197 src_vq->ops = &vpe_qops;
2198 src_vq->mem_ops = &vb2_dma_contig_memops;
2199 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2200 src_vq->lock = &dev->dev_mutex;
2201 src_vq->dev = dev->v4l2_dev.dev;
2202
2203 ret = vb2_queue_init(src_vq);
2204 if (ret)
2205 return ret;
2206
2207 memset(dst_vq, 0, sizeof(*dst_vq));
2208 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2209 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2210 dst_vq->drv_priv = ctx;
2211 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2212 dst_vq->ops = &vpe_qops;
2213 dst_vq->mem_ops = &vb2_dma_contig_memops;
2214 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2215 dst_vq->lock = &dev->dev_mutex;
2216 dst_vq->dev = dev->v4l2_dev.dev;
2217
2218 return vb2_queue_init(dst_vq);
2219}
2220
2221static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2222 .ops = &vpe_ctrl_ops,
2223 .id = V4L2_CID_VPE_BUFS_PER_JOB,
2224 .name = "Buffers Per Transaction",
2225 .type = V4L2_CTRL_TYPE_INTEGER,
2226 .def = VPE_DEF_BUFS_PER_JOB,
2227 .min = 1,
2228 .max = VIDEO_MAX_FRAME,
2229 .step = 1,
2230};
2231
2232
2233
2234
2235static int vpe_open(struct file *file)
2236{
2237 struct vpe_dev *dev = video_drvdata(file);
2238 struct vpe_q_data *s_q_data;
2239 struct v4l2_ctrl_handler *hdl;
2240 struct vpe_ctx *ctx;
2241 int ret;
2242
2243 vpe_dbg(dev, "vpe_open\n");
2244
2245 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2246 if (!ctx)
2247 return -ENOMEM;
2248
2249 ctx->dev = dev;
2250
2251 if (mutex_lock_interruptible(&dev->dev_mutex)) {
2252 ret = -ERESTARTSYS;
2253 goto free_ctx;
2254 }
2255
2256 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2257 VPDMA_LIST_TYPE_NORMAL);
2258 if (ret != 0)
2259 goto unlock;
2260
2261 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2262 if (ret != 0)
2263 goto free_desc_list;
2264
2265 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2266 if (ret != 0)
2267 goto free_mmr_adb;
2268
2269 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2270 if (ret != 0)
2271 goto free_sc_h;
2272
2273 init_adb_hdrs(ctx);
2274
2275 v4l2_fh_init(&ctx->fh, video_devdata(file));
2276 file->private_data = &ctx->fh;
2277
2278 hdl = &ctx->hdl;
2279 v4l2_ctrl_handler_init(hdl, 1);
2280 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2281 if (hdl->error) {
2282 ret = hdl->error;
2283 goto exit_fh;
2284 }
2285 ctx->fh.ctrl_handler = hdl;
2286 v4l2_ctrl_handler_setup(hdl);
2287
2288 s_q_data = &ctx->q_data[Q_DATA_SRC];
2289 s_q_data->fmt = &vpe_formats[2];
2290 s_q_data->width = 1920;
2291 s_q_data->height = 1080;
2292 s_q_data->nplanes = 1;
2293 s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2294 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2295 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2296 s_q_data->height);
2297 s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2298 s_q_data->field = V4L2_FIELD_NONE;
2299 s_q_data->c_rect.left = 0;
2300 s_q_data->c_rect.top = 0;
2301 s_q_data->c_rect.width = s_q_data->width;
2302 s_q_data->c_rect.height = s_q_data->height;
2303 s_q_data->flags = 0;
2304
2305 ctx->q_data[Q_DATA_DST] = *s_q_data;
2306
2307 set_dei_shadow_registers(ctx);
2308 set_src_registers(ctx);
2309 set_dst_registers(ctx);
2310 ret = set_srcdst_params(ctx);
2311 if (ret)
2312 goto exit_fh;
2313
2314 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2315
2316 if (IS_ERR(ctx->fh.m2m_ctx)) {
2317 ret = PTR_ERR(ctx->fh.m2m_ctx);
2318 goto exit_fh;
2319 }
2320
2321 v4l2_fh_add(&ctx->fh);
2322
2323
2324
2325
2326
2327
2328 if (atomic_inc_return(&dev->num_instances) == 1)
2329 vpe_dbg(dev, "first instance created\n");
2330
2331 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2332
2333 ctx->load_mmrs = true;
2334
2335 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2336 ctx, ctx->fh.m2m_ctx);
2337
2338 mutex_unlock(&dev->dev_mutex);
2339
2340 return 0;
2341exit_fh:
2342 v4l2_ctrl_handler_free(hdl);
2343 v4l2_fh_exit(&ctx->fh);
2344 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2345free_sc_h:
2346 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2347free_mmr_adb:
2348 vpdma_free_desc_buf(&ctx->mmr_adb);
2349free_desc_list:
2350 vpdma_free_desc_list(&ctx->desc_list);
2351unlock:
2352 mutex_unlock(&dev->dev_mutex);
2353free_ctx:
2354 kfree(ctx);
2355 return ret;
2356}
2357
2358static int vpe_release(struct file *file)
2359{
2360 struct vpe_dev *dev = video_drvdata(file);
2361 struct vpe_ctx *ctx = file2ctx(file);
2362
2363 vpe_dbg(dev, "releasing instance %p\n", ctx);
2364
2365 mutex_lock(&dev->dev_mutex);
2366 free_mv_buffers(ctx);
2367 vpdma_free_desc_list(&ctx->desc_list);
2368 vpdma_free_desc_buf(&ctx->mmr_adb);
2369
2370 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2371 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2372
2373 v4l2_fh_del(&ctx->fh);
2374 v4l2_fh_exit(&ctx->fh);
2375 v4l2_ctrl_handler_free(&ctx->hdl);
2376 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2377
2378 kfree(ctx);
2379
2380
2381
2382
2383
2384
2385 if (atomic_dec_return(&dev->num_instances) == 0)
2386 vpe_dbg(dev, "last instance released\n");
2387
2388 mutex_unlock(&dev->dev_mutex);
2389
2390 return 0;
2391}
2392
2393static const struct v4l2_file_operations vpe_fops = {
2394 .owner = THIS_MODULE,
2395 .open = vpe_open,
2396 .release = vpe_release,
2397 .poll = v4l2_m2m_fop_poll,
2398 .unlocked_ioctl = video_ioctl2,
2399 .mmap = v4l2_m2m_fop_mmap,
2400};
2401
2402static const struct video_device vpe_videodev = {
2403 .name = VPE_MODULE_NAME,
2404 .fops = &vpe_fops,
2405 .ioctl_ops = &vpe_ioctl_ops,
2406 .minor = -1,
2407 .release = video_device_release_empty,
2408 .vfl_dir = VFL_DIR_M2M,
2409 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
2410};
2411
2412static const struct v4l2_m2m_ops m2m_ops = {
2413 .device_run = device_run,
2414 .job_ready = job_ready,
2415 .job_abort = job_abort,
2416};
2417
2418static int vpe_runtime_get(struct platform_device *pdev)
2419{
2420 int r;
2421
2422 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2423
2424 r = pm_runtime_get_sync(&pdev->dev);
2425 WARN_ON(r < 0);
2426 return r < 0 ? r : 0;
2427}
2428
2429static void vpe_runtime_put(struct platform_device *pdev)
2430{
2431
2432 int r;
2433
2434 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2435
2436 r = pm_runtime_put_sync(&pdev->dev);
2437 WARN_ON(r < 0 && r != -ENOSYS);
2438}
2439
2440static void vpe_fw_cb(struct platform_device *pdev)
2441{
2442 struct vpe_dev *dev = platform_get_drvdata(pdev);
2443 struct video_device *vfd;
2444 int ret;
2445
2446 vfd = &dev->vfd;
2447 *vfd = vpe_videodev;
2448 vfd->lock = &dev->dev_mutex;
2449 vfd->v4l2_dev = &dev->v4l2_dev;
2450
2451 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2452 if (ret) {
2453 vpe_err(dev, "Failed to register video device\n");
2454
2455 vpe_set_clock_enable(dev, 0);
2456 vpe_runtime_put(pdev);
2457 pm_runtime_disable(&pdev->dev);
2458 v4l2_m2m_release(dev->m2m_dev);
2459 v4l2_device_unregister(&dev->v4l2_dev);
2460
2461 return;
2462 }
2463
2464 video_set_drvdata(vfd, dev);
2465 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2466 vfd->num);
2467}
2468
2469static int vpe_probe(struct platform_device *pdev)
2470{
2471 struct vpe_dev *dev;
2472 int ret, irq, func;
2473
2474 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2475 if (!dev)
2476 return -ENOMEM;
2477
2478 spin_lock_init(&dev->lock);
2479
2480 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2481 if (ret)
2482 return ret;
2483
2484 atomic_set(&dev->num_instances, 0);
2485 mutex_init(&dev->dev_mutex);
2486
2487 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2488 "vpe_top");
2489
2490
2491
2492
2493
2494
2495 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2496 if (!dev->base) {
2497 ret = -ENOMEM;
2498 goto v4l2_dev_unreg;
2499 }
2500
2501 irq = platform_get_irq(pdev, 0);
2502 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2503 dev);
2504 if (ret)
2505 goto v4l2_dev_unreg;
2506
2507 platform_set_drvdata(pdev, dev);
2508
2509 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2510 if (IS_ERR(dev->m2m_dev)) {
2511 vpe_err(dev, "Failed to init mem2mem device\n");
2512 ret = PTR_ERR(dev->m2m_dev);
2513 goto v4l2_dev_unreg;
2514 }
2515
2516 pm_runtime_enable(&pdev->dev);
2517
2518 ret = vpe_runtime_get(pdev);
2519 if (ret)
2520 goto rel_m2m;
2521
2522
2523 vpe_set_clock_enable(dev, 1);
2524
2525 vpe_top_reset(dev);
2526
2527 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2528 VPE_PID_FUNC_SHIFT);
2529 vpe_dbg(dev, "VPE PID function %x\n", func);
2530
2531 vpe_top_vpdma_reset(dev);
2532
2533 dev->sc = sc_create(pdev, "sc");
2534 if (IS_ERR(dev->sc)) {
2535 ret = PTR_ERR(dev->sc);
2536 goto runtime_put;
2537 }
2538
2539 dev->csc = csc_create(pdev, "csc");
2540 if (IS_ERR(dev->csc)) {
2541 ret = PTR_ERR(dev->csc);
2542 goto runtime_put;
2543 }
2544
2545 dev->vpdma = &dev->vpdma_data;
2546 ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb);
2547 if (ret)
2548 goto runtime_put;
2549
2550 return 0;
2551
2552runtime_put:
2553 vpe_runtime_put(pdev);
2554rel_m2m:
2555 pm_runtime_disable(&pdev->dev);
2556 v4l2_m2m_release(dev->m2m_dev);
2557v4l2_dev_unreg:
2558 v4l2_device_unregister(&dev->v4l2_dev);
2559
2560 return ret;
2561}
2562
2563static int vpe_remove(struct platform_device *pdev)
2564{
2565 struct vpe_dev *dev = platform_get_drvdata(pdev);
2566
2567 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2568
2569 v4l2_m2m_release(dev->m2m_dev);
2570 video_unregister_device(&dev->vfd);
2571 v4l2_device_unregister(&dev->v4l2_dev);
2572
2573 vpe_set_clock_enable(dev, 0);
2574 vpe_runtime_put(pdev);
2575 pm_runtime_disable(&pdev->dev);
2576
2577 return 0;
2578}
2579
2580#if defined(CONFIG_OF)
2581static const struct of_device_id vpe_of_match[] = {
2582 {
2583 .compatible = "ti,vpe",
2584 },
2585 {},
2586};
2587MODULE_DEVICE_TABLE(of, vpe_of_match);
2588#endif
2589
2590static struct platform_driver vpe_pdrv = {
2591 .probe = vpe_probe,
2592 .remove = vpe_remove,
2593 .driver = {
2594 .name = VPE_MODULE_NAME,
2595 .of_match_table = of_match_ptr(vpe_of_match),
2596 },
2597};
2598
2599module_platform_driver(vpe_pdrv);
2600
2601MODULE_DESCRIPTION("TI VPE driver");
2602MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2603MODULE_LICENSE("GPL");
2604