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8#include <linux/clk.h>
9#include <linux/interrupt.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <linux/reset.h>
13#include <media/rc-core.h>
14
15#define MTK_IR_DEV KBUILD_MODNAME
16
17
18#define MTK_CONFIG_HIGH_REG 0x0c
19
20
21#define MTK_PWM_EN BIT(13)
22
23
24
25
26
27#define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16)
28
29
30#define MTK_IR_EN BIT(0)
31
32
33#define MTK_IRCLR BIT(0)
34
35
36#define MTK_WIDTH_MASK (GENMASK(7, 0))
37
38
39#define MTK_IRINT_EN BIT(0)
40
41
42#define MTK_IRINT_CLR BIT(0)
43
44
45#define MTK_MAX_SAMPLES 0xff
46
47#define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
48
49#define MTK_CHKDATA_SZ 17
50
51#define MTK_IR_SAMPLE 46000
52
53enum mtk_fields {
54
55 MTK_CHK_PERIOD,
56
57 MTK_HW_PERIOD,
58};
59
60enum mtk_regs {
61
62 MTK_IRCLR_REG,
63
64 MTK_CHKDATA_REG,
65
66 MTK_IRINT_EN_REG,
67
68 MTK_IRINT_CLR_REG
69};
70
71static const u32 mt7623_regs[] = {
72 [MTK_IRCLR_REG] = 0x20,
73 [MTK_CHKDATA_REG] = 0x88,
74 [MTK_IRINT_EN_REG] = 0xcc,
75 [MTK_IRINT_CLR_REG] = 0xd0,
76};
77
78static const u32 mt7622_regs[] = {
79 [MTK_IRCLR_REG] = 0x18,
80 [MTK_CHKDATA_REG] = 0x30,
81 [MTK_IRINT_EN_REG] = 0x1c,
82 [MTK_IRINT_CLR_REG] = 0x20,
83};
84
85struct mtk_field_type {
86 u32 reg;
87 u8 offset;
88 u32 mask;
89};
90
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100
101struct mtk_ir_data {
102 const u32 *regs;
103 const struct mtk_field_type *fields;
104 u8 div;
105 u8 ok_count;
106 u32 hw_period;
107};
108
109static const struct mtk_field_type mt7623_fields[] = {
110 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
111 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
112};
113
114static const struct mtk_field_type mt7622_fields[] = {
115 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
116 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
117};
118
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128
129
130struct mtk_ir {
131 struct device *dev;
132 struct rc_dev *rc;
133 void __iomem *base;
134 int irq;
135 struct clk *clk;
136 struct clk *bus;
137 const struct mtk_ir_data *data;
138};
139
140static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
141{
142 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
143}
144
145static inline u32 mtk_chk_period(struct mtk_ir *ir)
146{
147 u32 val;
148
149
150 val = DIV_ROUND_CLOSEST(1000000000ul,
151 clk_get_rate(ir->bus) / ir->data->div);
152
153
154
155
156
157 val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val);
158
159 dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
160 clk_get_rate(ir->bus) / ir->data->div);
161 dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
162
163 return val;
164}
165
166static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
167{
168 u32 tmp;
169
170 tmp = __raw_readl(ir->base + reg);
171 tmp = (tmp & ~mask) | val;
172 __raw_writel(tmp, ir->base + reg);
173}
174
175static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
176{
177 __raw_writel(val, ir->base + reg);
178}
179
180static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
181{
182 return __raw_readl(ir->base + reg);
183}
184
185static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
186{
187 u32 val;
188
189 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
190 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
191}
192
193static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
194{
195 u32 val;
196
197 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
198 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
199}
200
201static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
202{
203 struct mtk_ir *ir = dev_id;
204 u8 wid = 0;
205 u32 i, j, val;
206 struct ir_raw_event rawir = {};
207
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214
215
216
217
218 ir_raw_event_reset(ir->rc);
219
220
221 rawir.pulse = false;
222
223
224 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
225 val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
226 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
227
228 for (j = 0 ; j < 4 ; j++) {
229 wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
230 rawir.pulse = !rawir.pulse;
231 rawir.duration = wid * (MTK_IR_SAMPLE + 1);
232 ir_raw_event_store_with_filter(ir->rc, &rawir);
233 }
234 }
235
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237
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242
243
244
245 if (!MTK_IR_END(wid, rawir.pulse)) {
246 rawir.pulse = false;
247 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
248 ir_raw_event_store_with_filter(ir->rc, &rawir);
249 }
250
251 ir_raw_event_handle(ir->rc);
252
253
254
255
256
257 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
258
259
260 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
261 ir->data->regs[MTK_IRINT_CLR_REG]);
262
263 return IRQ_HANDLED;
264}
265
266static const struct mtk_ir_data mt7623_data = {
267 .regs = mt7623_regs,
268 .fields = mt7623_fields,
269 .ok_count = 0xf,
270 .hw_period = 0xff,
271 .div = 4,
272};
273
274static const struct mtk_ir_data mt7622_data = {
275 .regs = mt7622_regs,
276 .fields = mt7622_fields,
277 .ok_count = 0xf,
278 .hw_period = 0xffff,
279 .div = 32,
280};
281
282static const struct of_device_id mtk_ir_match[] = {
283 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
284 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
285 {},
286};
287MODULE_DEVICE_TABLE(of, mtk_ir_match);
288
289static int mtk_ir_probe(struct platform_device *pdev)
290{
291 struct device *dev = &pdev->dev;
292 struct device_node *dn = dev->of_node;
293 struct resource *res;
294 struct mtk_ir *ir;
295 u32 val;
296 int ret = 0;
297 const char *map_name;
298
299 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
300 if (!ir)
301 return -ENOMEM;
302
303 ir->dev = dev;
304 ir->data = of_device_get_match_data(dev);
305
306 ir->clk = devm_clk_get(dev, "clk");
307 if (IS_ERR(ir->clk)) {
308 dev_err(dev, "failed to get a ir clock.\n");
309 return PTR_ERR(ir->clk);
310 }
311
312 ir->bus = devm_clk_get(dev, "bus");
313 if (IS_ERR(ir->bus)) {
314
315
316
317
318 ir->bus = ir->clk;
319 }
320
321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
322 ir->base = devm_ioremap_resource(dev, res);
323 if (IS_ERR(ir->base))
324 return PTR_ERR(ir->base);
325
326 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
327 if (!ir->rc) {
328 dev_err(dev, "failed to allocate device\n");
329 return -ENOMEM;
330 }
331
332 ir->rc->priv = ir;
333 ir->rc->device_name = MTK_IR_DEV;
334 ir->rc->input_phys = MTK_IR_DEV "/input0";
335 ir->rc->input_id.bustype = BUS_HOST;
336 ir->rc->input_id.vendor = 0x0001;
337 ir->rc->input_id.product = 0x0001;
338 ir->rc->input_id.version = 0x0001;
339 map_name = of_get_property(dn, "linux,rc-map-name", NULL);
340 ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
341 ir->rc->dev.parent = dev;
342 ir->rc->driver_name = MTK_IR_DEV;
343 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL;
344 ir->rc->rx_resolution = MTK_IR_SAMPLE;
345 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
346
347 ret = devm_rc_register_device(dev, ir->rc);
348 if (ret) {
349 dev_err(dev, "failed to register rc device\n");
350 return ret;
351 }
352
353 platform_set_drvdata(pdev, ir);
354
355 ir->irq = platform_get_irq(pdev, 0);
356 if (ir->irq < 0) {
357 dev_err(dev, "no irq resource\n");
358 return -ENODEV;
359 }
360
361 if (clk_prepare_enable(ir->clk)) {
362 dev_err(dev, "try to enable ir_clk failed\n");
363 return -EINVAL;
364 }
365
366 if (clk_prepare_enable(ir->bus)) {
367 dev_err(dev, "try to enable ir_clk failed\n");
368 ret = -EINVAL;
369 goto exit_clkdisable_clk;
370 }
371
372
373
374
375
376 mtk_irq_disable(ir, MTK_IRINT_EN);
377
378 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
379 if (ret) {
380 dev_err(dev, "failed request irq\n");
381 goto exit_clkdisable_bus;
382 }
383
384
385
386
387 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
388 ir->data->fields[MTK_CHK_PERIOD].mask;
389 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
390 ir->data->fields[MTK_CHK_PERIOD].reg);
391
392
393
394
395
396 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
397 ir->data->fields[MTK_HW_PERIOD].mask;
398 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
399 ir->data->fields[MTK_HW_PERIOD].reg);
400
401
402 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
403 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
404 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
405
406 mtk_irq_enable(ir, MTK_IRINT_EN);
407
408 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
409 DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));
410
411 return 0;
412
413exit_clkdisable_bus:
414 clk_disable_unprepare(ir->bus);
415exit_clkdisable_clk:
416 clk_disable_unprepare(ir->clk);
417
418 return ret;
419}
420
421static int mtk_ir_remove(struct platform_device *pdev)
422{
423 struct mtk_ir *ir = platform_get_drvdata(pdev);
424
425
426
427
428
429
430 mtk_irq_disable(ir, MTK_IRINT_EN);
431 synchronize_irq(ir->irq);
432
433 clk_disable_unprepare(ir->bus);
434 clk_disable_unprepare(ir->clk);
435
436 return 0;
437}
438
439static struct platform_driver mtk_ir_driver = {
440 .probe = mtk_ir_probe,
441 .remove = mtk_ir_remove,
442 .driver = {
443 .name = MTK_IR_DEV,
444 .of_match_table = mtk_ir_match,
445 },
446};
447
448module_platform_driver(mtk_ir_driver);
449
450MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
451MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
452MODULE_LICENSE("GPL");
453