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6#include <linux/spinlock.h>
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/device.h>
10#include <linux/mutex.h>
11#include <linux/init.h>
12#include <linux/list.h>
13#include <linux/mm.h>
14#include <linux/of.h>
15#include <linux/slab.h>
16#include <linux/idr.h>
17#include <linux/pci.h>
18#include <linux/sched/task.h>
19
20#include <asm/cputable.h>
21#include <misc/cxl-base.h>
22
23#include "cxl.h"
24#include "trace.h"
25
26static DEFINE_SPINLOCK(adapter_idr_lock);
27static DEFINE_IDR(cxl_adapter_idr);
28
29uint cxl_verbose;
30module_param_named(verbose, cxl_verbose, uint, 0600);
31MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
32
33const struct cxl_backend_ops *cxl_ops;
34
35int cxl_afu_slbia(struct cxl_afu *afu)
36{
37 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
38
39 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
40 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
41 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
42 if (time_after_eq(jiffies, timeout)) {
43 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
44 return -EBUSY;
45 }
46
47
48
49 if (!cxl_ops->link_ok(afu->adapter, afu))
50 return -EIO;
51 cpu_relax();
52 }
53 return 0;
54}
55
56static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
57{
58 unsigned long flags;
59
60 if (ctx->mm != mm)
61 return;
62
63 pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
64 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
65
66 spin_lock_irqsave(&ctx->sste_lock, flags);
67 trace_cxl_slbia(ctx);
68 memset(ctx->sstp, 0, ctx->sst_size);
69 spin_unlock_irqrestore(&ctx->sste_lock, flags);
70 mb();
71 cxl_afu_slbia(ctx->afu);
72}
73
74static inline void cxl_slbia_core(struct mm_struct *mm)
75{
76 struct cxl *adapter;
77 struct cxl_afu *afu;
78 struct cxl_context *ctx;
79 int card, slice, id;
80
81 pr_devel("%s called\n", __func__);
82
83 spin_lock(&adapter_idr_lock);
84 idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
85
86 spin_lock(&adapter->afu_list_lock);
87 for (slice = 0; slice < adapter->slices; slice++) {
88 afu = adapter->afu[slice];
89 if (!afu || !afu->enabled)
90 continue;
91 rcu_read_lock();
92 idr_for_each_entry(&afu->contexts_idr, ctx, id)
93 _cxl_slbia(ctx, mm);
94 rcu_read_unlock();
95 }
96 spin_unlock(&adapter->afu_list_lock);
97 }
98 spin_unlock(&adapter_idr_lock);
99}
100
101static struct cxl_calls cxl_calls = {
102 .cxl_slbia = cxl_slbia_core,
103 .owner = THIS_MODULE,
104};
105
106int cxl_alloc_sst(struct cxl_context *ctx)
107{
108 unsigned long vsid;
109 u64 ea_mask, size, sstp0, sstp1;
110
111 sstp0 = 0;
112 sstp1 = 0;
113
114 ctx->sst_size = PAGE_SIZE;
115 ctx->sst_lru = 0;
116 ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
117 if (!ctx->sstp) {
118 pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
119 return -ENOMEM;
120 }
121 pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
122
123 vsid = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
124
125 sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
126 sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
127
128 size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
129 if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
130 WARN(1, "Impossible segment table size\n");
131 return -EINVAL;
132 }
133 sstp0 |= size;
134
135 if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
136 ea_mask = 0xfffff00ULL;
137 else
138 ea_mask = 0xffffffff00ULL;
139
140 sstp0 |= vsid >> (50-14);
141 sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
142 sstp1 |= (u64)ctx->sstp & ea_mask;
143 sstp1 |= CXL_SSTP1_An_V;
144
145 pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
146 (u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
147
148
149 ctx->sstp0 = sstp0;
150 ctx->sstp1 = sstp1;
151
152 return 0;
153}
154
155
156void cxl_dump_debug_buffer(void *buf, size_t buf_len)
157{
158#ifdef DEBUG
159 int i, *ptr;
160
161
162
163
164
165 ptr = (int *) buf;
166 for (i = 0; i * 4 < buf_len; i += 4) {
167 if ((i + 3) * 4 < buf_len)
168 pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
169 ptr[i + 2], ptr[i + 3]);
170 else if ((i + 2) * 4 < buf_len)
171 pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
172 ptr[i + 2]);
173 else if ((i + 1) * 4 < buf_len)
174 pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
175 else
176 pr_devel("%.8x\n", ptr[i]);
177 }
178#endif
179}
180
181
182struct cxl *get_cxl_adapter(int num)
183{
184 struct cxl *adapter;
185
186 spin_lock(&adapter_idr_lock);
187 if ((adapter = idr_find(&cxl_adapter_idr, num)))
188 get_device(&adapter->dev);
189 spin_unlock(&adapter_idr_lock);
190
191 return adapter;
192}
193
194static int cxl_alloc_adapter_nr(struct cxl *adapter)
195{
196 int i;
197
198 idr_preload(GFP_KERNEL);
199 spin_lock(&adapter_idr_lock);
200 i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
201 spin_unlock(&adapter_idr_lock);
202 idr_preload_end();
203 if (i < 0)
204 return i;
205
206 adapter->adapter_num = i;
207
208 return 0;
209}
210
211void cxl_remove_adapter_nr(struct cxl *adapter)
212{
213 idr_remove(&cxl_adapter_idr, adapter->adapter_num);
214}
215
216struct cxl *cxl_alloc_adapter(void)
217{
218 struct cxl *adapter;
219
220 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
221 return NULL;
222
223 spin_lock_init(&adapter->afu_list_lock);
224
225 if (cxl_alloc_adapter_nr(adapter))
226 goto err1;
227
228 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
229 goto err2;
230
231
232 atomic_set(&adapter->contexts_num, -1);
233
234 return adapter;
235err2:
236 cxl_remove_adapter_nr(adapter);
237err1:
238 kfree(adapter);
239 return NULL;
240}
241
242struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
243{
244 struct cxl_afu *afu;
245
246 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
247 return NULL;
248
249 afu->adapter = adapter;
250 afu->dev.parent = &adapter->dev;
251 afu->dev.release = cxl_ops->release_afu;
252 afu->slice = slice;
253 idr_init(&afu->contexts_idr);
254 mutex_init(&afu->contexts_lock);
255 spin_lock_init(&afu->afu_cntl_lock);
256 atomic_set(&afu->configured_state, -1);
257 afu->prefault_mode = CXL_PREFAULT_NONE;
258 afu->irqs_max = afu->adapter->user_irqs;
259
260 return afu;
261}
262
263int cxl_afu_select_best_mode(struct cxl_afu *afu)
264{
265 if (afu->modes_supported & CXL_MODE_DIRECTED)
266 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
267
268 if (afu->modes_supported & CXL_MODE_DEDICATED)
269 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
270
271 dev_warn(&afu->dev, "No supported programming modes available\n");
272
273 return 0;
274}
275
276int cxl_adapter_context_get(struct cxl *adapter)
277{
278 int rc;
279
280 rc = atomic_inc_unless_negative(&adapter->contexts_num);
281 return rc ? 0 : -EBUSY;
282}
283
284void cxl_adapter_context_put(struct cxl *adapter)
285{
286 atomic_dec_if_positive(&adapter->contexts_num);
287}
288
289int cxl_adapter_context_lock(struct cxl *adapter)
290{
291 int rc;
292
293 rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
294 return rc ? -EBUSY : 0;
295}
296
297void cxl_adapter_context_unlock(struct cxl *adapter)
298{
299 int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
300
301
302
303
304
305
306
307 if (val != -1) {
308 atomic_set(&adapter->contexts_num, 0);
309 WARN(1, "Adapter context unlocked with %d active contexts",
310 val);
311 }
312}
313
314static int __init init_cxl(void)
315{
316 int rc = 0;
317
318 if ((rc = cxl_file_init()))
319 return rc;
320
321 cxl_debugfs_init();
322
323
324
325
326
327 if (cxl_is_power8()) {
328 rc = register_cxl_calls(&cxl_calls);
329 if (rc)
330 goto err;
331 }
332
333 if (cpu_has_feature(CPU_FTR_HVMODE)) {
334 cxl_ops = &cxl_native_ops;
335 rc = pci_register_driver(&cxl_pci_driver);
336 }
337#ifdef CONFIG_PPC_PSERIES
338 else {
339 cxl_ops = &cxl_guest_ops;
340 rc = platform_driver_register(&cxl_of_driver);
341 }
342#endif
343 if (rc)
344 goto err1;
345
346 return 0;
347err1:
348 if (cxl_is_power8())
349 unregister_cxl_calls(&cxl_calls);
350err:
351 cxl_debugfs_exit();
352 cxl_file_exit();
353
354 return rc;
355}
356
357static void exit_cxl(void)
358{
359 if (cpu_has_feature(CPU_FTR_HVMODE))
360 pci_unregister_driver(&cxl_pci_driver);
361#ifdef CONFIG_PPC_PSERIES
362 else
363 platform_driver_unregister(&cxl_of_driver);
364#endif
365
366 cxl_debugfs_exit();
367 cxl_file_exit();
368 if (cxl_is_power8())
369 unregister_cxl_calls(&cxl_calls);
370 idr_destroy(&cxl_adapter_idr);
371}
372
373module_init(init_cxl);
374module_exit(exit_cxl);
375
376MODULE_DESCRIPTION("IBM Coherent Accelerator");
377MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
378MODULE_LICENSE("GPL");
379
