LXR linux/drivers/misc/pch

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4 */
   5
   6#include <linux/module.h>
   7#include <linux/kernel.h>
   8#include <linux/types.h>
   9#include <linux/fs.h>
  10#include <linux/uaccess.h>
  11#include <linux/string.h>
  12#include <linux/pci.h>
  13#include <linux/io.h>
  14#include <linux/delay.h>
  15#include <linux/mutex.h>
  16#include <linux/if_ether.h>
  17#include <linux/ctype.h>
  18#include <linux/dmi.h>
  19#include <linux/of.h>
  20
  21#define PHUB_STATUS 0x00                /* Status Register offset */
  22#define PHUB_CONTROL 0x04               /* Control Register offset */
  23#define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
  24#define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
  25#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
  26#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14  /* MAC data area start address
  27                                               offset */
  28#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C  /* MAC data area start address
  29                                                 offset */
  30#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
  31                                              (Intel EG20T PCH)*/
  32#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
  33                                                offset(LAPIS Semicon ML7213)
  34                                              */
  35#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
  36                                                offset(LAPIS Semicon ML7223)
  37                                              */
  38
  39/* MAX number of INT_REDUCE_CONTROL registers */
  40#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
  41#define PCI_DEVICE_ID_PCH1_PHUB 0x8801
  42#define PCH_MINOR_NOS 1
  43#define CLKCFG_CAN_50MHZ 0x12000000
  44#define CLKCFG_CANCLK_MASK 0xFF000000
  45#define CLKCFG_UART_MASK                        0xFFFFFF
  46
  47/* CM-iTC */
  48#define CLKCFG_UART_48MHZ                       (1 << 16)
  49#define CLKCFG_UART_25MHZ                       (2 << 16)
  50#define CLKCFG_BAUDDIV                          (2 << 20)
  51#define CLKCFG_PLL2VCO                          (8 << 9)
  52#define CLKCFG_UARTCLKSEL                       (1 << 18)
  53
  54/* Macros for ML7213 */
  55#define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
  56
  57/* Macros for ML7223 */
  58#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
  59#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
  60
  61/* Macros for ML7831 */
  62#define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
  63
  64/* SROM ACCESS Macro */
  65#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
  66
  67/* Registers address offset */
  68#define PCH_PHUB_ID_REG                         0x0000
  69#define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
  70#define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
  71#define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
  72#define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
  73#define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
  74#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
  75#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
  76#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
  77#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
  78#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
  79#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
  80#define CLKCFG_REG_OFFSET                       0x500
  81#define FUNCSEL_REG_OFFSET                      0x508
  82
  83#define PCH_PHUB_OROM_SIZE 15360
  84
  85/**
  86 * struct pch_phub_reg - PHUB register structure
  87 * @phub_id_reg:                        PHUB_ID register val
  88 * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
  89 * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
  90 * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
  91 * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
  92 * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
  93 * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
  94 * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
  95 * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
  96 * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
  97 * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
  98 * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
  99 * @clkcfg_reg:                         CLK CFG register val
 100 * @funcsel_reg:                        Function select register value
 101 * @pch_phub_base_address:              Register base address
 102 * @pch_phub_extrom_base_address:       external rom base address
 103 * @pch_mac_start_address:              MAC address area start address
 104 * @pch_opt_rom_start_address:          Option ROM start address
 105 * @ioh_type:                           Save IOH type
 106 * @pdev:                               pointer to pci device struct
 107 */
 108struct pch_phub_reg {
 109        u32 phub_id_reg;
 110        u32 q_pri_val_reg;
 111        u32 rc_q_maxsize_reg;
 112        u32 bri_q_maxsize_reg;
 113        u32 comp_resp_timeout_reg;
 114        u32 bus_slave_control_reg;
 115        u32 deadlock_avoid_type_reg;
 116        u32 intpin_reg_wpermit_reg0;
 117        u32 intpin_reg_wpermit_reg1;
 118        u32 intpin_reg_wpermit_reg2;
 119        u32 intpin_reg_wpermit_reg3;
 120        u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
 121        u32 clkcfg_reg;
 122        u32 funcsel_reg;
 123        void __iomem *pch_phub_base_address;
 124        void __iomem *pch_phub_extrom_base_address;
 125        u32 pch_mac_start_address;
 126        u32 pch_opt_rom_start_address;
 127        int ioh_type;
 128        struct pci_dev *pdev;
 129};
 130
 131/* SROM SPEC for MAC address assignment offset */
 132static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
 133
 134static DEFINE_MUTEX(pch_phub_mutex);
 135
 136/**
 137 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
 138 * @reg_addr_offset:    Register offset address value.
 139 * @data:               Writing value.
 140 * @mask:               Mask value.
 141 */
 142static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
 143                                           unsigned int reg_addr_offset,
 144                                           unsigned int data, unsigned int mask)
 145{
 146        void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
 147        iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
 148}
 149
 150#ifdef CONFIG_PM
 151/* pch_phub_save_reg_conf - saves register configuration */
 152static void pch_phub_save_reg_conf(struct pci_dev *pdev)
 153{
 154        unsigned int i;
 155        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 156
 157        void __iomem *p = chip->pch_phub_base_address;
 158
 159        chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
 160        chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 161        chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 162        chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 163        chip->comp_resp_timeout_reg =
 164                                ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 165        chip->bus_slave_control_reg =
 166                                ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 167        chip->deadlock_avoid_type_reg =
 168                                ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 169        chip->intpin_reg_wpermit_reg0 =
 170                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 171        chip->intpin_reg_wpermit_reg1 =
 172                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 173        chip->intpin_reg_wpermit_reg2 =
 174                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 175        chip->intpin_reg_wpermit_reg3 =
 176                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 177        dev_dbg(&pdev->dev, "%s : "
 178                "chip->phub_id_reg=%x, "
 179                "chip->q_pri_val_reg=%x, "
 180                "chip->rc_q_maxsize_reg=%x, "
 181                "chip->bri_q_maxsize_reg=%x, "
 182                "chip->comp_resp_timeout_reg=%x, "
 183                "chip->bus_slave_control_reg=%x, "
 184                "chip->deadlock_avoid_type_reg=%x, "
 185                "chip->intpin_reg_wpermit_reg0=%x, "
 186                "chip->intpin_reg_wpermit_reg1=%x, "
 187                "chip->intpin_reg_wpermit_reg2=%x, "
 188                "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 189                chip->phub_id_reg,
 190                chip->q_pri_val_reg,
 191                chip->rc_q_maxsize_reg,
 192                chip->bri_q_maxsize_reg,
 193                chip->comp_resp_timeout_reg,
 194                chip->bus_slave_control_reg,
 195                chip->deadlock_avoid_type_reg,
 196                chip->intpin_reg_wpermit_reg0,
 197                chip->intpin_reg_wpermit_reg1,
 198                chip->intpin_reg_wpermit_reg2,
 199                chip->intpin_reg_wpermit_reg3);
 200        for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 201                chip->int_reduce_control_reg[i] =
 202                    ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 203                dev_dbg(&pdev->dev, "%s : "
 204                        "chip->int_reduce_control_reg[%d]=%x\n",
 205                        __func__, i, chip->int_reduce_control_reg[i]);
 206        }
 207        chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
 208        if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 209                chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
 210}
 211
 212/* pch_phub_restore_reg_conf - restore register configuration */
 213static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
 214{
 215        unsigned int i;
 216        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 217        void __iomem *p;
 218        p = chip->pch_phub_base_address;
 219
 220        iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
 221        iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 222        iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 223        iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 224        iowrite32(chip->comp_resp_timeout_reg,
 225                                        p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 226        iowrite32(chip->bus_slave_control_reg,
 227                                        p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 228        iowrite32(chip->deadlock_avoid_type_reg,
 229                                        p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 230        iowrite32(chip->intpin_reg_wpermit_reg0,
 231                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 232        iowrite32(chip->intpin_reg_wpermit_reg1,
 233                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 234        iowrite32(chip->intpin_reg_wpermit_reg2,
 235                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 236        iowrite32(chip->intpin_reg_wpermit_reg3,
 237                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 238        dev_dbg(&pdev->dev, "%s : "
 239                "chip->phub_id_reg=%x, "
 240                "chip->q_pri_val_reg=%x, "
 241                "chip->rc_q_maxsize_reg=%x, "
 242                "chip->bri_q_maxsize_reg=%x, "
 243                "chip->comp_resp_timeout_reg=%x, "
 244                "chip->bus_slave_control_reg=%x, "
 245                "chip->deadlock_avoid_type_reg=%x, "
 246                "chip->intpin_reg_wpermit_reg0=%x, "
 247                "chip->intpin_reg_wpermit_reg1=%x, "
 248                "chip->intpin_reg_wpermit_reg2=%x, "
 249                "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 250                chip->phub_id_reg,
 251                chip->q_pri_val_reg,
 252                chip->rc_q_maxsize_reg,
 253                chip->bri_q_maxsize_reg,
 254                chip->comp_resp_timeout_reg,
 255                chip->bus_slave_control_reg,
 256                chip->deadlock_avoid_type_reg,
 257                chip->intpin_reg_wpermit_reg0,
 258                chip->intpin_reg_wpermit_reg1,
 259                chip->intpin_reg_wpermit_reg2,
 260                chip->intpin_reg_wpermit_reg3);
 261        for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 262                iowrite32(chip->int_reduce_control_reg[i],
 263                        p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 264                dev_dbg(&pdev->dev, "%s : "
 265                        "chip->int_reduce_control_reg[%d]=%x\n",
 266                        __func__, i, chip->int_reduce_control_reg[i]);
 267        }
 268
 269        iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
 270        if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 271                iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
 272}
 273#endif
 274
 275/**
 276 * pch_phub_read_serial_rom() - Reading Serial ROM
 277 * @offset_address:     Serial ROM offset address to read.
 278 * @data:               Read buffer for specified Serial ROM value.
 279 */
 280static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
 281                                     unsigned int offset_address, u8 *data)
 282{
 283        void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 284                                                                offset_address;
 285
 286        *data = ioread8(mem_addr);
 287}
 288
 289/**
 290 * pch_phub_write_serial_rom() - Writing Serial ROM
 291 * @offset_address:     Serial ROM offset address.
 292 * @data:               Serial ROM value to write.
 293 */
 294static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
 295                                     unsigned int offset_address, u8 data)
 296{
 297        void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 298                                        (offset_address & PCH_WORD_ADDR_MASK);
 299        int i;
 300        unsigned int word_data;
 301        unsigned int pos;
 302        unsigned int mask;
 303        pos = (offset_address % 4) * 8;
 304        mask = ~(0xFF << pos);
 305
 306        iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
 307                        chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 308
 309        word_data = ioread32(mem_addr);
 310        iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
 311
 312        i = 0;
 313        while (ioread8(chip->pch_phub_extrom_base_address +
 314                                                PHUB_STATUS) != 0x00) {
 315                msleep(1);
 316                if (i == PHUB_TIMEOUT)
 317                        return -ETIMEDOUT;
 318                i++;
 319        }
 320
 321        iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
 322                        chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 323
 324        return 0;
 325}
 326
 327/**
 328 * pch_phub_read_serial_rom_val() - Read Serial ROM value
 329 * @offset_address:     Serial ROM address offset value.
 330 * @data:               Serial ROM value to read.
 331 */
 332static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
 333                                         unsigned int offset_address, u8 *data)
 334{
 335        unsigned int mem_addr;
 336
 337        mem_addr = chip->pch_mac_start_address +
 338                        pch_phub_mac_offset[offset_address];
 339
 340        pch_phub_read_serial_rom(chip, mem_addr, data);
 341}
 342
 343/**
 344 * pch_phub_write_serial_rom_val() - writing Serial ROM value
 345 * @offset_address:     Serial ROM address offset value.
 346 * @data:               Serial ROM value.
 347 */
 348static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
 349                                         unsigned int offset_address, u8 data)
 350{
 351        int retval;
 352        unsigned int mem_addr;
 353
 354        mem_addr = chip->pch_mac_start_address +
 355                        pch_phub_mac_offset[offset_address];
 356
 357        retval = pch_phub_write_serial_rom(chip, mem_addr, data);
 358
 359        return retval;
 360}
 361
 362/* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
 363 * for Gigabit Ethernet MAC address
 364 */
 365static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
 366{
 367        int retval;
 368
 369        retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
 370        retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
 371        retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
 372        retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
 373
 374        retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
 375        retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
 376        retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
 377        retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
 378
 379        retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
 380        retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
 381        retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
 382        retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
 383
 384        retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
 385        retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
 386        retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
 387        retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
 388
 389        retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
 390        retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
 391        retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
 392        retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
 393
 394        retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
 395        retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
 396        retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
 397        retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
 398
 399        return retval;
 400}
 401
 402/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
 403 * for Gigabit Ethernet MAC address
 404 */
 405static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
 406{
 407        int retval;
 408        u32 offset_addr;
 409
 410        offset_addr = 0x200;
 411        retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
 412        retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
 413        retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
 414        retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
 415
 416        retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
 417        retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
 418        retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
 419        retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
 420
 421        retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
 422        retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
 423        retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
 424        retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
 425
 426        retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
 427        retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
 428        retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
 429        retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
 430
 431        retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
 432        retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
 433        retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
 434        retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
 435
 436        retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
 437        retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
 438        retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
 439        retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
 440
 441        return retval;
 442}
 443
 444/**
 445 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
 446 * @offset_address:     Gigabit Ethernet MAC address offset value.
 447 * @data:               Buffer of the Gigabit Ethernet MAC address value.
 448 */
 449static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 450{
 451        int i;
 452        for (i = 0; i < ETH_ALEN; i++)
 453                pch_phub_read_serial_rom_val(chip, i, &data[i]);
 454}
 455
 456/**
 457 * pch_phub_write_gbe_mac_addr() - Write MAC address
 458 * @offset_address:     Gigabit Ethernet MAC address offset value.
 459 * @data:               Gigabit Ethernet MAC address value.
 460 */
 461static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 462{
 463        int retval;
 464        int i;
 465
 466        if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
 467                retval = pch_phub_gbe_serial_rom_conf(chip);
 468        else    /* ML7223 */
 469                retval = pch_phub_gbe_serial_rom_conf_mp(chip);
 470        if (retval)
 471                return retval;
 472
 473        for (i = 0; i < ETH_ALEN; i++) {
 474                retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
 475                if (retval)
 476                        return retval;
 477        }
 478
 479        return retval;
 480}
 481
 482static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
 483                                 struct bin_attribute *attr, char *buf,
 484                                 loff_t off, size_t count)
 485{
 486        unsigned int rom_signature;
 487        unsigned char rom_length;
 488        unsigned int tmp;
 489        unsigned int addr_offset;
 490        unsigned int orom_size;
 491        int ret;
 492        int err;
 493        ssize_t rom_size;
 494
 495        struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
 496
 497        ret = mutex_lock_interruptible(&pch_phub_mutex);
 498        if (ret) {
 499                err = -ERESTARTSYS;
 500                goto return_err_nomutex;
 501        }
 502
 503        /* Get Rom signature */
 504        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 505        if (!chip->pch_phub_extrom_base_address) {
 506                err = -ENODATA;
 507                goto exrom_map_err;
 508        }
 509
 510        pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
 511                                (unsigned char *)&rom_signature);
 512        rom_signature &= 0xff;
 513        pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
 514                                (unsigned char *)&tmp);
 515        rom_signature |= (tmp & 0xff) << 8;
 516        if (rom_signature == 0xAA55) {
 517                pch_phub_read_serial_rom(chip,
 518                                         chip->pch_opt_rom_start_address + 2,
 519                                         &rom_length);
 520                orom_size = rom_length * 512;
 521                if (orom_size < off) {
 522                        addr_offset = 0;
 523                        goto return_ok;
 524                }
 525                if (orom_size < count) {
 526                        addr_offset = 0;
 527                        goto return_ok;
 528                }
 529
 530                for (addr_offset = 0; addr_offset < count; addr_offset++) {
 531                        pch_phub_read_serial_rom(chip,
 532                            chip->pch_opt_rom_start_address + addr_offset + off,
 533                            &buf[addr_offset]);
 534                }
 535        } else {
 536                err = -ENODATA;
 537                goto return_err;
 538        }
 539return_ok:
 540        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 541        mutex_unlock(&pch_phub_mutex);
 542        return addr_offset;
 543
 544return_err:
 545        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 546exrom_map_err:
 547        mutex_unlock(&pch_phub_mutex);
 548return_err_nomutex:
 549        return err;
 550}
 551
 552static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
 553                                  struct bin_attribute *attr,
 554                                  char *buf, loff_t off, size_t count)
 555{
 556        int err;
 557        unsigned int addr_offset;
 558        int ret;
 559        ssize_t rom_size;
 560        struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
 561
 562        ret = mutex_lock_interruptible(&pch_phub_mutex);
 563        if (ret)
 564                return -ERESTARTSYS;
 565
 566        if (off > PCH_PHUB_OROM_SIZE) {
 567                addr_offset = 0;
 568                goto return_ok;
 569        }
 570        if (count > PCH_PHUB_OROM_SIZE) {
 571                addr_offset = 0;
 572                goto return_ok;
 573        }
 574
 575        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 576        if (!chip->pch_phub_extrom_base_address) {
 577                err = -ENOMEM;
 578                goto exrom_map_err;
 579        }
 580
 581        for (addr_offset = 0; addr_offset < count; addr_offset++) {
 582                if (PCH_PHUB_OROM_SIZE < off + addr_offset)
 583                        goto return_ok;
 584
 585                ret = pch_phub_write_serial_rom(chip,
 586                            chip->pch_opt_rom_start_address + addr_offset + off,
 587                            buf[addr_offset]);
 588                if (ret) {
 589                        err = ret;
 590                        goto return_err;
 591                }
 592        }
 593
 594return_ok:
 595        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 596        mutex_unlock(&pch_phub_mutex);
 597        return addr_offset;
 598
 599return_err:
 600        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 601
 602exrom_map_err:
 603        mutex_unlock(&pch_phub_mutex);
 604        return err;
 605}
 606
 607static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
 608                            char *buf)
 609{
 610        u8 mac[8];
 611        struct pch_phub_reg *chip = dev_get_drvdata(dev);
 612        ssize_t rom_size;
 613
 614        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 615        if (!chip->pch_phub_extrom_base_address)
 616                return -ENOMEM;
 617
 618        pch_phub_read_gbe_mac_addr(chip, mac);
 619        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 620
 621        return sprintf(buf, "%pM\n", mac);
 622}
 623
 624static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
 625                             const char *buf, size_t count)
 626{
 627        u8 mac[ETH_ALEN];
 628        ssize_t rom_size;
 629        struct pch_phub_reg *chip = dev_get_drvdata(dev);
 630        int ret;
 631
 632        if (!mac_pton(buf, mac))
 633                return -EINVAL;
 634
 635        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 636        if (!chip->pch_phub_extrom_base_address)
 637                return -ENOMEM;
 638
 639        ret = pch_phub_write_gbe_mac_addr(chip, mac);
 640        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 641        if (ret)
 642                return ret;
 643
 644        return count;
 645}
 646
 647static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
 648
 649static const struct bin_attribute pch_bin_attr = {
 650        .attr = {
 651                .name = "pch_firmware",
 652                .mode = S_IRUGO | S_IWUSR,
 653        },
 654        .size = PCH_PHUB_OROM_SIZE + 1,
 655        .read = pch_phub_bin_read,
 656        .write = pch_phub_bin_write,
 657};
 658
 659static int pch_phub_probe(struct pci_dev *pdev,
 660                                    const struct pci_device_id *id)
 661{
 662        int ret;
 663        struct pch_phub_reg *chip;
 664
 665        chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
 666        if (chip == NULL)
 667                return -ENOMEM;
 668
 669        ret = pci_enable_device(pdev);
 670        if (ret) {
 671                dev_err(&pdev->dev,
 672                "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
 673                goto err_pci_enable_dev;
 674        }
 675        dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
 676                ret);
 677
 678        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 679        if (ret) {
 680                dev_err(&pdev->dev,
 681                "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
 682                goto err_req_regions;
 683        }
 684        dev_dbg(&pdev->dev, "%s : "
 685                "pci_request_regions returns %d\n", __func__, ret);
 686
 687        chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
 688
 689
 690        if (chip->pch_phub_base_address == NULL) {
 691                dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
 692                ret = -ENOMEM;
 693                goto err_pci_iomap;
 694        }
 695        dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
 696                "in pch_phub_base_address variable is %p\n", __func__,
 697                chip->pch_phub_base_address);
 698
 699        chip->pdev = pdev; /* Save pci device struct */
 700
 701        if (id->driver_data == 1) { /* EG20T PCH */
 702                const char *board_name;
 703                unsigned int prefetch = 0x000affaa;
 704
 705                if (pdev->dev.of_node)
 706                        of_property_read_u32(pdev->dev.of_node,
 707                                                  "intel,eg20t-prefetch",
 708                                                  &prefetch);
 709
 710                ret = sysfs_create_file(&pdev->dev.kobj,
 711                                        &dev_attr_pch_mac.attr);
 712                if (ret)
 713                        goto err_sysfs_create;
 714
 715                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 716                if (ret)
 717                        goto exit_bin_attr;
 718
 719                pch_phub_read_modify_write_reg(chip,
 720                                               (unsigned int)CLKCFG_REG_OFFSET,
 721                                               CLKCFG_CAN_50MHZ,
 722                                               CLKCFG_CANCLK_MASK);
 723
 724                /* quirk for CM-iTC board */
 725                board_name = dmi_get_system_info(DMI_BOARD_NAME);
 726                if (board_name && strstr(board_name, "CM-iTC"))
 727                        pch_phub_read_modify_write_reg(chip,
 728                                                (unsigned int)CLKCFG_REG_OFFSET,
 729                                                CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
 730                                                CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
 731                                                CLKCFG_UART_MASK);
 732
 733                /* set the prefech value */
 734                iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
 735                /* set the interrupt delay value */
 736                iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 737                chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 738                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 739
 740                /* quirk for MIPS Boston platform */
 741                if (pdev->dev.of_node) {
 742                        if (of_machine_is_compatible("img,boston")) {
 743                                pch_phub_read_modify_write_reg(chip,
 744                                        (unsigned int)CLKCFG_REG_OFFSET,
 745                                        CLKCFG_UART_25MHZ,
 746                                        CLKCFG_UART_MASK);
 747                        }
 748                }
 749        } else if (id->driver_data == 2) { /* ML7213 IOH */
 750                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 751                if (ret)
 752                        goto err_sysfs_create;
 753                /* set the prefech value
 754                 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
 755                 * Device4(SDIO #0,1,2):f
 756                 * Device6(SATA 2):f
 757                 * Device8(USB OHCI #0/ USB EHCI #0):a
 758                 */
 759                iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
 760                chip->pch_opt_rom_start_address =\
 761                                                 PCH_PHUB_ROM_START_ADDR_ML7213;
 762        } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
 763                /* set the prefech value
 764                 * Device8(GbE)
 765                 */
 766                iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
 767                /* set the interrupt delay value */
 768                iowrite32(0x25, chip->pch_phub_base_address + 0x140);
 769                chip->pch_opt_rom_start_address =\
 770                                                 PCH_PHUB_ROM_START_ADDR_ML7223;
 771                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 772        } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
 773                ret = sysfs_create_file(&pdev->dev.kobj,
 774                                        &dev_attr_pch_mac.attr);
 775                if (ret)
 776                        goto err_sysfs_create;
 777                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 778                if (ret)
 779                        goto exit_bin_attr;
 780                /* set the prefech value
 781                 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
 782                 * Device4(SDIO #0,1):f
 783                 * Device6(SATA 2):f
 784                 */
 785                iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
 786                chip->pch_opt_rom_start_address =\
 787                                                 PCH_PHUB_ROM_START_ADDR_ML7223;
 788                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 789        } else if (id->driver_data == 5) { /* ML7831 */
 790                ret = sysfs_create_file(&pdev->dev.kobj,
 791                                        &dev_attr_pch_mac.attr);
 792                if (ret)
 793                        goto err_sysfs_create;
 794
 795                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 796                if (ret)
 797                        goto exit_bin_attr;
 798
 799                /* set the prefech value */
 800                iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 801                /* set the interrupt delay value */
 802                iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 803                chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 804                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 805        }
 806
 807        chip->ioh_type = id->driver_data;
 808        pci_set_drvdata(pdev, chip);
 809
 810        return 0;
 811exit_bin_attr:
 812        sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 813
 814err_sysfs_create:
 815        pci_iounmap(pdev, chip->pch_phub_base_address);
 816err_pci_iomap:
 817        pci_release_regions(pdev);
 818err_req_regions:
 819        pci_disable_device(pdev);
 820err_pci_enable_dev:
 821        kfree(chip);
 822        dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
 823        return ret;
 824}
 825
 826static void pch_phub_remove(struct pci_dev *pdev)
 827{
 828        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 829
 830        sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 831        sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 832        pci_iounmap(pdev, chip->pch_phub_base_address);
 833        pci_release_regions(pdev);
 834        pci_disable_device(pdev);
 835        kfree(chip);
 836}
 837
 838#ifdef CONFIG_PM
 839
 840static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
 841{
 842        int ret;
 843
 844        pch_phub_save_reg_conf(pdev);
 845        ret = pci_save_state(pdev);
 846        if (ret) {
 847                dev_err(&pdev->dev,
 848                        " %s -pci_save_state returns %d\n", __func__, ret);
 849                return ret;
 850        }
 851        pci_enable_wake(pdev, PCI_D3hot, 0);
 852        pci_disable_device(pdev);
 853        pci_set_power_state(pdev, pci_choose_state(pdev, state));
 854
 855        return 0;
 856}
 857
 858static int pch_phub_resume(struct pci_dev *pdev)
 859{
 860        int ret;
 861
 862        pci_set_power_state(pdev, PCI_D0);
 863        pci_restore_state(pdev);
 864        ret = pci_enable_device(pdev);
 865        if (ret) {
 866                dev_err(&pdev->dev,
 867                "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
 868                return ret;
 869        }
 870
 871        pci_enable_wake(pdev, PCI_D3hot, 0);
 872        pch_phub_restore_reg_conf(pdev);
 873
 874        return 0;
 875}
 876#else
 877#define pch_phub_suspend NULL
 878#define pch_phub_resume NULL
 879#endif /* CONFIG_PM */
 880
 881static const struct pci_device_id pch_phub_pcidev_id[] = {
 882        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
 883        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
 884        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3,  },
 885        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4,  },
 886        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5,  },
 887        { }
 888};
 889MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
 890
 891static struct pci_driver pch_phub_driver = {
 892        .name = "pch_phub",
 893        .id_table = pch_phub_pcidev_id,
 894        .probe = pch_phub_probe,
 895        .remove = pch_phub_remove,
 896        .suspend = pch_phub_suspend,
 897        .resume = pch_phub_resume
 898};
 899
 900module_pci_driver(pch_phub_driver);
 901
 902MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
 903MODULE_LICENSE("GPL");
 904