1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 2001, 2003 Maciej W. Rozycki 4 * 5 * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for 6 * DECstation/DECsystem 5000/2x0 and DECsystem 5900 and 5900/260 7 * systems. 8 */ 9 10#include <linux/ioport.h> 11#include <linux/mtd/mtd.h> 12 13/* 14 * Addresses are decoded as follows: 15 * 16 * 0x000000 - 0x3fffff SRAM 17 * 0x400000 - 0x7fffff CSR 18 * 19 * Within the SRAM area the following ranges are forced by the system 20 * firmware: 21 * 22 * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot 23 * 0x000400 - ENDofRAM storage area, available to operating systems 24 * 25 * but we can't really use the available area right from 0x000400 as 26 * the first word is used by the firmware as a status flag passed 27 * from an operating system. If anything but the valid data magic 28 * ID value is found, the firmware considers the SRAM clean, i.e. 29 * containing no valid data, and disables the battery resulting in 30 * data being erased as soon as power is switched off. So the choice 31 * for the start address of the user-available is 0x001000 which is 32 * nicely page aligned. The area between 0x000404 and 0x000fff may 33 * be used by the driver for own needs. 34 * 35 * The diagnostic area defines two status words to be read by an 36 * operating system, a magic ID to distinguish a MS02-NV board from 37 * anything else and a status information providing results of tests 38 * as well as the size of SRAM available, which can be 1MiB or 2MiB 39 * (that's what the firmware handles; no idea if 2MiB modules ever 40 * existed). 41 * 42 * The firmware only handles the MS02-NV board if installed in the 43 * last (15th) slot, so for any other location the status information 44 * stored in the SRAM cannot be relied upon. But from the hardware 45 * point of view there is no problem using up to 14 such boards in a 46 * system -- only the 1st slot needs to be filled with a DRAM module. 47 * The MS02-NV board is ECC-protected, like other MS02 memory boards. 48 * 49 * The state of the battery as provided by the CSR is reflected on 50 * the two onboard LEDs. When facing the battery side of the board, 51 * with the LEDs at the top left and the battery at the bottom right 52 * (i.e. looking from the back side of the system box), their meaning 53 * is as follows (the system has to be powered on): 54 * 55 * left LED battery disable status: lit = enabled 56 * right LED battery condition status: lit = OK 57 */ 58 59/* MS02-NV iomem register offsets. */ 60#define MS02NV_CSR 0x400000 /* control & status register */ 61 62/* MS02-NV CSR status bits. */ 63#define MS02NV_CSR_BATT_OK 0x01 /* battery OK */ 64#define MS02NV_CSR_BATT_OFF 0x02 /* battery disabled */ 65 66 67/* MS02-NV memory offsets. */ 68#define MS02NV_DIAG 0x0003f8 /* diagnostic status */ 69#define MS02NV_MAGIC 0x0003fc /* MS02-NV magic ID */ 70#define MS02NV_VALID 0x000400 /* valid data magic ID */ 71#define MS02NV_RAM 0x001000 /* user-exposed RAM start */ 72 73/* MS02-NV diagnostic status bits. */ 74#define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */ 75#define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */ 76#define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */ 77#define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */ 78#define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */ 79#define MS02NV_DIAG_SIZE_SHIFT 0x10 /* SRAM size shift (left) */ 80 81/* MS02-NV general constants. */ 82#define MS02NV_ID 0x03021966 /* MS02-NV magic ID value */ 83#define MS02NV_VALID_ID 0xbd100248 /* valid data magic ID value */ 84#define MS02NV_SLOT_SIZE 0x800000 /* size of the address space 85 decoded by the module */ 86 87 88typedef volatile u32 ms02nv_uint; 89 90struct ms02nv_private { 91 struct mtd_info *next; 92 struct { 93 struct resource *module; 94 struct resource *diag_ram; 95 struct resource *user_ram; 96 struct resource *csr; 97 } resource; 98 u_char *addr; 99 size_t size; 100 u_char *uaddr; 101}; 102