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12#include <linux/netdevice.h>
13#include <linux/can.h>
14#include <linux/can/dev.h>
15#include <linux/can/error.h>
16#include <linux/can/led.h>
17#include <linux/can/rx-offload.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/mfd/syscon.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/consumer.h>
28#include <linux/regmap.h>
29
30#define DRV_NAME "flexcan"
31
32
33#define FLEXCAN_NAPI_WEIGHT (8 + 2)
34
35
36#define FLEXCAN_MCR_MDIS BIT(31)
37#define FLEXCAN_MCR_FRZ BIT(30)
38#define FLEXCAN_MCR_FEN BIT(29)
39#define FLEXCAN_MCR_HALT BIT(28)
40#define FLEXCAN_MCR_NOT_RDY BIT(27)
41#define FLEXCAN_MCR_WAK_MSK BIT(26)
42#define FLEXCAN_MCR_SOFTRST BIT(25)
43#define FLEXCAN_MCR_FRZ_ACK BIT(24)
44#define FLEXCAN_MCR_SUPV BIT(23)
45#define FLEXCAN_MCR_SLF_WAK BIT(22)
46#define FLEXCAN_MCR_WRN_EN BIT(21)
47#define FLEXCAN_MCR_LPM_ACK BIT(20)
48#define FLEXCAN_MCR_WAK_SRC BIT(19)
49#define FLEXCAN_MCR_DOZE BIT(18)
50#define FLEXCAN_MCR_SRX_DIS BIT(17)
51#define FLEXCAN_MCR_IRMQ BIT(16)
52#define FLEXCAN_MCR_LPRIO_EN BIT(13)
53#define FLEXCAN_MCR_AEN BIT(12)
54
55#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
56#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
57#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
58#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
59#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
60
61
62#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
63#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
64#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
65#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
66#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
67#define FLEXCAN_CTRL_ERR_MSK BIT(14)
68#define FLEXCAN_CTRL_CLK_SRC BIT(13)
69#define FLEXCAN_CTRL_LPB BIT(12)
70#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
71#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
72#define FLEXCAN_CTRL_SMP BIT(7)
73#define FLEXCAN_CTRL_BOFF_REC BIT(6)
74#define FLEXCAN_CTRL_TSYN BIT(5)
75#define FLEXCAN_CTRL_LBUF BIT(4)
76#define FLEXCAN_CTRL_LOM BIT(3)
77#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
78#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
79#define FLEXCAN_CTRL_ERR_STATE \
80 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
81 FLEXCAN_CTRL_BOFF_MSK)
82#define FLEXCAN_CTRL_ERR_ALL \
83 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
84
85
86#define FLEXCAN_CTRL2_ECRWRE BIT(29)
87#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
88#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
89#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
90#define FLEXCAN_CTRL2_MRP BIT(18)
91#define FLEXCAN_CTRL2_RRS BIT(17)
92#define FLEXCAN_CTRL2_EACEN BIT(16)
93
94
95#define FLEXCAN_MECR_ECRWRDIS BIT(31)
96#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
97#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
98#define FLEXCAN_MECR_CEI_MSK BIT(16)
99#define FLEXCAN_MECR_HAERRIE BIT(15)
100#define FLEXCAN_MECR_FAERRIE BIT(14)
101#define FLEXCAN_MECR_EXTERRIE BIT(13)
102#define FLEXCAN_MECR_RERRDIS BIT(9)
103#define FLEXCAN_MECR_ECCDIS BIT(8)
104#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
105
106
107#define FLEXCAN_ESR_TWRN_INT BIT(17)
108#define FLEXCAN_ESR_RWRN_INT BIT(16)
109#define FLEXCAN_ESR_BIT1_ERR BIT(15)
110#define FLEXCAN_ESR_BIT0_ERR BIT(14)
111#define FLEXCAN_ESR_ACK_ERR BIT(13)
112#define FLEXCAN_ESR_CRC_ERR BIT(12)
113#define FLEXCAN_ESR_FRM_ERR BIT(11)
114#define FLEXCAN_ESR_STF_ERR BIT(10)
115#define FLEXCAN_ESR_TX_WRN BIT(9)
116#define FLEXCAN_ESR_RX_WRN BIT(8)
117#define FLEXCAN_ESR_IDLE BIT(7)
118#define FLEXCAN_ESR_TXRX BIT(6)
119#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
120#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
121#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
122#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
123#define FLEXCAN_ESR_BOFF_INT BIT(2)
124#define FLEXCAN_ESR_ERR_INT BIT(1)
125#define FLEXCAN_ESR_WAK_INT BIT(0)
126#define FLEXCAN_ESR_ERR_BUS \
127 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
128 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
129 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
130#define FLEXCAN_ESR_ERR_STATE \
131 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
132#define FLEXCAN_ESR_ERR_ALL \
133 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
134#define FLEXCAN_ESR_ALL_INT \
135 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
136 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
137 FLEXCAN_ESR_WAK_INT)
138
139
140
141#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
142#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
143#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
144#define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
145#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
146#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
147#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
148
149
150#define FLEXCAN_MB_CODE_MASK (0xf << 24)
151#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
152#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
153#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
154#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
155#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
156#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
157
158#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
159#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
160#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
161#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
162
163#define FLEXCAN_MB_CNT_SRR BIT(22)
164#define FLEXCAN_MB_CNT_IDE BIT(21)
165#define FLEXCAN_MB_CNT_RTR BIT(20)
166#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
167#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
168
169#define FLEXCAN_TIMEOUT_US (250)
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185
186#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
187#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
188#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
189#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
190#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
191#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
192#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
193#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)
194
195
196struct flexcan_mb {
197 u32 can_ctrl;
198 u32 can_id;
199 u32 data[];
200};
201
202
203struct flexcan_regs {
204 u32 mcr;
205 u32 ctrl;
206 u32 timer;
207 u32 _reserved1;
208 u32 rxgmask;
209 u32 rx14mask;
210 u32 rx15mask;
211 u32 ecr;
212 u32 esr;
213 u32 imask2;
214 u32 imask1;
215 u32 iflag2;
216 u32 iflag1;
217 union {
218 u32 gfwr_mx28;
219 u32 ctrl2;
220 };
221 u32 esr2;
222 u32 imeur;
223 u32 lrfr;
224 u32 crcr;
225 u32 rxfgmask;
226 u32 rxfir;
227 u32 _reserved3[12];
228 u8 mb[2][512];
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238
239 u32 _reserved4[256];
240 u32 rximr[64];
241 u32 _reserved5[24];
242 u32 gfwr_mx6;
243 u32 _reserved6[63];
244 u32 mecr;
245 u32 erriar;
246 u32 erridpr;
247 u32 errippr;
248 u32 rerrar;
249 u32 rerrdr;
250 u32 rerrsynr;
251 u32 errsr;
252};
253
254struct flexcan_devtype_data {
255 u32 quirks;
256};
257
258struct flexcan_stop_mode {
259 struct regmap *gpr;
260 u8 req_gpr;
261 u8 req_bit;
262 u8 ack_gpr;
263 u8 ack_bit;
264};
265
266struct flexcan_priv {
267 struct can_priv can;
268 struct can_rx_offload offload;
269
270 struct flexcan_regs __iomem *regs;
271 struct flexcan_mb __iomem *tx_mb;
272 struct flexcan_mb __iomem *tx_mb_reserved;
273 u8 tx_mb_idx;
274 u8 mb_count;
275 u8 mb_size;
276 u32 reg_ctrl_default;
277 u32 reg_imask1_default;
278 u32 reg_imask2_default;
279
280 struct clk *clk_ipg;
281 struct clk *clk_per;
282 const struct flexcan_devtype_data *devtype_data;
283 struct regulator *reg_xceiver;
284 struct flexcan_stop_mode stm;
285
286
287 u32 (*read)(void __iomem *addr);
288 void (*write)(u32 val, void __iomem *addr);
289};
290
291static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
292 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
293 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
294 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
295};
296
297static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
298 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
299 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
300};
301
302static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
303 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
304};
305
306static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
307 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
308 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
309 FLEXCAN_QUIRK_SETUP_STOP_MODE,
310};
311
312static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
313 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
314 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
315 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
316};
317
318static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
319 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
320 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
321 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
322};
323
324static const struct can_bittiming_const flexcan_bittiming_const = {
325 .name = DRV_NAME,
326 .tseg1_min = 4,
327 .tseg1_max = 16,
328 .tseg2_min = 2,
329 .tseg2_max = 8,
330 .sjw_max = 4,
331 .brp_min = 1,
332 .brp_max = 256,
333 .brp_inc = 1,
334};
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347
348
349static inline u32 flexcan_read_be(void __iomem *addr)
350{
351 return ioread32be(addr);
352}
353
354static inline void flexcan_write_be(u32 val, void __iomem *addr)
355{
356 iowrite32be(val, addr);
357}
358
359static inline u32 flexcan_read_le(void __iomem *addr)
360{
361 return ioread32(addr);
362}
363
364static inline void flexcan_write_le(u32 val, void __iomem *addr)
365{
366 iowrite32(val, addr);
367}
368
369static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
370 u8 mb_index)
371{
372 u8 bank_size;
373 bool bank;
374
375 if (WARN_ON(mb_index >= priv->mb_count))
376 return NULL;
377
378 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
379
380 bank = mb_index >= bank_size;
381 if (bank)
382 mb_index -= bank_size;
383
384 return (struct flexcan_mb __iomem *)
385 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
386}
387
388static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
389{
390 struct flexcan_regs __iomem *regs = priv->regs;
391 u32 reg_mcr;
392
393 reg_mcr = priv->read(®s->mcr);
394
395 if (enable)
396 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
397 else
398 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
399
400 priv->write(reg_mcr, ®s->mcr);
401}
402
403static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
404{
405 struct flexcan_regs __iomem *regs = priv->regs;
406 unsigned int ackval;
407 u32 reg_mcr;
408
409 reg_mcr = priv->read(®s->mcr);
410 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
411 priv->write(reg_mcr, ®s->mcr);
412
413
414 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
415 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
416
417
418 if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
419 ackval, ackval & (1 << priv->stm.ack_bit),
420 0, FLEXCAN_TIMEOUT_US))
421 return -ETIMEDOUT;
422
423 return 0;
424}
425
426static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
427{
428 struct flexcan_regs __iomem *regs = priv->regs;
429 unsigned int ackval;
430 u32 reg_mcr;
431
432
433 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
434 1 << priv->stm.req_bit, 0);
435
436
437 if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
438 ackval, !(ackval & (1 << priv->stm.ack_bit)),
439 0, FLEXCAN_TIMEOUT_US))
440 return -ETIMEDOUT;
441
442 reg_mcr = priv->read(®s->mcr);
443 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
444 priv->write(reg_mcr, ®s->mcr);
445
446 return 0;
447}
448
449static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
450{
451 struct flexcan_regs __iomem *regs = priv->regs;
452 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
453
454 priv->write(reg_ctrl, ®s->ctrl);
455}
456
457static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
458{
459 struct flexcan_regs __iomem *regs = priv->regs;
460 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
461
462 priv->write(reg_ctrl, ®s->ctrl);
463}
464
465static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
466{
467 if (!priv->reg_xceiver)
468 return 0;
469
470 return regulator_enable(priv->reg_xceiver);
471}
472
473static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
474{
475 if (!priv->reg_xceiver)
476 return 0;
477
478 return regulator_disable(priv->reg_xceiver);
479}
480
481static int flexcan_chip_enable(struct flexcan_priv *priv)
482{
483 struct flexcan_regs __iomem *regs = priv->regs;
484 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
485 u32 reg;
486
487 reg = priv->read(®s->mcr);
488 reg &= ~FLEXCAN_MCR_MDIS;
489 priv->write(reg, ®s->mcr);
490
491 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
492 udelay(10);
493
494 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
495 return -ETIMEDOUT;
496
497 return 0;
498}
499
500static int flexcan_chip_disable(struct flexcan_priv *priv)
501{
502 struct flexcan_regs __iomem *regs = priv->regs;
503 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
504 u32 reg;
505
506 reg = priv->read(®s->mcr);
507 reg |= FLEXCAN_MCR_MDIS;
508 priv->write(reg, ®s->mcr);
509
510 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
511 udelay(10);
512
513 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
514 return -ETIMEDOUT;
515
516 return 0;
517}
518
519static int flexcan_chip_freeze(struct flexcan_priv *priv)
520{
521 struct flexcan_regs __iomem *regs = priv->regs;
522 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
523 u32 reg;
524
525 reg = priv->read(®s->mcr);
526 reg |= FLEXCAN_MCR_HALT;
527 priv->write(reg, ®s->mcr);
528
529 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
530 udelay(100);
531
532 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
533 return -ETIMEDOUT;
534
535 return 0;
536}
537
538static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
539{
540 struct flexcan_regs __iomem *regs = priv->regs;
541 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
542 u32 reg;
543
544 reg = priv->read(®s->mcr);
545 reg &= ~FLEXCAN_MCR_HALT;
546 priv->write(reg, ®s->mcr);
547
548 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
549 udelay(10);
550
551 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
552 return -ETIMEDOUT;
553
554 return 0;
555}
556
557static int flexcan_chip_softreset(struct flexcan_priv *priv)
558{
559 struct flexcan_regs __iomem *regs = priv->regs;
560 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
561
562 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
563 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
564 udelay(10);
565
566 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
567 return -ETIMEDOUT;
568
569 return 0;
570}
571
572static int __flexcan_get_berr_counter(const struct net_device *dev,
573 struct can_berr_counter *bec)
574{
575 const struct flexcan_priv *priv = netdev_priv(dev);
576 struct flexcan_regs __iomem *regs = priv->regs;
577 u32 reg = priv->read(®s->ecr);
578
579 bec->txerr = (reg >> 0) & 0xff;
580 bec->rxerr = (reg >> 8) & 0xff;
581
582 return 0;
583}
584
585static int flexcan_get_berr_counter(const struct net_device *dev,
586 struct can_berr_counter *bec)
587{
588 const struct flexcan_priv *priv = netdev_priv(dev);
589 int err;
590
591 err = clk_prepare_enable(priv->clk_ipg);
592 if (err)
593 return err;
594
595 err = clk_prepare_enable(priv->clk_per);
596 if (err)
597 goto out_disable_ipg;
598
599 err = __flexcan_get_berr_counter(dev, bec);
600
601 clk_disable_unprepare(priv->clk_per);
602 out_disable_ipg:
603 clk_disable_unprepare(priv->clk_ipg);
604
605 return err;
606}
607
608static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
609{
610 const struct flexcan_priv *priv = netdev_priv(dev);
611 struct can_frame *cf = (struct can_frame *)skb->data;
612 u32 can_id;
613 u32 data;
614 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
615 int i;
616
617 if (can_dropped_invalid_skb(dev, skb))
618 return NETDEV_TX_OK;
619
620 netif_stop_queue(dev);
621
622 if (cf->can_id & CAN_EFF_FLAG) {
623 can_id = cf->can_id & CAN_EFF_MASK;
624 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
625 } else {
626 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
627 }
628
629 if (cf->can_id & CAN_RTR_FLAG)
630 ctrl |= FLEXCAN_MB_CNT_RTR;
631
632 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
633 data = be32_to_cpup((__be32 *)&cf->data[i]);
634 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
635 }
636
637 can_put_echo_skb(skb, dev, 0);
638
639 priv->write(can_id, &priv->tx_mb->can_id);
640 priv->write(ctrl, &priv->tx_mb->can_ctrl);
641
642
643
644
645 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
646 &priv->tx_mb_reserved->can_ctrl);
647 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
648 &priv->tx_mb_reserved->can_ctrl);
649
650 return NETDEV_TX_OK;
651}
652
653static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
654{
655 struct flexcan_priv *priv = netdev_priv(dev);
656 struct flexcan_regs __iomem *regs = priv->regs;
657 struct sk_buff *skb;
658 struct can_frame *cf;
659 bool rx_errors = false, tx_errors = false;
660 u32 timestamp;
661
662 timestamp = priv->read(®s->timer) << 16;
663
664 skb = alloc_can_err_skb(dev, &cf);
665 if (unlikely(!skb))
666 return;
667
668 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
669
670 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
671 netdev_dbg(dev, "BIT1_ERR irq\n");
672 cf->data[2] |= CAN_ERR_PROT_BIT1;
673 tx_errors = true;
674 }
675 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
676 netdev_dbg(dev, "BIT0_ERR irq\n");
677 cf->data[2] |= CAN_ERR_PROT_BIT0;
678 tx_errors = true;
679 }
680 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
681 netdev_dbg(dev, "ACK_ERR irq\n");
682 cf->can_id |= CAN_ERR_ACK;
683 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
684 tx_errors = true;
685 }
686 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
687 netdev_dbg(dev, "CRC_ERR irq\n");
688 cf->data[2] |= CAN_ERR_PROT_BIT;
689 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
690 rx_errors = true;
691 }
692 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
693 netdev_dbg(dev, "FRM_ERR irq\n");
694 cf->data[2] |= CAN_ERR_PROT_FORM;
695 rx_errors = true;
696 }
697 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
698 netdev_dbg(dev, "STF_ERR irq\n");
699 cf->data[2] |= CAN_ERR_PROT_STUFF;
700 rx_errors = true;
701 }
702
703 priv->can.can_stats.bus_error++;
704 if (rx_errors)
705 dev->stats.rx_errors++;
706 if (tx_errors)
707 dev->stats.tx_errors++;
708
709 can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
710}
711
712static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
713{
714 struct flexcan_priv *priv = netdev_priv(dev);
715 struct flexcan_regs __iomem *regs = priv->regs;
716 struct sk_buff *skb;
717 struct can_frame *cf;
718 enum can_state new_state, rx_state, tx_state;
719 int flt;
720 struct can_berr_counter bec;
721 u32 timestamp;
722
723 timestamp = priv->read(®s->timer) << 16;
724
725 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
726 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
727 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
728 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
729 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
730 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
731 new_state = max(tx_state, rx_state);
732 } else {
733 __flexcan_get_berr_counter(dev, &bec);
734 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
735 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
736 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
737 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
738 }
739
740
741 if (likely(new_state == priv->can.state))
742 return;
743
744 skb = alloc_can_err_skb(dev, &cf);
745 if (unlikely(!skb))
746 return;
747
748 can_change_state(dev, cf, tx_state, rx_state);
749
750 if (unlikely(new_state == CAN_STATE_BUS_OFF))
751 can_bus_off(dev);
752
753 can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
754}
755
756static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
757{
758 return container_of(offload, struct flexcan_priv, offload);
759}
760
761static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
762 struct can_frame *cf,
763 u32 *timestamp, unsigned int n)
764{
765 struct flexcan_priv *priv = rx_offload_to_priv(offload);
766 struct flexcan_regs __iomem *regs = priv->regs;
767 struct flexcan_mb __iomem *mb;
768 u32 reg_ctrl, reg_id, reg_iflag1;
769 int i;
770
771 mb = flexcan_get_mb(priv, n);
772
773 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
774 u32 code;
775
776 do {
777 reg_ctrl = priv->read(&mb->can_ctrl);
778 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
779
780
781 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
782 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
783 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
784 return 0;
785
786 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
787
788 offload->dev->stats.rx_over_errors++;
789 offload->dev->stats.rx_errors++;
790 }
791 } else {
792 reg_iflag1 = priv->read(®s->iflag1);
793 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
794 return 0;
795
796 reg_ctrl = priv->read(&mb->can_ctrl);
797 }
798
799
800 *timestamp = reg_ctrl << 16;
801
802 reg_id = priv->read(&mb->can_id);
803 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
804 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
805 else
806 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
807
808 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
809 cf->can_id |= CAN_RTR_FLAG;
810 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
811
812 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
813 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
814 *(__be32 *)(cf->data + i) = data;
815 }
816
817
818 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
819
820 if (n < 32)
821 priv->write(BIT(n), ®s->iflag1);
822 else
823 priv->write(BIT(n - 32), ®s->iflag2);
824 } else {
825 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
826 }
827
828
829
830
831
832 priv->read(®s->timer);
833
834 return 1;
835}
836
837
838static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
839{
840 struct flexcan_regs __iomem *regs = priv->regs;
841 u32 iflag1, iflag2;
842
843 iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default &
844 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
845 iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default;
846
847 return (u64)iflag2 << 32 | iflag1;
848}
849
850static irqreturn_t flexcan_irq(int irq, void *dev_id)
851{
852 struct net_device *dev = dev_id;
853 struct net_device_stats *stats = &dev->stats;
854 struct flexcan_priv *priv = netdev_priv(dev);
855 struct flexcan_regs __iomem *regs = priv->regs;
856 irqreturn_t handled = IRQ_NONE;
857 u32 reg_iflag2, reg_esr;
858 enum can_state last_state = priv->can.state;
859
860
861 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
862 u64 reg_iflag;
863 int ret;
864
865 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
866 handled = IRQ_HANDLED;
867 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
868 reg_iflag);
869 if (!ret)
870 break;
871 }
872 } else {
873 u32 reg_iflag1;
874
875 reg_iflag1 = priv->read(®s->iflag1);
876 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
877 handled = IRQ_HANDLED;
878 can_rx_offload_irq_offload_fifo(&priv->offload);
879 }
880
881
882 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
883 handled = IRQ_HANDLED;
884 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
885 ®s->iflag1);
886 dev->stats.rx_over_errors++;
887 dev->stats.rx_errors++;
888 }
889 }
890
891 reg_iflag2 = priv->read(®s->iflag2);
892
893
894 if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
895 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
896
897 handled = IRQ_HANDLED;
898 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
899 0, reg_ctrl << 16);
900 stats->tx_packets++;
901 can_led_event(dev, CAN_LED_EVENT_TX);
902
903
904 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
905 &priv->tx_mb->can_ctrl);
906 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag2);
907 netif_wake_queue(dev);
908 }
909
910 reg_esr = priv->read(®s->esr);
911
912
913 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
914 handled = IRQ_HANDLED;
915 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
916 }
917
918
919 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
920 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
921 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
922 flexcan_irq_state(dev, reg_esr);
923
924
925 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
926 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
927 flexcan_irq_bus_err(dev, reg_esr);
928
929
930
931
932
933
934
935
936
937
938
939
940
941 if ((last_state != priv->can.state) &&
942 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
943 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
944 switch (priv->can.state) {
945 case CAN_STATE_ERROR_ACTIVE:
946 if (priv->devtype_data->quirks &
947 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
948 flexcan_error_irq_enable(priv);
949 else
950 flexcan_error_irq_disable(priv);
951 break;
952
953 case CAN_STATE_ERROR_WARNING:
954 flexcan_error_irq_enable(priv);
955 break;
956
957 case CAN_STATE_ERROR_PASSIVE:
958 case CAN_STATE_BUS_OFF:
959 flexcan_error_irq_disable(priv);
960 break;
961
962 default:
963 break;
964 }
965 }
966
967 return handled;
968}
969
970static void flexcan_set_bittiming(struct net_device *dev)
971{
972 const struct flexcan_priv *priv = netdev_priv(dev);
973 const struct can_bittiming *bt = &priv->can.bittiming;
974 struct flexcan_regs __iomem *regs = priv->regs;
975 u32 reg;
976
977 reg = priv->read(®s->ctrl);
978 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
979 FLEXCAN_CTRL_RJW(0x3) |
980 FLEXCAN_CTRL_PSEG1(0x7) |
981 FLEXCAN_CTRL_PSEG2(0x7) |
982 FLEXCAN_CTRL_PROPSEG(0x7) |
983 FLEXCAN_CTRL_LPB |
984 FLEXCAN_CTRL_SMP |
985 FLEXCAN_CTRL_LOM);
986
987 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
988 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
989 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
990 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
991 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
992
993 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
994 reg |= FLEXCAN_CTRL_LPB;
995 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
996 reg |= FLEXCAN_CTRL_LOM;
997 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
998 reg |= FLEXCAN_CTRL_SMP;
999
1000 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1001 priv->write(reg, ®s->ctrl);
1002
1003
1004 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1005 priv->read(®s->mcr), priv->read(®s->ctrl));
1006}
1007
1008
1009
1010
1011
1012
1013static int flexcan_chip_start(struct net_device *dev)
1014{
1015 struct flexcan_priv *priv = netdev_priv(dev);
1016 struct flexcan_regs __iomem *regs = priv->regs;
1017 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1018 int err, i;
1019 struct flexcan_mb __iomem *mb;
1020
1021
1022 err = flexcan_chip_enable(priv);
1023 if (err)
1024 return err;
1025
1026
1027 err = flexcan_chip_softreset(priv);
1028 if (err)
1029 goto out_chip_disable;
1030
1031 flexcan_set_bittiming(dev);
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043 reg_mcr = priv->read(®s->mcr);
1044 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1045 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1046 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1047 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1048
1049
1050
1051
1052
1053
1054
1055 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1056 reg_mcr &= ~FLEXCAN_MCR_FEN;
1057 else
1058 reg_mcr |= FLEXCAN_MCR_FEN;
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1073 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1074 else
1075 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1076
1077 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1078 priv->write(reg_mcr, ®s->mcr);
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091 reg_ctrl = priv->read(®s->ctrl);
1092 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1093 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1094 FLEXCAN_CTRL_ERR_STATE;
1095
1096
1097
1098
1099
1100 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1101 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1102 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1103 else
1104 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1105
1106
1107 priv->reg_ctrl_default = reg_ctrl;
1108
1109 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1110 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1111 priv->write(reg_ctrl, ®s->ctrl);
1112
1113 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1114 reg_ctrl2 = priv->read(®s->ctrl2);
1115 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1116 priv->write(reg_ctrl2, ®s->ctrl2);
1117 }
1118
1119 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1120 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1121 mb = flexcan_get_mb(priv, i);
1122 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1123 &mb->can_ctrl);
1124 }
1125 } else {
1126
1127 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1128 mb = flexcan_get_mb(priv, i);
1129 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1130 &mb->can_ctrl);
1131 }
1132 }
1133
1134
1135 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1136 &priv->tx_mb_reserved->can_ctrl);
1137
1138
1139 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1140 &priv->tx_mb->can_ctrl);
1141
1142
1143 priv->write(0x0, ®s->rxgmask);
1144 priv->write(0x0, ®s->rx14mask);
1145 priv->write(0x0, ®s->rx15mask);
1146
1147 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1148 priv->write(0x0, ®s->rxfgmask);
1149
1150
1151 for (i = 0; i < priv->mb_count; i++)
1152 priv->write(0, ®s->rximr[i]);
1153
1154
1155
1156
1157
1158
1159
1160 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1161
1162
1163
1164
1165 reg_ctrl2 = priv->read(®s->ctrl2);
1166 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1167 priv->write(reg_ctrl2, ®s->ctrl2);
1168
1169 reg_mecr = priv->read(®s->mecr);
1170 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1171 priv->write(reg_mecr, ®s->mecr);
1172 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1173 FLEXCAN_MECR_FANCEI_MSK);
1174 priv->write(reg_mecr, ®s->mecr);
1175 }
1176
1177 err = flexcan_transceiver_enable(priv);
1178 if (err)
1179 goto out_chip_disable;
1180
1181
1182 err = flexcan_chip_unfreeze(priv);
1183 if (err)
1184 goto out_transceiver_disable;
1185
1186 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1187
1188
1189 disable_irq(dev->irq);
1190 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1191 priv->write(priv->reg_imask1_default, ®s->imask1);
1192 priv->write(priv->reg_imask2_default, ®s->imask2);
1193 enable_irq(dev->irq);
1194
1195
1196 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1197 priv->read(®s->mcr), priv->read(®s->ctrl));
1198
1199 return 0;
1200
1201 out_transceiver_disable:
1202 flexcan_transceiver_disable(priv);
1203 out_chip_disable:
1204 flexcan_chip_disable(priv);
1205 return err;
1206}
1207
1208
1209
1210
1211
1212static void flexcan_chip_stop(struct net_device *dev)
1213{
1214 struct flexcan_priv *priv = netdev_priv(dev);
1215 struct flexcan_regs __iomem *regs = priv->regs;
1216
1217
1218 flexcan_chip_freeze(priv);
1219 flexcan_chip_disable(priv);
1220
1221
1222 priv->write(0, ®s->imask2);
1223 priv->write(0, ®s->imask1);
1224 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1225 ®s->ctrl);
1226
1227 flexcan_transceiver_disable(priv);
1228 priv->can.state = CAN_STATE_STOPPED;
1229}
1230
1231static int flexcan_open(struct net_device *dev)
1232{
1233 struct flexcan_priv *priv = netdev_priv(dev);
1234 int err;
1235
1236 err = clk_prepare_enable(priv->clk_ipg);
1237 if (err)
1238 return err;
1239
1240 err = clk_prepare_enable(priv->clk_per);
1241 if (err)
1242 goto out_disable_ipg;
1243
1244 err = open_candev(dev);
1245 if (err)
1246 goto out_disable_per;
1247
1248 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1249 if (err)
1250 goto out_close;
1251
1252 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1253 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1254 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1255
1256 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1257 priv->tx_mb_reserved =
1258 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1259 else
1260 priv->tx_mb_reserved =
1261 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1262 priv->tx_mb_idx = priv->mb_count - 1;
1263 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1264
1265 priv->reg_imask1_default = 0;
1266 priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1267
1268 priv->offload.mailbox_read = flexcan_mailbox_read;
1269
1270 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1271 u64 imask;
1272
1273 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1274 priv->offload.mb_last = priv->mb_count - 2;
1275
1276 imask = GENMASK_ULL(priv->offload.mb_last,
1277 priv->offload.mb_first);
1278 priv->reg_imask1_default |= imask;
1279 priv->reg_imask2_default |= imask >> 32;
1280
1281 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1282 } else {
1283 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1284 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1285 err = can_rx_offload_add_fifo(dev, &priv->offload,
1286 FLEXCAN_NAPI_WEIGHT);
1287 }
1288 if (err)
1289 goto out_free_irq;
1290
1291
1292 err = flexcan_chip_start(dev);
1293 if (err)
1294 goto out_offload_del;
1295
1296 can_led_event(dev, CAN_LED_EVENT_OPEN);
1297
1298 can_rx_offload_enable(&priv->offload);
1299 netif_start_queue(dev);
1300
1301 return 0;
1302
1303 out_offload_del:
1304 can_rx_offload_del(&priv->offload);
1305 out_free_irq:
1306 free_irq(dev->irq, dev);
1307 out_close:
1308 close_candev(dev);
1309 out_disable_per:
1310 clk_disable_unprepare(priv->clk_per);
1311 out_disable_ipg:
1312 clk_disable_unprepare(priv->clk_ipg);
1313
1314 return err;
1315}
1316
1317static int flexcan_close(struct net_device *dev)
1318{
1319 struct flexcan_priv *priv = netdev_priv(dev);
1320
1321 netif_stop_queue(dev);
1322 can_rx_offload_disable(&priv->offload);
1323 flexcan_chip_stop(dev);
1324
1325 can_rx_offload_del(&priv->offload);
1326 free_irq(dev->irq, dev);
1327 clk_disable_unprepare(priv->clk_per);
1328 clk_disable_unprepare(priv->clk_ipg);
1329
1330 close_candev(dev);
1331
1332 can_led_event(dev, CAN_LED_EVENT_STOP);
1333
1334 return 0;
1335}
1336
1337static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1338{
1339 int err;
1340
1341 switch (mode) {
1342 case CAN_MODE_START:
1343 err = flexcan_chip_start(dev);
1344 if (err)
1345 return err;
1346
1347 netif_wake_queue(dev);
1348 break;
1349
1350 default:
1351 return -EOPNOTSUPP;
1352 }
1353
1354 return 0;
1355}
1356
1357static const struct net_device_ops flexcan_netdev_ops = {
1358 .ndo_open = flexcan_open,
1359 .ndo_stop = flexcan_close,
1360 .ndo_start_xmit = flexcan_start_xmit,
1361 .ndo_change_mtu = can_change_mtu,
1362};
1363
1364static int register_flexcandev(struct net_device *dev)
1365{
1366 struct flexcan_priv *priv = netdev_priv(dev);
1367 struct flexcan_regs __iomem *regs = priv->regs;
1368 u32 reg, err;
1369
1370 err = clk_prepare_enable(priv->clk_ipg);
1371 if (err)
1372 return err;
1373
1374 err = clk_prepare_enable(priv->clk_per);
1375 if (err)
1376 goto out_disable_ipg;
1377
1378
1379 err = flexcan_chip_disable(priv);
1380 if (err)
1381 goto out_disable_per;
1382 reg = priv->read(®s->ctrl);
1383 reg |= FLEXCAN_CTRL_CLK_SRC;
1384 priv->write(reg, ®s->ctrl);
1385
1386 err = flexcan_chip_enable(priv);
1387 if (err)
1388 goto out_chip_disable;
1389
1390
1391 reg = priv->read(®s->mcr);
1392 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1393 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1394 priv->write(reg, ®s->mcr);
1395
1396
1397
1398
1399
1400
1401 reg = priv->read(®s->mcr);
1402 if (!(reg & FLEXCAN_MCR_FEN)) {
1403 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1404 err = -ENODEV;
1405 goto out_chip_disable;
1406 }
1407
1408 err = register_candev(dev);
1409
1410
1411 out_chip_disable:
1412 flexcan_chip_disable(priv);
1413 out_disable_per:
1414 clk_disable_unprepare(priv->clk_per);
1415 out_disable_ipg:
1416 clk_disable_unprepare(priv->clk_ipg);
1417
1418 return err;
1419}
1420
1421static void unregister_flexcandev(struct net_device *dev)
1422{
1423 unregister_candev(dev);
1424}
1425
1426static int flexcan_setup_stop_mode(struct platform_device *pdev)
1427{
1428 struct net_device *dev = platform_get_drvdata(pdev);
1429 struct device_node *np = pdev->dev.of_node;
1430 struct device_node *gpr_np;
1431 struct flexcan_priv *priv;
1432 phandle phandle;
1433 u32 out_val[5];
1434 int ret;
1435
1436 if (!np)
1437 return -EINVAL;
1438
1439
1440
1441
1442 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1443 ARRAY_SIZE(out_val));
1444 if (ret) {
1445 dev_dbg(&pdev->dev, "no stop-mode property\n");
1446 return ret;
1447 }
1448 phandle = *out_val;
1449
1450 gpr_np = of_find_node_by_phandle(phandle);
1451 if (!gpr_np) {
1452 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1453 return -ENODEV;
1454 }
1455
1456 priv = netdev_priv(dev);
1457 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1458 if (IS_ERR(priv->stm.gpr)) {
1459 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1460 ret = PTR_ERR(priv->stm.gpr);
1461 goto out_put_node;
1462 }
1463
1464 priv->stm.req_gpr = out_val[1];
1465 priv->stm.req_bit = out_val[2];
1466 priv->stm.ack_gpr = out_val[3];
1467 priv->stm.ack_bit = out_val[4];
1468
1469 dev_dbg(&pdev->dev,
1470 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1471 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1472 priv->stm.ack_gpr, priv->stm.ack_bit);
1473
1474 device_set_wakeup_capable(&pdev->dev, true);
1475
1476out_put_node:
1477 of_node_put(gpr_np);
1478 return ret;
1479}
1480
1481static const struct of_device_id flexcan_of_match[] = {
1482 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1483 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1484 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1485 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1486 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1487 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1488 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1489 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1490 { },
1491};
1492MODULE_DEVICE_TABLE(of, flexcan_of_match);
1493
1494static const struct platform_device_id flexcan_id_table[] = {
1495 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1496 { },
1497};
1498MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1499
1500static int flexcan_probe(struct platform_device *pdev)
1501{
1502 const struct of_device_id *of_id;
1503 const struct flexcan_devtype_data *devtype_data;
1504 struct net_device *dev;
1505 struct flexcan_priv *priv;
1506 struct regulator *reg_xceiver;
1507 struct resource *mem;
1508 struct clk *clk_ipg = NULL, *clk_per = NULL;
1509 struct flexcan_regs __iomem *regs;
1510 int err, irq;
1511 u32 clock_freq = 0;
1512
1513 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1514 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1515 return -EPROBE_DEFER;
1516 else if (IS_ERR(reg_xceiver))
1517 reg_xceiver = NULL;
1518
1519 if (pdev->dev.of_node)
1520 of_property_read_u32(pdev->dev.of_node,
1521 "clock-frequency", &clock_freq);
1522
1523 if (!clock_freq) {
1524 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1525 if (IS_ERR(clk_ipg)) {
1526 dev_err(&pdev->dev, "no ipg clock defined\n");
1527 return PTR_ERR(clk_ipg);
1528 }
1529
1530 clk_per = devm_clk_get(&pdev->dev, "per");
1531 if (IS_ERR(clk_per)) {
1532 dev_err(&pdev->dev, "no per clock defined\n");
1533 return PTR_ERR(clk_per);
1534 }
1535 clock_freq = clk_get_rate(clk_per);
1536 }
1537
1538 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1539 irq = platform_get_irq(pdev, 0);
1540 if (irq <= 0)
1541 return -ENODEV;
1542
1543 regs = devm_ioremap_resource(&pdev->dev, mem);
1544 if (IS_ERR(regs))
1545 return PTR_ERR(regs);
1546
1547 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1548 if (of_id) {
1549 devtype_data = of_id->data;
1550 } else if (platform_get_device_id(pdev)->driver_data) {
1551 devtype_data = (struct flexcan_devtype_data *)
1552 platform_get_device_id(pdev)->driver_data;
1553 } else {
1554 return -ENODEV;
1555 }
1556
1557 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1558 if (!dev)
1559 return -ENOMEM;
1560
1561 platform_set_drvdata(pdev, dev);
1562 SET_NETDEV_DEV(dev, &pdev->dev);
1563
1564 dev->netdev_ops = &flexcan_netdev_ops;
1565 dev->irq = irq;
1566 dev->flags |= IFF_ECHO;
1567
1568 priv = netdev_priv(dev);
1569
1570 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1571 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1572 priv->read = flexcan_read_be;
1573 priv->write = flexcan_write_be;
1574 } else {
1575 priv->read = flexcan_read_le;
1576 priv->write = flexcan_write_le;
1577 }
1578
1579 priv->can.clock.freq = clock_freq;
1580 priv->can.bittiming_const = &flexcan_bittiming_const;
1581 priv->can.do_set_mode = flexcan_set_mode;
1582 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1583 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1584 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1585 CAN_CTRLMODE_BERR_REPORTING;
1586 priv->regs = regs;
1587 priv->clk_ipg = clk_ipg;
1588 priv->clk_per = clk_per;
1589 priv->devtype_data = devtype_data;
1590 priv->reg_xceiver = reg_xceiver;
1591
1592 err = register_flexcandev(dev);
1593 if (err) {
1594 dev_err(&pdev->dev, "registering netdev failed\n");
1595 goto failed_register;
1596 }
1597
1598 devm_can_led_init(dev);
1599
1600 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1601 err = flexcan_setup_stop_mode(pdev);
1602 if (err)
1603 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1604 }
1605
1606 return 0;
1607
1608 failed_register:
1609 free_candev(dev);
1610 return err;
1611}
1612
1613static int flexcan_remove(struct platform_device *pdev)
1614{
1615 struct net_device *dev = platform_get_drvdata(pdev);
1616
1617 unregister_flexcandev(dev);
1618 free_candev(dev);
1619
1620 return 0;
1621}
1622
1623static int __maybe_unused flexcan_suspend(struct device *device)
1624{
1625 struct net_device *dev = dev_get_drvdata(device);
1626 struct flexcan_priv *priv = netdev_priv(dev);
1627 int err;
1628
1629 if (netif_running(dev)) {
1630
1631
1632
1633 if (device_may_wakeup(device)) {
1634 enable_irq_wake(dev->irq);
1635 err = flexcan_enter_stop_mode(priv);
1636 if (err)
1637 return err;
1638 } else {
1639 err = flexcan_chip_disable(priv);
1640 if (err)
1641 return err;
1642 }
1643 netif_stop_queue(dev);
1644 netif_device_detach(dev);
1645 }
1646 priv->can.state = CAN_STATE_SLEEPING;
1647
1648 return 0;
1649}
1650
1651static int __maybe_unused flexcan_resume(struct device *device)
1652{
1653 struct net_device *dev = dev_get_drvdata(device);
1654 struct flexcan_priv *priv = netdev_priv(dev);
1655 int err;
1656
1657 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1658 if (netif_running(dev)) {
1659 netif_device_attach(dev);
1660 netif_start_queue(dev);
1661 if (device_may_wakeup(device)) {
1662 disable_irq_wake(dev->irq);
1663 } else {
1664 err = flexcan_chip_enable(priv);
1665 if (err)
1666 return err;
1667 }
1668 }
1669 return 0;
1670}
1671
1672static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1673{
1674 struct net_device *dev = dev_get_drvdata(device);
1675 struct flexcan_priv *priv = netdev_priv(dev);
1676
1677 if (netif_running(dev) && device_may_wakeup(device))
1678 flexcan_enable_wakeup_irq(priv, true);
1679
1680 return 0;
1681}
1682
1683static int __maybe_unused flexcan_noirq_resume(struct device *device)
1684{
1685 struct net_device *dev = dev_get_drvdata(device);
1686 struct flexcan_priv *priv = netdev_priv(dev);
1687 int err;
1688
1689 if (netif_running(dev) && device_may_wakeup(device)) {
1690 flexcan_enable_wakeup_irq(priv, false);
1691 err = flexcan_exit_stop_mode(priv);
1692 if (err)
1693 return err;
1694 }
1695
1696 return 0;
1697}
1698
1699static const struct dev_pm_ops flexcan_pm_ops = {
1700 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1701 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1702};
1703
1704static struct platform_driver flexcan_driver = {
1705 .driver = {
1706 .name = DRV_NAME,
1707 .pm = &flexcan_pm_ops,
1708 .of_match_table = flexcan_of_match,
1709 },
1710 .probe = flexcan_probe,
1711 .remove = flexcan_remove,
1712 .id_table = flexcan_id_table,
1713};
1714
1715module_platform_driver(flexcan_driver);
1716
1717MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1718 "Marc Kleine-Budde <kernel@pengutronix.de>");
1719MODULE_LICENSE("GPL v2");
1720MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
1721