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8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <linux/of_net.h>
21#include <linux/of_mdio.h>
22#include <net/dsa.h>
23#include <linux/ethtool.h>
24#include <linux/if_bridge.h>
25#include <linux/brcmphy.h>
26#include <linux/etherdevice.h>
27#include <linux/platform_data/b53.h>
28
29#include "bcm_sf2.h"
30#include "bcm_sf2_regs.h"
31#include "b53/b53_priv.h"
32#include "b53/b53_regs.h"
33
34static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
35{
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
37 unsigned int i;
38 u32 reg, offset;
39
40 if (priv->type == BCM7445_DEVICE_ID)
41 offset = CORE_STS_OVERRIDE_IMP;
42 else
43 offset = CORE_STS_OVERRIDE_IMP2;
44
45
46 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
47 reg &= ~P_TXQ_PSM_VDD(port);
48 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
49
50
51 reg = core_readl(priv, CORE_IMP_CTL);
52 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
53 reg &= ~(RX_DIS | TX_DIS);
54 core_writel(priv, reg, CORE_IMP_CTL);
55
56
57 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
58
59
60 reg = core_readl(priv, CORE_SWITCH_CTRL);
61 reg |= MII_DUMB_FWDG_EN;
62 core_writel(priv, reg, CORE_SWITCH_CTRL);
63
64
65
66
67 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
68 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
69 reg |= i << (PRT_TO_QID_SHIFT * i);
70 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
71
72 b53_brcm_hdr_setup(ds, port);
73
74
75 reg = core_readl(priv, offset);
76 reg |= (MII_SW_OR | LINK_STS);
77 core_writel(priv, reg, offset);
78}
79
80static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
81{
82 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
83 u32 reg;
84
85 reg = reg_readl(priv, REG_SPHY_CNTRL);
86 if (enable) {
87 reg |= PHY_RESET;
88 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
89 reg_writel(priv, reg, REG_SPHY_CNTRL);
90 udelay(21);
91 reg = reg_readl(priv, REG_SPHY_CNTRL);
92 reg &= ~PHY_RESET;
93 } else {
94 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
95 reg_writel(priv, reg, REG_SPHY_CNTRL);
96 mdelay(1);
97 reg |= CK25_DIS;
98 }
99 reg_writel(priv, reg, REG_SPHY_CNTRL);
100
101
102 if (!enable) {
103 reg = reg_readl(priv, REG_LED_CNTRL(0));
104 reg |= SPDLNK_SRC_SEL;
105 reg_writel(priv, reg, REG_LED_CNTRL(0));
106 }
107}
108
109static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
110 int port)
111{
112 unsigned int off;
113
114 switch (port) {
115 case 7:
116 off = P7_IRQ_OFF;
117 break;
118 case 0:
119
120 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
121 return;
122 default:
123 off = P_IRQ_OFF(port);
124 break;
125 }
126
127 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
128}
129
130static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
131 int port)
132{
133 unsigned int off;
134
135 switch (port) {
136 case 7:
137 off = P7_IRQ_OFF;
138 break;
139 case 0:
140
141 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
142 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
143 return;
144 default:
145 off = P_IRQ_OFF(port);
146 break;
147 }
148
149 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
150 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
151}
152
153static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
154 struct phy_device *phy)
155{
156 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
157 unsigned int i;
158 u32 reg;
159
160
161 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
162 reg &= ~P_TXQ_PSM_VDD(port);
163 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
164
165
166 reg = core_readl(priv, CORE_DIS_LEARN);
167 reg &= ~BIT(port);
168 core_writel(priv, reg, CORE_DIS_LEARN);
169
170
171 if (priv->brcm_tag_mask & BIT(port))
172 b53_brcm_hdr_setup(ds, port);
173
174
175
176
177 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
178 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
179 reg |= i << (PRT_TO_QID_SHIFT * i);
180 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
181
182
183 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
184 bcm_sf2_gphy_enable_set(ds, true);
185 if (phy) {
186
187
188
189
190
191
192
193
194
195 phy->state = PHY_READY;
196 phy_init_hw(phy);
197 }
198 }
199
200
201 if (port == priv->moca_port)
202 bcm_sf2_port_intr_enable(priv, port);
203
204
205 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
206
207
208 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
209 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
210 SF2_NUM_EGRESS_QUEUES + i));
211 reg &= ~XOFF_THRESHOLD_MASK;
212 reg |= 24;
213 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
214 SF2_NUM_EGRESS_QUEUES + i));
215 }
216
217 return b53_enable_port(ds, port, phy);
218}
219
220static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
221{
222 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
223 u32 reg;
224
225
226 if (priv->wol_ports_mask & (1 << port)) {
227 reg = core_readl(priv, CORE_DIS_LEARN);
228 reg |= BIT(port);
229 core_writel(priv, reg, CORE_DIS_LEARN);
230 return;
231 }
232
233 if (port == priv->moca_port)
234 bcm_sf2_port_intr_disable(priv, port);
235
236 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
237 bcm_sf2_gphy_enable_set(ds, false);
238
239 b53_disable_port(ds, port);
240
241
242 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
243 reg |= P_TXQ_PSM_VDD(port);
244 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
245}
246
247
248static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
249 int regnum, u16 val)
250{
251 int ret = 0;
252 u32 reg;
253
254 reg = reg_readl(priv, REG_SWITCH_CNTRL);
255 reg |= MDIO_MASTER_SEL;
256 reg_writel(priv, reg, REG_SWITCH_CNTRL);
257
258
259 reg = 0x70;
260 reg <<= 2;
261 core_writel(priv, addr, reg);
262
263
264 reg = 0x80 << 8 | regnum << 1;
265 reg <<= 2;
266
267 if (op)
268 ret = core_readl(priv, reg);
269 else
270 core_writel(priv, val, reg);
271
272 reg = reg_readl(priv, REG_SWITCH_CNTRL);
273 reg &= ~MDIO_MASTER_SEL;
274 reg_writel(priv, reg, REG_SWITCH_CNTRL);
275
276 return ret & 0xffff;
277}
278
279static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
280{
281 struct bcm_sf2_priv *priv = bus->priv;
282
283
284
285
286 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
287 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
288 else
289 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
290}
291
292static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
293 u16 val)
294{
295 struct bcm_sf2_priv *priv = bus->priv;
296
297
298
299
300 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
301 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
302 else
303 return mdiobus_write_nested(priv->master_mii_bus, addr,
304 regnum, val);
305}
306
307static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
308{
309 struct dsa_switch *ds = dev_id;
310 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
311
312 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
313 ~priv->irq0_mask;
314 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
315
316 return IRQ_HANDLED;
317}
318
319static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
320{
321 struct dsa_switch *ds = dev_id;
322 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
323
324 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
325 ~priv->irq1_mask;
326 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
327
328 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
329 priv->port_sts[7].link = true;
330 dsa_port_phylink_mac_change(ds, 7, true);
331 }
332 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
333 priv->port_sts[7].link = false;
334 dsa_port_phylink_mac_change(ds, 7, false);
335 }
336
337 return IRQ_HANDLED;
338}
339
340static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
341{
342 unsigned int timeout = 1000;
343 u32 reg;
344
345 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
346 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
347 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
348
349 do {
350 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
351 if (!(reg & SOFTWARE_RESET))
352 break;
353
354 usleep_range(1000, 2000);
355 } while (timeout-- > 0);
356
357 if (timeout == 0)
358 return -ETIMEDOUT;
359
360 return 0;
361}
362
363static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
364{
365 intrl2_0_mask_set(priv, 0xffffffff);
366 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
367 intrl2_1_mask_set(priv, 0xffffffff);
368 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
369}
370
371static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
372 struct device_node *dn)
373{
374 struct device_node *port;
375 int mode;
376 unsigned int port_num;
377
378 priv->moca_port = -1;
379
380 for_each_available_child_of_node(dn, port) {
381 if (of_property_read_u32(port, "reg", &port_num))
382 continue;
383
384
385
386
387
388
389 mode = of_get_phy_mode(port);
390 if (mode < 0)
391 continue;
392
393 if (mode == PHY_INTERFACE_MODE_INTERNAL)
394 priv->int_phy_mask |= 1 << port_num;
395
396 if (mode == PHY_INTERFACE_MODE_MOCA)
397 priv->moca_port = port_num;
398
399 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
400 priv->brcm_tag_mask |= 1 << port_num;
401 }
402}
403
404static int bcm_sf2_mdio_register(struct dsa_switch *ds)
405{
406 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
407 struct device_node *dn;
408 static int index;
409 int err;
410
411
412 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
413 priv->master_mii_bus = of_mdio_find_bus(dn);
414 if (!priv->master_mii_bus)
415 return -EPROBE_DEFER;
416
417 get_device(&priv->master_mii_bus->dev);
418 priv->master_mii_dn = dn;
419
420 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
421 if (!priv->slave_mii_bus)
422 return -ENOMEM;
423
424 priv->slave_mii_bus->priv = priv;
425 priv->slave_mii_bus->name = "sf2 slave mii";
426 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
427 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
428 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
429 index++);
430 priv->slave_mii_bus->dev.of_node = dn;
431
432
433
434
435
436
437
438
439
440
441
442 if (of_machine_is_compatible("brcm,bcm7445d0"))
443 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
444 else
445 priv->indir_phy_mask = 0;
446
447 ds->phys_mii_mask = priv->indir_phy_mask;
448 ds->slave_mii_bus = priv->slave_mii_bus;
449 priv->slave_mii_bus->parent = ds->dev->parent;
450 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
451
452 err = of_mdiobus_register(priv->slave_mii_bus, dn);
453 if (err && dn)
454 of_node_put(dn);
455
456 return err;
457}
458
459static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
460{
461 mdiobus_unregister(priv->slave_mii_bus);
462 of_node_put(priv->master_mii_dn);
463}
464
465static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
466{
467 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
468
469
470
471
472
473
474 return priv->hw_params.gphy_rev;
475}
476
477static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
478 unsigned long *supported,
479 struct phylink_link_state *state)
480{
481 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
482 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
483
484 if (!phy_interface_mode_is_rgmii(state->interface) &&
485 state->interface != PHY_INTERFACE_MODE_MII &&
486 state->interface != PHY_INTERFACE_MODE_REVMII &&
487 state->interface != PHY_INTERFACE_MODE_GMII &&
488 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
489 state->interface != PHY_INTERFACE_MODE_MOCA) {
490 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
491 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
492 dev_err(ds->dev,
493 "Unsupported interface: %d for port %d\n",
494 state->interface, port);
495 return;
496 }
497
498
499 phylink_set(mask, Autoneg);
500 phylink_set_port_modes(mask);
501 phylink_set(mask, Pause);
502 phylink_set(mask, Asym_Pause);
503
504
505
506
507 if (state->interface != PHY_INTERFACE_MODE_MII &&
508 state->interface != PHY_INTERFACE_MODE_REVMII) {
509 phylink_set(mask, 1000baseT_Full);
510 phylink_set(mask, 1000baseT_Half);
511 }
512
513 phylink_set(mask, 10baseT_Half);
514 phylink_set(mask, 10baseT_Full);
515 phylink_set(mask, 100baseT_Half);
516 phylink_set(mask, 100baseT_Full);
517
518 bitmap_and(supported, supported, mask,
519 __ETHTOOL_LINK_MODE_MASK_NBITS);
520 bitmap_and(state->advertising, state->advertising, mask,
521 __ETHTOOL_LINK_MODE_MASK_NBITS);
522}
523
524static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
525 unsigned int mode,
526 const struct phylink_link_state *state)
527{
528 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
529 u32 id_mode_dis = 0, port_mode;
530 u32 reg, offset;
531
532 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
533 return;
534
535 if (priv->type == BCM7445_DEVICE_ID)
536 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
537 else
538 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
539
540 switch (state->interface) {
541 case PHY_INTERFACE_MODE_RGMII:
542 id_mode_dis = 1;
543
544 case PHY_INTERFACE_MODE_RGMII_TXID:
545 port_mode = EXT_GPHY;
546 break;
547 case PHY_INTERFACE_MODE_MII:
548 port_mode = EXT_EPHY;
549 break;
550 case PHY_INTERFACE_MODE_REVMII:
551 port_mode = EXT_REVMII;
552 break;
553 default:
554
555 goto force_link;
556 }
557
558
559
560
561 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
562 reg &= ~ID_MODE_DIS;
563 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
564 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
565
566 reg |= port_mode;
567 if (id_mode_dis)
568 reg |= ID_MODE_DIS;
569
570 if (state->pause & MLO_PAUSE_TXRX_MASK) {
571 if (state->pause & MLO_PAUSE_TX)
572 reg |= TX_PAUSE_EN;
573 reg |= RX_PAUSE_EN;
574 }
575
576 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
577
578force_link:
579
580 reg = SW_OVERRIDE;
581 switch (state->speed) {
582 case SPEED_1000:
583 reg |= SPDSTS_1000 << SPEED_SHIFT;
584 break;
585 case SPEED_100:
586 reg |= SPDSTS_100 << SPEED_SHIFT;
587 break;
588 }
589
590 if (state->link)
591 reg |= LINK_STS;
592 if (state->duplex == DUPLEX_FULL)
593 reg |= DUPLX_MODE;
594
595 core_writel(priv, reg, offset);
596}
597
598static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
599 phy_interface_t interface, bool link)
600{
601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
602 u32 reg;
603
604 if (!phy_interface_mode_is_rgmii(interface) &&
605 interface != PHY_INTERFACE_MODE_MII &&
606 interface != PHY_INTERFACE_MODE_REVMII)
607 return;
608
609
610 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
611 if (link)
612 reg |= RGMII_MODE_EN;
613 else
614 reg &= ~RGMII_MODE_EN;
615 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
616}
617
618static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
619 unsigned int mode,
620 phy_interface_t interface)
621{
622 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
623}
624
625static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
626 unsigned int mode,
627 phy_interface_t interface,
628 struct phy_device *phydev)
629{
630 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
631 struct ethtool_eee *p = &priv->dev->ports[port].eee;
632
633 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
634
635 if (mode == MLO_AN_PHY && phydev)
636 p->eee_enabled = b53_eee_init(ds, port, phydev);
637}
638
639static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
640 struct phylink_link_state *status)
641{
642 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
643
644 status->link = false;
645
646
647
648
649
650
651
652
653
654 if (port == priv->moca_port) {
655 status->link = priv->port_sts[port].link;
656
657
658
659
660
661 if (!status->link)
662 netif_carrier_off(ds->ports[port].slave);
663 status->duplex = DUPLEX_FULL;
664 } else {
665 status->link = true;
666 }
667}
668
669static void bcm_sf2_enable_acb(struct dsa_switch *ds)
670{
671 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
672 u32 reg;
673
674
675 reg = acb_readl(priv, ACB_CONTROL);
676 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
677 acb_writel(priv, reg, ACB_CONTROL);
678 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
679 reg |= ACB_EN | ACB_ALGORITHM;
680 acb_writel(priv, reg, ACB_CONTROL);
681}
682
683static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
684{
685 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
686 unsigned int port;
687
688 bcm_sf2_intr_disable(priv);
689
690
691
692
693
694 for (port = 0; port < ds->num_ports; port++) {
695 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
696 bcm_sf2_port_disable(ds, port);
697 }
698
699 return 0;
700}
701
702static int bcm_sf2_sw_resume(struct dsa_switch *ds)
703{
704 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
705 int ret;
706
707 ret = bcm_sf2_sw_rst(priv);
708 if (ret) {
709 pr_err("%s: failed to software reset switch\n", __func__);
710 return ret;
711 }
712
713 ret = bcm_sf2_cfp_resume(ds);
714 if (ret)
715 return ret;
716
717 if (priv->hw_params.num_gphy == 1)
718 bcm_sf2_gphy_enable_set(ds, true);
719
720 ds->ops->setup(ds);
721
722 return 0;
723}
724
725static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
726 struct ethtool_wolinfo *wol)
727{
728 struct net_device *p = ds->ports[port].cpu_dp->master;
729 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
730 struct ethtool_wolinfo pwol = { };
731
732
733 if (p->ethtool_ops->get_wol)
734 p->ethtool_ops->get_wol(p, &pwol);
735
736
737 wol->supported = pwol.supported;
738 memset(&wol->sopass, 0, sizeof(wol->sopass));
739
740 if (pwol.wolopts & WAKE_MAGICSECURE)
741 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
742
743 if (priv->wol_ports_mask & (1 << port))
744 wol->wolopts = pwol.wolopts;
745 else
746 wol->wolopts = 0;
747}
748
749static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
750 struct ethtool_wolinfo *wol)
751{
752 struct net_device *p = ds->ports[port].cpu_dp->master;
753 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
754 s8 cpu_port = ds->ports[port].cpu_dp->index;
755 struct ethtool_wolinfo pwol = { };
756
757 if (p->ethtool_ops->get_wol)
758 p->ethtool_ops->get_wol(p, &pwol);
759 if (wol->wolopts & ~pwol.supported)
760 return -EINVAL;
761
762 if (wol->wolopts)
763 priv->wol_ports_mask |= (1 << port);
764 else
765 priv->wol_ports_mask &= ~(1 << port);
766
767
768
769
770
771 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
772 priv->wol_ports_mask |= (1 << cpu_port);
773 else
774 priv->wol_ports_mask &= ~(1 << cpu_port);
775
776 return p->ethtool_ops->set_wol(p, wol);
777}
778
779static int bcm_sf2_sw_setup(struct dsa_switch *ds)
780{
781 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
782 unsigned int port;
783
784
785 for (port = 0; port < priv->hw_params.num_ports; port++) {
786
787 if (dsa_is_user_port(ds, port))
788 bcm_sf2_port_setup(ds, port, NULL);
789 else if (dsa_is_cpu_port(ds, port))
790 bcm_sf2_imp_setup(ds, port);
791 else
792 bcm_sf2_port_disable(ds, port);
793 }
794
795 b53_configure_vlan(ds);
796 bcm_sf2_enable_acb(ds);
797
798 return 0;
799}
800
801
802
803
804
805#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
806
807static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
808 u8 *val)
809{
810 struct bcm_sf2_priv *priv = dev->priv;
811
812 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
813
814 return 0;
815}
816
817static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
818 u16 *val)
819{
820 struct bcm_sf2_priv *priv = dev->priv;
821
822 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
823
824 return 0;
825}
826
827static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
828 u32 *val)
829{
830 struct bcm_sf2_priv *priv = dev->priv;
831
832 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
833
834 return 0;
835}
836
837static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
838 u64 *val)
839{
840 struct bcm_sf2_priv *priv = dev->priv;
841
842 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
843
844 return 0;
845}
846
847static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
848 u8 value)
849{
850 struct bcm_sf2_priv *priv = dev->priv;
851
852 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
853
854 return 0;
855}
856
857static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
858 u16 value)
859{
860 struct bcm_sf2_priv *priv = dev->priv;
861
862 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
863
864 return 0;
865}
866
867static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
868 u32 value)
869{
870 struct bcm_sf2_priv *priv = dev->priv;
871
872 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
873
874 return 0;
875}
876
877static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
878 u64 value)
879{
880 struct bcm_sf2_priv *priv = dev->priv;
881
882 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
883
884 return 0;
885}
886
887static const struct b53_io_ops bcm_sf2_io_ops = {
888 .read8 = bcm_sf2_core_read8,
889 .read16 = bcm_sf2_core_read16,
890 .read32 = bcm_sf2_core_read32,
891 .read48 = bcm_sf2_core_read64,
892 .read64 = bcm_sf2_core_read64,
893 .write8 = bcm_sf2_core_write8,
894 .write16 = bcm_sf2_core_write16,
895 .write32 = bcm_sf2_core_write32,
896 .write48 = bcm_sf2_core_write64,
897 .write64 = bcm_sf2_core_write64,
898};
899
900static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
901 u32 stringset, uint8_t *data)
902{
903 int cnt = b53_get_sset_count(ds, port, stringset);
904
905 b53_get_strings(ds, port, stringset, data);
906 bcm_sf2_cfp_get_strings(ds, port, stringset,
907 data + cnt * ETH_GSTRING_LEN);
908}
909
910static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
911 uint64_t *data)
912{
913 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
914
915 b53_get_ethtool_stats(ds, port, data);
916 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
917}
918
919static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
920 int sset)
921{
922 int cnt = b53_get_sset_count(ds, port, sset);
923
924 if (cnt < 0)
925 return cnt;
926
927 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
928
929 return cnt;
930}
931
932static const struct dsa_switch_ops bcm_sf2_ops = {
933 .get_tag_protocol = b53_get_tag_protocol,
934 .setup = bcm_sf2_sw_setup,
935 .get_strings = bcm_sf2_sw_get_strings,
936 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
937 .get_sset_count = bcm_sf2_sw_get_sset_count,
938 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
939 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
940 .phylink_validate = bcm_sf2_sw_validate,
941 .phylink_mac_config = bcm_sf2_sw_mac_config,
942 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
943 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
944 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
945 .suspend = bcm_sf2_sw_suspend,
946 .resume = bcm_sf2_sw_resume,
947 .get_wol = bcm_sf2_sw_get_wol,
948 .set_wol = bcm_sf2_sw_set_wol,
949 .port_enable = bcm_sf2_port_setup,
950 .port_disable = bcm_sf2_port_disable,
951 .get_mac_eee = b53_get_mac_eee,
952 .set_mac_eee = b53_set_mac_eee,
953 .port_bridge_join = b53_br_join,
954 .port_bridge_leave = b53_br_leave,
955 .port_stp_state_set = b53_br_set_stp_state,
956 .port_fast_age = b53_br_fast_age,
957 .port_vlan_filtering = b53_vlan_filtering,
958 .port_vlan_prepare = b53_vlan_prepare,
959 .port_vlan_add = b53_vlan_add,
960 .port_vlan_del = b53_vlan_del,
961 .port_fdb_dump = b53_fdb_dump,
962 .port_fdb_add = b53_fdb_add,
963 .port_fdb_del = b53_fdb_del,
964 .get_rxnfc = bcm_sf2_get_rxnfc,
965 .set_rxnfc = bcm_sf2_set_rxnfc,
966 .port_mirror_add = b53_mirror_add,
967 .port_mirror_del = b53_mirror_del,
968};
969
970struct bcm_sf2_of_data {
971 u32 type;
972 const u16 *reg_offsets;
973 unsigned int core_reg_align;
974 unsigned int num_cfp_rules;
975};
976
977
978static const u16 bcm_sf2_7445_reg_offsets[] = {
979 [REG_SWITCH_CNTRL] = 0x00,
980 [REG_SWITCH_STATUS] = 0x04,
981 [REG_DIR_DATA_WRITE] = 0x08,
982 [REG_DIR_DATA_READ] = 0x0C,
983 [REG_SWITCH_REVISION] = 0x18,
984 [REG_PHY_REVISION] = 0x1C,
985 [REG_SPHY_CNTRL] = 0x2C,
986 [REG_RGMII_0_CNTRL] = 0x34,
987 [REG_RGMII_1_CNTRL] = 0x40,
988 [REG_RGMII_2_CNTRL] = 0x4c,
989 [REG_LED_0_CNTRL] = 0x90,
990 [REG_LED_1_CNTRL] = 0x94,
991 [REG_LED_2_CNTRL] = 0x98,
992};
993
994static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
995 .type = BCM7445_DEVICE_ID,
996 .core_reg_align = 0,
997 .reg_offsets = bcm_sf2_7445_reg_offsets,
998 .num_cfp_rules = 256,
999};
1000
1001static const u16 bcm_sf2_7278_reg_offsets[] = {
1002 [REG_SWITCH_CNTRL] = 0x00,
1003 [REG_SWITCH_STATUS] = 0x04,
1004 [REG_DIR_DATA_WRITE] = 0x08,
1005 [REG_DIR_DATA_READ] = 0x0c,
1006 [REG_SWITCH_REVISION] = 0x10,
1007 [REG_PHY_REVISION] = 0x14,
1008 [REG_SPHY_CNTRL] = 0x24,
1009 [REG_RGMII_0_CNTRL] = 0xe0,
1010 [REG_RGMII_1_CNTRL] = 0xec,
1011 [REG_RGMII_2_CNTRL] = 0xf8,
1012 [REG_LED_0_CNTRL] = 0x40,
1013 [REG_LED_1_CNTRL] = 0x4c,
1014 [REG_LED_2_CNTRL] = 0x58,
1015};
1016
1017static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1018 .type = BCM7278_DEVICE_ID,
1019 .core_reg_align = 1,
1020 .reg_offsets = bcm_sf2_7278_reg_offsets,
1021 .num_cfp_rules = 128,
1022};
1023
1024static const struct of_device_id bcm_sf2_of_match[] = {
1025 { .compatible = "brcm,bcm7445-switch-v4.0",
1026 .data = &bcm_sf2_7445_data
1027 },
1028 { .compatible = "brcm,bcm7278-switch-v4.0",
1029 .data = &bcm_sf2_7278_data
1030 },
1031 { .compatible = "brcm,bcm7278-switch-v4.8",
1032 .data = &bcm_sf2_7278_data
1033 },
1034 { },
1035};
1036MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1037
1038static int bcm_sf2_sw_probe(struct platform_device *pdev)
1039{
1040 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1041 struct device_node *dn = pdev->dev.of_node;
1042 const struct of_device_id *of_id = NULL;
1043 const struct bcm_sf2_of_data *data;
1044 struct b53_platform_data *pdata;
1045 struct dsa_switch_ops *ops;
1046 struct bcm_sf2_priv *priv;
1047 struct b53_device *dev;
1048 struct dsa_switch *ds;
1049 void __iomem **base;
1050 struct resource *r;
1051 unsigned int i;
1052 u32 reg, rev;
1053 int ret;
1054
1055 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1056 if (!priv)
1057 return -ENOMEM;
1058
1059 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1060 if (!ops)
1061 return -ENOMEM;
1062
1063 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1064 if (!dev)
1065 return -ENOMEM;
1066
1067 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1068 if (!pdata)
1069 return -ENOMEM;
1070
1071 of_id = of_match_node(bcm_sf2_of_match, dn);
1072 if (!of_id || !of_id->data)
1073 return -EINVAL;
1074
1075 data = of_id->data;
1076
1077
1078 priv->type = data->type;
1079 priv->reg_offsets = data->reg_offsets;
1080 priv->core_reg_align = data->core_reg_align;
1081 priv->num_cfp_rules = data->num_cfp_rules;
1082
1083
1084
1085
1086
1087 pdata->chip_id = priv->type;
1088 dev->pdata = pdata;
1089
1090 priv->dev = dev;
1091 ds = dev->ds;
1092 ds->ops = &bcm_sf2_ops;
1093
1094
1095 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1096
1097 dev_set_drvdata(&pdev->dev, priv);
1098
1099 spin_lock_init(&priv->indir_lock);
1100 mutex_init(&priv->cfp.lock);
1101 INIT_LIST_HEAD(&priv->cfp.rules_list);
1102
1103
1104
1105
1106 set_bit(0, priv->cfp.used);
1107 set_bit(0, priv->cfp.unique);
1108
1109 bcm_sf2_identify_ports(priv, dn->child);
1110
1111 priv->irq0 = irq_of_parse_and_map(dn, 0);
1112 priv->irq1 = irq_of_parse_and_map(dn, 1);
1113
1114 base = &priv->core;
1115 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1116 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1117 *base = devm_ioremap_resource(&pdev->dev, r);
1118 if (IS_ERR(*base)) {
1119 pr_err("unable to find register: %s\n", reg_names[i]);
1120 return PTR_ERR(*base);
1121 }
1122 base++;
1123 }
1124
1125 ret = bcm_sf2_sw_rst(priv);
1126 if (ret) {
1127 pr_err("unable to software reset switch: %d\n", ret);
1128 return ret;
1129 }
1130
1131 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1132
1133 ret = bcm_sf2_mdio_register(ds);
1134 if (ret) {
1135 pr_err("failed to register MDIO bus\n");
1136 return ret;
1137 }
1138
1139 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1140
1141 ret = bcm_sf2_cfp_rst(priv);
1142 if (ret) {
1143 pr_err("failed to reset CFP\n");
1144 goto out_mdio;
1145 }
1146
1147
1148 bcm_sf2_intr_disable(priv);
1149
1150 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1151 "switch_0", ds);
1152 if (ret < 0) {
1153 pr_err("failed to request switch_0 IRQ\n");
1154 goto out_mdio;
1155 }
1156
1157 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1158 "switch_1", ds);
1159 if (ret < 0) {
1160 pr_err("failed to request switch_1 IRQ\n");
1161 goto out_mdio;
1162 }
1163
1164
1165 reg = core_readl(priv, CORE_GMNCFGCFG);
1166 reg |= RST_MIB_CNT;
1167 core_writel(priv, reg, CORE_GMNCFGCFG);
1168 reg &= ~RST_MIB_CNT;
1169 core_writel(priv, reg, CORE_GMNCFGCFG);
1170
1171
1172 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1173 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1174 priv->hw_params.num_ports = DSA_MAX_PORTS;
1175
1176
1177 if (of_property_read_u32(dn, "brcm,num-gphy",
1178 &priv->hw_params.num_gphy))
1179 priv->hw_params.num_gphy = 1;
1180
1181 rev = reg_readl(priv, REG_SWITCH_REVISION);
1182 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1183 SWITCH_TOP_REV_MASK;
1184 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1185
1186 rev = reg_readl(priv, REG_PHY_REVISION);
1187 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1188
1189 ret = b53_switch_register(dev);
1190 if (ret)
1191 goto out_mdio;
1192
1193 dev_info(&pdev->dev,
1194 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1195 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1196 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1197 priv->irq0, priv->irq1);
1198
1199 return 0;
1200
1201out_mdio:
1202 bcm_sf2_mdio_unregister(priv);
1203 return ret;
1204}
1205
1206static int bcm_sf2_sw_remove(struct platform_device *pdev)
1207{
1208 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1209
1210 priv->wol_ports_mask = 0;
1211 dsa_unregister_switch(priv->dev->ds);
1212 bcm_sf2_cfp_exit(priv->dev->ds);
1213
1214 bcm_sf2_sw_suspend(priv->dev->ds);
1215 bcm_sf2_mdio_unregister(priv);
1216
1217 return 0;
1218}
1219
1220static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1221{
1222 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1223
1224
1225
1226
1227
1228
1229
1230 if (priv->hw_params.num_gphy == 1)
1231 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1232}
1233
1234#ifdef CONFIG_PM_SLEEP
1235static int bcm_sf2_suspend(struct device *dev)
1236{
1237 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1238
1239 return dsa_switch_suspend(priv->dev->ds);
1240}
1241
1242static int bcm_sf2_resume(struct device *dev)
1243{
1244 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1245
1246 return dsa_switch_resume(priv->dev->ds);
1247}
1248#endif
1249
1250static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1251 bcm_sf2_suspend, bcm_sf2_resume);
1252
1253
1254static struct platform_driver bcm_sf2_driver = {
1255 .probe = bcm_sf2_sw_probe,
1256 .remove = bcm_sf2_sw_remove,
1257 .shutdown = bcm_sf2_sw_shutdown,
1258 .driver = {
1259 .name = "brcm-sf2",
1260 .of_match_table = bcm_sf2_of_match,
1261 .pm = &bcm_sf2_pm_ops,
1262 },
1263};
1264module_platform_driver(bcm_sf2_driver);
1265
1266MODULE_AUTHOR("Broadcom Corporation");
1267MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1268MODULE_LICENSE("GPL");
1269MODULE_ALIAS("platform:brcm-sf2");
1270