LXR linux/drivers/net/dsa/mv88e6xxx/port.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Marvell 88E6xxx Switch Port Registers support
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 *
   7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   8 *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   9 */
  10
  11#include <linux/bitfield.h>
  12#include <linux/if_bridge.h>
  13#include <linux/phy.h>
  14#include <linux/phylink.h>
  15
  16#include "chip.h"
  17#include "port.h"
  18#include "serdes.h"
  19
  20int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
  21                        u16 *val)
  22{
  23        int addr = chip->info->port_base_addr + port;
  24
  25        return mv88e6xxx_read(chip, addr, reg, val);
  26}
  27
  28int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
  29                         u16 val)
  30{
  31        int addr = chip->info->port_base_addr + port;
  32
  33        return mv88e6xxx_write(chip, addr, reg, val);
  34}
  35
  36/* Offset 0x00: MAC (or PCS or Physical) Status Register
  37 *
  38 * For most devices, this is read only. However the 6185 has the MyPause
  39 * bit read/write.
  40 */
  41int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
  42                             int pause)
  43{
  44        u16 reg;
  45        int err;
  46
  47        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
  48        if (err)
  49                return err;
  50
  51        if (pause)
  52                reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
  53        else
  54                reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
  55
  56        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
  57}
  58
  59/* Offset 0x01: MAC (or PCS or Physical) Control Register
  60 *
  61 * Link, Duplex and Flow Control have one force bit, one value bit.
  62 *
  63 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
  64 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
  65 * Newer chips need a ForcedSpd bit 13 set to consider the value.
  66 */
  67
  68static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
  69                                          phy_interface_t mode)
  70{
  71        u16 reg;
  72        int err;
  73
  74        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
  75        if (err)
  76                return err;
  77
  78        reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
  79                 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
  80
  81        switch (mode) {
  82        case PHY_INTERFACE_MODE_RGMII_RXID:
  83                reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
  84                break;
  85        case PHY_INTERFACE_MODE_RGMII_TXID:
  86                reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
  87                break;
  88        case PHY_INTERFACE_MODE_RGMII_ID:
  89                reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
  90                        MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
  91                break;
  92        case PHY_INTERFACE_MODE_RGMII:
  93                break;
  94        default:
  95                return 0;
  96        }
  97
  98        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
  99        if (err)
 100                return err;
 101
 102        dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
 103                reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
 104                reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
 105
 106        return 0;
 107}
 108
 109int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 110                                   phy_interface_t mode)
 111{
 112        if (port < 5)
 113                return -EOPNOTSUPP;
 114
 115        return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
 116}
 117
 118int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 119                                   phy_interface_t mode)
 120{
 121        if (port != 0)
 122                return -EOPNOTSUPP;
 123
 124        return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
 125}
 126
 127int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
 128{
 129        u16 reg;
 130        int err;
 131
 132        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
 133        if (err)
 134                return err;
 135
 136        reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
 137                 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
 138
 139        switch (link) {
 140        case LINK_FORCED_DOWN:
 141                reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
 142                break;
 143        case LINK_FORCED_UP:
 144                reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
 145                        MV88E6XXX_PORT_MAC_CTL_LINK_UP;
 146                break;
 147        case LINK_UNFORCED:
 148                /* normal link detection */
 149                break;
 150        default:
 151                return -EINVAL;
 152        }
 153
 154        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
 155        if (err)
 156                return err;
 157
 158        dev_dbg(chip->dev, "p%d: %s link %s\n", port,
 159                reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
 160                reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
 161
 162        return 0;
 163}
 164
 165int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
 166{
 167        u16 reg;
 168        int err;
 169
 170        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
 171        if (err)
 172                return err;
 173
 174        reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
 175                 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
 176
 177        switch (dup) {
 178        case DUPLEX_HALF:
 179                reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
 180                break;
 181        case DUPLEX_FULL:
 182                reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
 183                        MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
 184                break;
 185        case DUPLEX_UNFORCED:
 186                /* normal duplex detection */
 187                break;
 188        default:
 189                return -EOPNOTSUPP;
 190        }
 191
 192        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
 193        if (err)
 194                return err;
 195
 196        dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
 197                reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
 198                reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
 199
 200        return 0;
 201}
 202
 203static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
 204                                    int speed, bool alt_bit, bool force_bit)
 205{
 206        u16 reg, ctrl;
 207        int err;
 208
 209        switch (speed) {
 210        case 10:
 211                ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
 212                break;
 213        case 100:
 214                ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
 215                break;
 216        case 200:
 217                if (alt_bit)
 218                        ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
 219                                MV88E6390_PORT_MAC_CTL_ALTSPEED;
 220                else
 221                        ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
 222                break;
 223        case 1000:
 224                ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
 225                break;
 226        case 2500:
 227                if (alt_bit)
 228                        ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
 229                                MV88E6390_PORT_MAC_CTL_ALTSPEED;
 230                else
 231                        ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
 232                break;
 233        case 10000:
 234                /* all bits set, fall through... */
 235        case SPEED_UNFORCED:
 236                ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
 237                break;
 238        default:
 239                return -EOPNOTSUPP;
 240        }
 241
 242        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
 243        if (err)
 244                return err;
 245
 246        reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
 247        if (alt_bit)
 248                reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
 249        if (force_bit) {
 250                reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
 251                if (speed != SPEED_UNFORCED)
 252                        ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
 253        }
 254        reg |= ctrl;
 255
 256        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
 257        if (err)
 258                return err;
 259
 260        if (speed)
 261                dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
 262        else
 263                dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
 264
 265        return 0;
 266}
 267
 268/* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
 269int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 270{
 271        if (speed == SPEED_MAX)
 272                speed = 200;
 273
 274        if (speed > 200)
 275                return -EOPNOTSUPP;
 276
 277        /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
 278        return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
 279}
 280
 281/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
 282int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 283{
 284        if (speed == SPEED_MAX)
 285                speed = 1000;
 286
 287        if (speed == 200 || speed > 1000)
 288                return -EOPNOTSUPP;
 289
 290        return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
 291}
 292
 293/* Support 10, 100 Mbps (e.g. 88E6250 family) */
 294int mv88e6250_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 295{
 296        if (speed == SPEED_MAX)
 297                speed = 100;
 298
 299        if (speed > 100)
 300                return -EOPNOTSUPP;
 301
 302        return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
 303}
 304
 305/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
 306int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 307{
 308        if (speed == SPEED_MAX)
 309                speed = port < 5 ? 1000 : 2500;
 310
 311        if (speed > 2500)
 312                return -EOPNOTSUPP;
 313
 314        if (speed == 200 && port != 0)
 315                return -EOPNOTSUPP;
 316
 317        if (speed == 2500 && port < 5)
 318                return -EOPNOTSUPP;
 319
 320        return mv88e6xxx_port_set_speed(chip, port, speed, !port, true);
 321}
 322
 323phy_interface_t mv88e6341_port_max_speed_mode(int port)
 324{
 325        if (port == 5)
 326                return PHY_INTERFACE_MODE_2500BASEX;
 327
 328        return PHY_INTERFACE_MODE_NA;
 329}
 330
 331/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
 332int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 333{
 334        if (speed == SPEED_MAX)
 335                speed = 1000;
 336
 337        if (speed > 1000)
 338                return -EOPNOTSUPP;
 339
 340        if (speed == 200 && port < 5)
 341                return -EOPNOTSUPP;
 342
 343        return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
 344}
 345
 346/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
 347int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 348{
 349        if (speed == SPEED_MAX)
 350                speed = port < 9 ? 1000 : 2500;
 351
 352        if (speed > 2500)
 353                return -EOPNOTSUPP;
 354
 355        if (speed == 200 && port != 0)
 356                return -EOPNOTSUPP;
 357
 358        if (speed == 2500 && port < 9)
 359                return -EOPNOTSUPP;
 360
 361        return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
 362}
 363
 364phy_interface_t mv88e6390_port_max_speed_mode(int port)
 365{
 366        if (port == 9 || port == 10)
 367                return PHY_INTERFACE_MODE_2500BASEX;
 368
 369        return PHY_INTERFACE_MODE_NA;
 370}
 371
 372/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
 373int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 374{
 375        if (speed == SPEED_MAX)
 376                speed = port < 9 ? 1000 : 10000;
 377
 378        if (speed == 200 && port != 0)
 379                return -EOPNOTSUPP;
 380
 381        if (speed >= 2500 && port < 9)
 382                return -EOPNOTSUPP;
 383
 384        return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
 385}
 386
 387phy_interface_t mv88e6390x_port_max_speed_mode(int port)
 388{
 389        if (port == 9 || port == 10)
 390                return PHY_INTERFACE_MODE_XAUI;
 391
 392        return PHY_INTERFACE_MODE_NA;
 393}
 394
 395int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 396                              phy_interface_t mode)
 397{
 398        int lane;
 399        u16 cmode;
 400        u16 reg;
 401        int err;
 402
 403        if (port != 9 && port != 10)
 404                return -EOPNOTSUPP;
 405
 406        /* Default to a slow mode, so freeing up SERDES interfaces for
 407         * other ports which might use them for SFPs.
 408         */
 409        if (mode == PHY_INTERFACE_MODE_NA)
 410                mode = PHY_INTERFACE_MODE_1000BASEX;
 411
 412        switch (mode) {
 413        case PHY_INTERFACE_MODE_1000BASEX:
 414                cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X;
 415                break;
 416        case PHY_INTERFACE_MODE_SGMII:
 417                cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
 418                break;
 419        case PHY_INTERFACE_MODE_2500BASEX:
 420                cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
 421                break;
 422        case PHY_INTERFACE_MODE_XGMII:
 423        case PHY_INTERFACE_MODE_XAUI:
 424                cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
 425                break;
 426        case PHY_INTERFACE_MODE_RXAUI:
 427                cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
 428                break;
 429        default:
 430                cmode = 0;
 431        }
 432
 433        /* cmode doesn't change, nothing to do for us */
 434        if (cmode == chip->ports[port].cmode)
 435                return 0;
 436
 437        lane = mv88e6390x_serdes_get_lane(chip, port);
 438        if (lane < 0 && lane != -ENODEV)
 439                return lane;
 440
 441        if (lane >= 0) {
 442                if (chip->ports[port].serdes_irq) {
 443                        err = mv88e6390_serdes_irq_disable(chip, port, lane);
 444                        if (err)
 445                                return err;
 446                }
 447
 448                err = mv88e6390x_serdes_power(chip, port, false);
 449                if (err)
 450                        return err;
 451        }
 452
 453        chip->ports[port].cmode = 0;
 454
 455        if (cmode) {
 456                err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 457                if (err)
 458                        return err;
 459
 460                reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
 461                reg |= cmode;
 462
 463                err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
 464                if (err)
 465                        return err;
 466
 467                chip->ports[port].cmode = cmode;
 468
 469                lane = mv88e6390x_serdes_get_lane(chip, port);
 470                if (lane < 0)
 471                        return lane;
 472
 473                err = mv88e6390x_serdes_power(chip, port, true);
 474                if (err)
 475                        return err;
 476
 477                if (chip->ports[port].serdes_irq) {
 478                        err = mv88e6390_serdes_irq_enable(chip, port, lane);
 479                        if (err)
 480                                return err;
 481                }
 482        }
 483
 484        return 0;
 485}
 486
 487int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 488                             phy_interface_t mode)
 489{
 490        switch (mode) {
 491        case PHY_INTERFACE_MODE_NA:
 492                return 0;
 493        case PHY_INTERFACE_MODE_XGMII:
 494        case PHY_INTERFACE_MODE_XAUI:
 495        case PHY_INTERFACE_MODE_RXAUI:
 496                return -EINVAL;
 497        default:
 498                break;
 499        }
 500
 501        return mv88e6390x_port_set_cmode(chip, port, mode);
 502}
 503
 504int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
 505{
 506        int err;
 507        u16 reg;
 508
 509        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 510        if (err)
 511                return err;
 512
 513        *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
 514
 515        return 0;
 516}
 517
 518int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
 519{
 520        int err;
 521        u16 reg;
 522
 523        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 524        if (err)
 525                return err;
 526
 527        *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
 528
 529        return 0;
 530}
 531
 532int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
 533                              struct phylink_link_state *state)
 534{
 535        int err;
 536        u16 reg;
 537
 538        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 539        if (err)
 540                return err;
 541
 542        if (port < 5) {
 543                switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
 544                case MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF:
 545                        state->speed = SPEED_10;
 546                        state->duplex = DUPLEX_HALF;
 547                        break;
 548                case MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF:
 549                        state->speed = SPEED_100;
 550                        state->duplex = DUPLEX_HALF;
 551                        break;
 552                case MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL:
 553                        state->speed = SPEED_10;
 554                        state->duplex = DUPLEX_FULL;
 555                        break;
 556                case MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL:
 557                        state->speed = SPEED_100;
 558                        state->duplex = DUPLEX_FULL;
 559                        break;
 560                default:
 561                        state->speed = SPEED_UNKNOWN;
 562                        state->duplex = DUPLEX_UNKNOWN;
 563                        break;
 564                }
 565        } else {
 566                switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
 567                case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF:
 568                        state->speed = SPEED_10;
 569                        state->duplex = DUPLEX_HALF;
 570                        break;
 571                case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF:
 572                        state->speed = SPEED_100;
 573                        state->duplex = DUPLEX_HALF;
 574                        break;
 575                case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL:
 576                        state->speed = SPEED_10;
 577                        state->duplex = DUPLEX_FULL;
 578                        break;
 579                case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL:
 580                        state->speed = SPEED_100;
 581                        state->duplex = DUPLEX_FULL;
 582                        break;
 583                default:
 584                        state->speed = SPEED_UNKNOWN;
 585                        state->duplex = DUPLEX_UNKNOWN;
 586                        break;
 587                }
 588        }
 589
 590        state->link = !!(reg & MV88E6250_PORT_STS_LINK);
 591        state->an_enabled = 1;
 592        state->an_complete = state->link;
 593
 594        return 0;
 595}
 596
 597int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
 598                              struct phylink_link_state *state)
 599{
 600        int err;
 601        u16 reg;
 602
 603        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 604        if (err)
 605                return err;
 606
 607        switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) {
 608        case MV88E6XXX_PORT_STS_SPEED_10:
 609                state->speed = SPEED_10;
 610                break;
 611        case MV88E6XXX_PORT_STS_SPEED_100:
 612                state->speed = SPEED_100;
 613                break;
 614        case MV88E6XXX_PORT_STS_SPEED_1000:
 615                state->speed = SPEED_1000;
 616                break;
 617        case MV88E6XXX_PORT_STS_SPEED_10000:
 618                if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) ==
 619                    MV88E6XXX_PORT_STS_CMODE_2500BASEX)
 620                        state->speed = SPEED_2500;
 621                else
 622                        state->speed = SPEED_10000;
 623                break;
 624        }
 625
 626        state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ?
 627                        DUPLEX_FULL : DUPLEX_HALF;
 628        state->link = !!(reg & MV88E6XXX_PORT_STS_LINK);
 629        state->an_enabled = 1;
 630        state->an_complete = state->link;
 631
 632        return 0;
 633}
 634
 635int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
 636                              struct phylink_link_state *state)
 637{
 638        if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
 639                u8 cmode = chip->ports[port].cmode;
 640
 641                /* When a port is in "Cross-chip serdes" mode, it uses
 642                 * 1000Base-X full duplex mode, but there is no automatic
 643                 * link detection. Use the sync OK status for link (as it
 644                 * would do for 1000Base-X mode.)
 645                 */
 646                if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) {
 647                        u16 mac;
 648                        int err;
 649
 650                        err = mv88e6xxx_port_read(chip, port,
 651                                                  MV88E6XXX_PORT_MAC_CTL, &mac);
 652                        if (err)
 653                                return err;
 654
 655                        state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK);
 656                        state->an_enabled = 1;
 657                        state->an_complete =
 658                                !!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE);
 659                        state->duplex =
 660                                state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN;
 661                        state->speed =
 662                                state->link ? SPEED_1000 : SPEED_UNKNOWN;
 663
 664                        return 0;
 665                }
 666        }
 667
 668        return mv88e6352_port_link_state(chip, port, state);
 669}
 670
 671/* Offset 0x02: Jamming Control
 672 *
 673 * Do not limit the period of time that this port can be paused for by
 674 * the remote end or the period of time that this port can pause the
 675 * remote end.
 676 */
 677int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 678                               u8 out)
 679{
 680        return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
 681                                    out << 8 | in);
 682}
 683
 684int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 685                               u8 out)
 686{
 687        int err;
 688
 689        err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
 690                                   MV88E6390_PORT_FLOW_CTL_UPDATE |
 691                                   MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
 692        if (err)
 693                return err;
 694
 695        return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
 696                                    MV88E6390_PORT_FLOW_CTL_UPDATE |
 697                                    MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
 698}
 699
 700/* Offset 0x04: Port Control Register */
 701
 702static const char * const mv88e6xxx_port_state_names[] = {
 703        [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
 704        [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
 705        [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
 706        [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
 707};
 708
 709int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
 710{
 711        u16 reg;
 712        int err;
 713
 714        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 715        if (err)
 716                return err;
 717
 718        reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
 719
 720        switch (state) {
 721        case BR_STATE_DISABLED:
 722                state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
 723                break;
 724        case BR_STATE_BLOCKING:
 725        case BR_STATE_LISTENING:
 726                state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
 727                break;
 728        case BR_STATE_LEARNING:
 729                state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
 730                break;
 731        case BR_STATE_FORWARDING:
 732                state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
 733                break;
 734        default:
 735                return -EINVAL;
 736        }
 737
 738        reg |= state;
 739
 740        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 741        if (err)
 742                return err;
 743
 744        dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
 745                mv88e6xxx_port_state_names[state]);
 746
 747        return 0;
 748}
 749
 750int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
 751                                   enum mv88e6xxx_egress_mode mode)
 752{
 753        int err;
 754        u16 reg;
 755
 756        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 757        if (err)
 758                return err;
 759
 760        reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
 761
 762        switch (mode) {
 763        case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
 764                reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
 765                break;
 766        case MV88E6XXX_EGRESS_MODE_UNTAGGED:
 767                reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
 768                break;
 769        case MV88E6XXX_EGRESS_MODE_TAGGED:
 770                reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
 771                break;
 772        case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
 773                reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
 774                break;
 775        default:
 776                return -EINVAL;
 777        }
 778
 779        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 780}
 781
 782int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 783                                  enum mv88e6xxx_frame_mode mode)
 784{
 785        int err;
 786        u16 reg;
 787
 788        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 789        if (err)
 790                return err;
 791
 792        reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
 793
 794        switch (mode) {
 795        case MV88E6XXX_FRAME_MODE_NORMAL:
 796                reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
 797                break;
 798        case MV88E6XXX_FRAME_MODE_DSA:
 799                reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
 800                break;
 801        default:
 802                return -EINVAL;
 803        }
 804
 805        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 806}
 807
 808int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 809                                  enum mv88e6xxx_frame_mode mode)
 810{
 811        int err;
 812        u16 reg;
 813
 814        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 815        if (err)
 816                return err;
 817
 818        reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
 819
 820        switch (mode) {
 821        case MV88E6XXX_FRAME_MODE_NORMAL:
 822                reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
 823                break;
 824        case MV88E6XXX_FRAME_MODE_DSA:
 825                reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
 826                break;
 827        case MV88E6XXX_FRAME_MODE_PROVIDER:
 828                reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
 829                break;
 830        case MV88E6XXX_FRAME_MODE_ETHERTYPE:
 831                reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
 832                break;
 833        default:
 834                return -EINVAL;
 835        }
 836
 837        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 838}
 839
 840static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
 841                                              int port, bool unicast)
 842{
 843        int err;
 844        u16 reg;
 845
 846        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 847        if (err)
 848                return err;
 849
 850        if (unicast)
 851                reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
 852        else
 853                reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
 854
 855        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 856}
 857
 858int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
 859                                     bool unicast, bool multicast)
 860{
 861        int err;
 862        u16 reg;
 863
 864        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 865        if (err)
 866                return err;
 867
 868        reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
 869
 870        if (unicast && multicast)
 871                reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
 872        else if (unicast)
 873                reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
 874        else if (multicast)
 875                reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
 876        else
 877                reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
 878
 879        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 880}
 881
 882/* Offset 0x05: Port Control 1 */
 883
 884int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
 885                                    bool message_port)
 886{
 887        u16 val;
 888        int err;
 889
 890        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
 891        if (err)
 892                return err;
 893
 894        if (message_port)
 895                val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
 896        else
 897                val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
 898
 899        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
 900}
 901
 902/* Offset 0x06: Port Based VLAN Map */
 903
 904int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
 905{
 906        const u16 mask = mv88e6xxx_port_mask(chip);
 907        u16 reg;
 908        int err;
 909
 910        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
 911        if (err)
 912                return err;
 913
 914        reg &= ~mask;
 915        reg |= map & mask;
 916
 917        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
 918        if (err)
 919                return err;
 920
 921        dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
 922
 923        return 0;
 924}
 925
 926int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
 927{
 928        const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
 929        u16 reg;
 930        int err;
 931
 932        /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
 933        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
 934        if (err)
 935                return err;
 936
 937        *fid = (reg & 0xf000) >> 12;
 938
 939        /* Port's default FID upper bits are located in reg 0x05, offset 0 */
 940        if (upper_mask) {
 941                err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
 942                                          &reg);
 943                if (err)
 944                        return err;
 945
 946                *fid |= (reg & upper_mask) << 4;
 947        }
 948
 949        return 0;
 950}
 951
 952int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
 953{
 954        const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
 955        u16 reg;
 956        int err;
 957
 958        if (fid >= mv88e6xxx_num_databases(chip))
 959                return -EINVAL;
 960
 961        /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
 962        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
 963        if (err)
 964                return err;
 965
 966        reg &= 0x0fff;
 967        reg |= (fid & 0x000f) << 12;
 968
 969        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
 970        if (err)
 971                return err;
 972
 973        /* Port's default FID upper bits are located in reg 0x05, offset 0 */
 974        if (upper_mask) {
 975                err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
 976                                          &reg);
 977                if (err)
 978                        return err;
 979
 980                reg &= ~upper_mask;
 981                reg |= (fid >> 4) & upper_mask;
 982
 983                err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
 984                                           reg);
 985                if (err)
 986                        return err;
 987        }
 988
 989        dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
 990
 991        return 0;
 992}
 993
 994/* Offset 0x07: Default Port VLAN ID & Priority */
 995
 996int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
 997{
 998        u16 reg;
 999        int err;
1000

1001        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1002                                  &reg);
1003        if (err)
1004                return err;
1005
1006        *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1007
1008        return 0;
1009}
1010
1011int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1012{
1013        u16 reg;
1014        int err;
1015
1016        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1017                                  &reg);
1018        if (err)
1019                return err;
1020
1021        reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1022        reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1023
1024        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1025                                   reg);
1026        if (err)
1027                return err;
1028
1029        dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1030
1031        return 0;
1032}
1033
1034/* Offset 0x08: Port Control 2 Register */
1035
1036static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1037        [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1038        [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1039        [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1040        [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1041};
1042
1043static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1044                                              int port, bool multicast)
1045{
1046        int err;
1047        u16 reg;
1048
1049        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1050        if (err)
1051                return err;
1052
1053        if (multicast)
1054                reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1055        else
1056                reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1057
1058        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1059}
1060
1061int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
1062                                     bool unicast, bool multicast)
1063{
1064        int err;
1065
1066        err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
1067        if (err)
1068                return err;
1069
1070        return mv88e6185_port_set_default_forward(chip, port, multicast);
1071}
1072
1073int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1074                                     int upstream_port)
1075{
1076        int err;
1077        u16 reg;
1078
1079        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1080        if (err)
1081                return err;
1082
1083        reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1084        reg |= upstream_port;
1085
1086        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1087}
1088
1089int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1090                                  u16 mode)
1091{
1092        u16 reg;
1093        int err;
1094
1095        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1096        if (err)
1097                return err;
1098
1099        reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1100        reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1101
1102        err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1103        if (err)
1104                return err;
1105
1106        dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1107                mv88e6xxx_port_8021q_mode_names[mode]);
1108
1109        return 0;
1110}
1111
1112int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
1113{
1114        u16 reg;
1115        int err;
1116
1117        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1118        if (err)
1119                return err;
1120
1121        reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1122
1123        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1124}
1125
1126int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1127                                  size_t size)
1128{
1129        u16 reg;
1130        int err;
1131
1132        err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1133        if (err)
1134                return err;
1135
1136        reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1137
1138        if (size <= 1522)
1139                reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1140        else if (size <= 2048)
1141                reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1142        else if (size <= 10240)
1143                reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1144        else
1145                return -ERANGE;
1146
1147        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1148}
1149
1150/* Offset 0x09: Port Rate Control */
1151
1152int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1153{
1154        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1155                                    0x0000);
1156}
1157
1158int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1159{
1160        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1161                                    0x0001);
1162}
1163
1164/* Offset 0x0C: Port ATU Control */
1165
1166int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1167{
1168        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1169}
1170
1171/* Offset 0x0D: (Priority) Override Register */
1172
1173int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1174{
1175        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1176}
1177
1178/* Offset 0x0f: Port Ether type */
1179
1180int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1181                                  u16 etype)
1182{
1183        return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1184}
1185
1186/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1187 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1188 */
1189
1190int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1191{
1192        int err;
1193
1194        /* Use a direct priority mapping for all IEEE tagged frames */
1195        err = mv88e6xxx_port_write(chip, port,
1196                                   MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1197                                   0x3210);
1198        if (err)
1199                return err;
1200
1201        return mv88e6xxx_port_write(chip, port,
1202                                    MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1203                                    0x7654);
1204}
1205
1206static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1207                                        int port, u16 table, u8 ptr, u16 data)
1208{
1209        u16 reg;
1210
1211        reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1212                (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1213                (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1214
1215        return mv88e6xxx_port_write(chip, port,
1216                                    MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1217}
1218
1219int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1220{
1221        int err, i;
1222        u16 table;
1223
1224        for (i = 0; i <= 7; i++) {
1225                table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1226                err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1227                                                   (i | i << 4));
1228                if (err)
1229                        return err;
1230
1231                table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1232                err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1233                if (err)
1234                        return err;
1235
1236                table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1237                err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1238                if (err)
1239                        return err;
1240
1241                table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1242                err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1243                if (err)
1244                        return err;
1245        }
1246
1247        return 0;
1248}
1249