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31
32#ifndef _ENA_ADMIN_H_
33#define _ENA_ADMIN_H_
34
35
36enum ena_admin_aq_opcode {
37 ENA_ADMIN_CREATE_SQ = 1,
38 ENA_ADMIN_DESTROY_SQ = 2,
39 ENA_ADMIN_CREATE_CQ = 3,
40 ENA_ADMIN_DESTROY_CQ = 4,
41 ENA_ADMIN_GET_FEATURE = 8,
42 ENA_ADMIN_SET_FEATURE = 9,
43 ENA_ADMIN_GET_STATS = 11,
44};
45
46enum ena_admin_aq_completion_status {
47 ENA_ADMIN_SUCCESS = 0,
48 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
49 ENA_ADMIN_BAD_OPCODE = 2,
50 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
51 ENA_ADMIN_MALFORMED_REQUEST = 4,
52
53 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
54 ENA_ADMIN_UNKNOWN_ERROR = 6,
55 ENA_ADMIN_RESOURCE_BUSY = 7,
56};
57
58enum ena_admin_aq_feature_id {
59 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
60 ENA_ADMIN_MAX_QUEUES_NUM = 2,
61 ENA_ADMIN_HW_HINTS = 3,
62 ENA_ADMIN_LLQ = 4,
63 ENA_ADMIN_MAX_QUEUES_EXT = 7,
64 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
65 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
66 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
67 ENA_ADMIN_MTU = 14,
68 ENA_ADMIN_RSS_HASH_INPUT = 18,
69 ENA_ADMIN_INTERRUPT_MODERATION = 20,
70 ENA_ADMIN_AENQ_CONFIG = 26,
71 ENA_ADMIN_LINK_CONFIG = 27,
72 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
73 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
74};
75
76enum ena_admin_placement_policy_type {
77
78 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
79
80
81
82 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
83};
84
85enum ena_admin_link_types {
86 ENA_ADMIN_LINK_SPEED_1G = 0x1,
87 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
88 ENA_ADMIN_LINK_SPEED_5G = 0x4,
89 ENA_ADMIN_LINK_SPEED_10G = 0x8,
90 ENA_ADMIN_LINK_SPEED_25G = 0x10,
91 ENA_ADMIN_LINK_SPEED_40G = 0x20,
92 ENA_ADMIN_LINK_SPEED_50G = 0x40,
93 ENA_ADMIN_LINK_SPEED_100G = 0x80,
94 ENA_ADMIN_LINK_SPEED_200G = 0x100,
95 ENA_ADMIN_LINK_SPEED_400G = 0x200,
96};
97
98enum ena_admin_completion_policy_type {
99
100 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
101
102 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
103
104
105
106 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
107
108
109
110 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
111};
112
113
114
115
116
117enum ena_admin_get_stats_type {
118 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
119 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
120};
121
122enum ena_admin_get_stats_scope {
123 ENA_ADMIN_SPECIFIC_QUEUE = 0,
124 ENA_ADMIN_ETH_TRAFFIC = 1,
125};
126
127struct ena_admin_aq_common_desc {
128
129
130
131 u16 command_id;
132
133
134 u8 opcode;
135
136
137
138
139
140
141
142
143 u8 flags;
144};
145
146
147
148
149
150struct ena_admin_ctrl_buff_info {
151 u32 length;
152
153 struct ena_common_mem_addr address;
154};
155
156struct ena_admin_sq {
157 u16 sq_idx;
158
159
160
161
162 u8 sq_identity;
163
164 u8 reserved1;
165};
166
167struct ena_admin_aq_entry {
168 struct ena_admin_aq_common_desc aq_common_descriptor;
169
170 union {
171 u32 inline_data_w1[3];
172
173 struct ena_admin_ctrl_buff_info control_buffer;
174 } u;
175
176 u32 inline_data_w4[12];
177};
178
179struct ena_admin_acq_common_desc {
180
181
182
183
184 u16 command;
185
186 u8 status;
187
188
189
190
191 u8 flags;
192
193 u16 extended_status;
194
195
196
197
198 u16 sq_head_indx;
199};
200
201struct ena_admin_acq_entry {
202 struct ena_admin_acq_common_desc acq_common_descriptor;
203
204 u32 response_specific_data[14];
205};
206
207struct ena_admin_aq_create_sq_cmd {
208 struct ena_admin_aq_common_desc aq_common_descriptor;
209
210
211
212
213 u8 sq_identity;
214
215 u8 reserved8_w1;
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232 u8 sq_caps_2;
233
234
235
236
237
238
239 u8 sq_caps_3;
240
241
242
243
244 u16 cq_idx;
245
246
247 u16 sq_depth;
248
249
250
251
252 struct ena_common_mem_addr sq_ba;
253
254
255
256
257
258 struct ena_common_mem_addr sq_head_writeback;
259
260 u32 reserved0_w7;
261
262 u32 reserved0_w8;
263};
264
265enum ena_admin_sq_direction {
266 ENA_ADMIN_SQ_DIRECTION_TX = 1,
267 ENA_ADMIN_SQ_DIRECTION_RX = 2,
268};
269
270struct ena_admin_acq_create_sq_resp_desc {
271 struct ena_admin_acq_common_desc acq_common_desc;
272
273 u16 sq_idx;
274
275 u16 reserved;
276
277
278 u32 sq_doorbell_offset;
279
280
281
282
283 u32 llq_descriptors_offset;
284
285
286
287
288 u32 llq_headers_offset;
289};
290
291struct ena_admin_aq_destroy_sq_cmd {
292 struct ena_admin_aq_common_desc aq_common_descriptor;
293
294 struct ena_admin_sq sq;
295};
296
297struct ena_admin_acq_destroy_sq_resp_desc {
298 struct ena_admin_acq_common_desc acq_common_desc;
299};
300
301struct ena_admin_aq_create_cq_cmd {
302 struct ena_admin_aq_common_desc aq_common_descriptor;
303
304
305
306
307
308
309 u8 cq_caps_1;
310
311
312
313
314
315 u8 cq_caps_2;
316
317
318 u16 cq_depth;
319
320
321 u32 msix_vector;
322
323
324
325
326 struct ena_common_mem_addr cq_ba;
327};
328
329struct ena_admin_acq_create_cq_resp_desc {
330 struct ena_admin_acq_common_desc acq_common_desc;
331
332 u16 cq_idx;
333
334
335 u16 cq_actual_depth;
336
337 u32 numa_node_register_offset;
338
339 u32 cq_head_db_register_offset;
340
341 u32 cq_interrupt_unmask_register_offset;
342};
343
344struct ena_admin_aq_destroy_cq_cmd {
345 struct ena_admin_aq_common_desc aq_common_descriptor;
346
347 u16 cq_idx;
348
349 u16 reserved1;
350};
351
352struct ena_admin_acq_destroy_cq_resp_desc {
353 struct ena_admin_acq_common_desc acq_common_desc;
354};
355
356
357
358
359struct ena_admin_aq_get_stats_cmd {
360 struct ena_admin_aq_common_desc aq_common_descriptor;
361
362 union {
363
364 u32 inline_data_w1[3];
365
366 struct ena_admin_ctrl_buff_info control_buffer;
367 } u;
368
369
370 u8 type;
371
372
373 u8 scope;
374
375 u16 reserved3;
376
377
378 u16 queue_idx;
379
380
381
382
383 u16 device_id;
384};
385
386
387struct ena_admin_basic_stats {
388 u32 tx_bytes_low;
389
390 u32 tx_bytes_high;
391
392 u32 tx_pkts_low;
393
394 u32 tx_pkts_high;
395
396 u32 rx_bytes_low;
397
398 u32 rx_bytes_high;
399
400 u32 rx_pkts_low;
401
402 u32 rx_pkts_high;
403
404 u32 rx_drops_low;
405
406 u32 rx_drops_high;
407};
408
409struct ena_admin_acq_get_stats_resp {
410 struct ena_admin_acq_common_desc acq_common_desc;
411
412 struct ena_admin_basic_stats basic_stats;
413};
414
415struct ena_admin_get_set_feature_common_desc {
416
417
418
419
420 u8 flags;
421
422
423 u8 feature_id;
424
425
426
427
428
429 u8 feature_version;
430
431 u8 reserved8;
432};
433
434struct ena_admin_device_attr_feature_desc {
435 u32 impl_id;
436
437 u32 device_version;
438
439
440 u32 supported_features;
441
442 u32 reserved3;
443
444
445 u32 phys_addr_width;
446
447
448 u32 virt_addr_width;
449
450
451 u8 mac_addr[6];
452
453 u8 reserved7[2];
454
455 u32 max_mtu;
456};
457
458enum ena_admin_llq_header_location {
459
460 ENA_ADMIN_INLINE_HEADER = 1,
461
462 ENA_ADMIN_HEADER_RING = 2,
463};
464
465enum ena_admin_llq_ring_entry_size {
466 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
467 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
468 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
469};
470
471enum ena_admin_llq_num_descs_before_header {
472 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
473 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
474 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
475 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
476 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
477};
478
479
480
481
482
483
484
485enum ena_admin_llq_stride_ctrl {
486 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
487 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
488};
489
490struct ena_admin_feature_llq_desc {
491 u32 max_llq_num;
492
493 u32 max_llq_depth;
494
495
496
497
498 u16 header_location_ctrl_supported;
499
500
501 u16 header_location_ctrl_enabled;
502
503
504
505
506
507
508
509 u16 entry_size_ctrl_supported;
510
511
512 u16 entry_size_ctrl_enabled;
513
514
515
516
517
518
519
520
521
522 u16 desc_num_before_header_supported;
523
524
525 u16 desc_num_before_header_enabled;
526
527
528
529
530 u16 descriptors_stride_ctrl_supported;
531
532
533 u16 descriptors_stride_ctrl_enabled;
534
535
536
537
538 u32 max_tx_burst_size;
539};
540
541struct ena_admin_queue_ext_feature_fields {
542 u32 max_tx_sq_num;
543
544 u32 max_tx_cq_num;
545
546 u32 max_rx_sq_num;
547
548 u32 max_rx_cq_num;
549
550 u32 max_tx_sq_depth;
551
552 u32 max_tx_cq_depth;
553
554 u32 max_rx_sq_depth;
555
556 u32 max_rx_cq_depth;
557
558 u32 max_tx_header_size;
559
560
561
562
563 u16 max_per_packet_tx_descs;
564
565
566 u16 max_per_packet_rx_descs;
567};
568
569struct ena_admin_queue_feature_desc {
570 u32 max_sq_num;
571
572 u32 max_sq_depth;
573
574 u32 max_cq_num;
575
576 u32 max_cq_depth;
577
578 u32 max_legacy_llq_num;
579
580 u32 max_legacy_llq_depth;
581
582 u32 max_header_size;
583
584
585
586
587 u16 max_packet_tx_descs;
588
589
590 u16 max_packet_rx_descs;
591};
592
593struct ena_admin_set_feature_mtu_desc {
594
595 u32 mtu;
596};
597
598struct ena_admin_set_feature_host_attr_desc {
599
600
601
602 struct ena_common_mem_addr os_info_ba;
603
604
605
606
607 struct ena_common_mem_addr debug_ba;
608
609
610 u32 debug_area_size;
611};
612
613struct ena_admin_feature_intr_moder_desc {
614
615 u16 intr_delay_resolution;
616
617 u16 reserved;
618};
619
620struct ena_admin_get_feature_link_desc {
621
622 u32 speed;
623
624
625 u32 supported;
626
627
628
629
630
631 u32 flags;
632};
633
634struct ena_admin_feature_aenq_desc {
635
636 u32 supported_groups;
637
638
639 u32 enabled_groups;
640};
641
642struct ena_admin_feature_offload_desc {
643
644
645
646
647
648
649
650
651
652
653
654 u32 tx;
655
656
657
658
659
660
661
662 u32 rx_supported;
663
664 u32 rx_enabled;
665};
666
667enum ena_admin_hash_functions {
668 ENA_ADMIN_TOEPLITZ = 1,
669 ENA_ADMIN_CRC32 = 2,
670};
671
672struct ena_admin_feature_rss_flow_hash_control {
673 u32 keys_num;
674
675 u32 reserved;
676
677 u32 key[10];
678};
679
680struct ena_admin_feature_rss_flow_hash_function {
681
682 u32 supported_func;
683
684
685
686
687 u32 selected_func;
688
689
690 u32 init_val;
691};
692
693
694enum ena_admin_flow_hash_proto {
695 ENA_ADMIN_RSS_TCP4 = 0,
696 ENA_ADMIN_RSS_UDP4 = 1,
697 ENA_ADMIN_RSS_TCP6 = 2,
698 ENA_ADMIN_RSS_UDP6 = 3,
699 ENA_ADMIN_RSS_IP4 = 4,
700 ENA_ADMIN_RSS_IP6 = 5,
701 ENA_ADMIN_RSS_IP4_FRAG = 6,
702 ENA_ADMIN_RSS_NOT_IP = 7,
703
704 ENA_ADMIN_RSS_TCP6_EX = 8,
705
706 ENA_ADMIN_RSS_IP6_EX = 9,
707 ENA_ADMIN_RSS_PROTO_NUM = 16,
708};
709
710
711enum ena_admin_flow_hash_fields {
712
713 ENA_ADMIN_RSS_L2_DA = BIT(0),
714
715 ENA_ADMIN_RSS_L2_SA = BIT(1),
716
717 ENA_ADMIN_RSS_L3_DA = BIT(2),
718
719 ENA_ADMIN_RSS_L3_SA = BIT(3),
720
721 ENA_ADMIN_RSS_L4_DP = BIT(4),
722
723 ENA_ADMIN_RSS_L4_SP = BIT(5),
724};
725
726struct ena_admin_proto_input {
727
728 u16 fields;
729
730 u16 reserved2;
731};
732
733struct ena_admin_feature_rss_hash_control {
734 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
735
736 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
737
738 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
739
740 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
741};
742
743struct ena_admin_feature_rss_flow_hash_input {
744
745
746
747
748
749
750 u16 supported_input_sort;
751
752
753
754
755
756
757
758 u16 enabled_input_sort;
759};
760
761enum ena_admin_os_type {
762 ENA_ADMIN_OS_LINUX = 1,
763 ENA_ADMIN_OS_WIN = 2,
764 ENA_ADMIN_OS_DPDK = 3,
765 ENA_ADMIN_OS_FREEBSD = 4,
766 ENA_ADMIN_OS_IPXE = 5,
767 ENA_ADMIN_OS_ESXI = 6,
768 ENA_ADMIN_OS_GROUPS_NUM = 6,
769};
770
771struct ena_admin_host_info {
772
773 u32 os_type;
774
775
776 u8 os_dist_str[128];
777
778
779 u32 os_dist;
780
781
782 u8 kernel_ver_str[32];
783
784
785 u32 kernel_ver;
786
787
788
789
790
791
792 u32 driver_version;
793
794
795 u32 supported_network_features[2];
796
797
798 u16 ena_spec_version;
799
800
801
802
803
804
805 u16 bdf;
806
807
808 u16 num_cpus;
809
810 u16 reserved;
811};
812
813struct ena_admin_rss_ind_table_entry {
814 u16 cq_idx;
815
816 u16 reserved;
817};
818
819struct ena_admin_feature_rss_ind_table {
820
821 u16 min_size;
822
823
824 u16 max_size;
825
826
827 u16 size;
828
829 u16 reserved;
830
831
832 u32 inline_index;
833
834
835
836
837 struct ena_admin_rss_ind_table_entry inline_entry;
838};
839
840
841struct ena_admin_ena_hw_hints {
842
843 u16 mmio_read_timeout;
844
845
846 u16 driver_watchdog_timeout;
847
848
849 u16 missing_tx_completion_timeout;
850
851 u16 missed_tx_completion_count_threshold_to_reset;
852
853
854 u16 admin_completion_tx_timeout;
855
856 u16 netdev_wd_timeout;
857
858 u16 max_tx_sgl_size;
859
860 u16 max_rx_sgl_size;
861
862 u16 reserved[8];
863};
864
865struct ena_admin_get_feat_cmd {
866 struct ena_admin_aq_common_desc aq_common_descriptor;
867
868 struct ena_admin_ctrl_buff_info control_buffer;
869
870 struct ena_admin_get_set_feature_common_desc feat_common;
871
872 u32 raw[11];
873};
874
875struct ena_admin_queue_ext_feature_desc {
876
877 u8 version;
878
879 u8 reserved1[3];
880
881 union {
882 struct ena_admin_queue_ext_feature_fields max_queue_ext;
883
884 u32 raw[10];
885 };
886};
887
888struct ena_admin_get_feat_resp {
889 struct ena_admin_acq_common_desc acq_common_desc;
890
891 union {
892 u32 raw[14];
893
894 struct ena_admin_device_attr_feature_desc dev_attr;
895
896 struct ena_admin_feature_llq_desc llq;
897
898 struct ena_admin_queue_feature_desc max_queue;
899
900 struct ena_admin_queue_ext_feature_desc max_queue_ext;
901
902 struct ena_admin_feature_aenq_desc aenq;
903
904 struct ena_admin_get_feature_link_desc link;
905
906 struct ena_admin_feature_offload_desc offload;
907
908 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
909
910 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
911
912 struct ena_admin_feature_rss_ind_table ind_table;
913
914 struct ena_admin_feature_intr_moder_desc intr_moderation;
915
916 struct ena_admin_ena_hw_hints hw_hints;
917 } u;
918};
919
920struct ena_admin_set_feat_cmd {
921 struct ena_admin_aq_common_desc aq_common_descriptor;
922
923 struct ena_admin_ctrl_buff_info control_buffer;
924
925 struct ena_admin_get_set_feature_common_desc feat_common;
926
927 union {
928 u32 raw[11];
929
930
931 struct ena_admin_set_feature_mtu_desc mtu;
932
933
934 struct ena_admin_set_feature_host_attr_desc host_attr;
935
936
937 struct ena_admin_feature_aenq_desc aenq;
938
939
940 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
941
942
943 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
944
945
946 struct ena_admin_feature_rss_ind_table ind_table;
947
948
949 struct ena_admin_feature_llq_desc llq;
950 } u;
951};
952
953struct ena_admin_set_feat_resp {
954 struct ena_admin_acq_common_desc acq_common_desc;
955
956 union {
957 u32 raw[14];
958 } u;
959};
960
961struct ena_admin_aenq_common_desc {
962 u16 group;
963
964 u16 syndrom;
965
966
967
968
969 u8 flags;
970
971 u8 reserved1[3];
972
973 u32 timestamp_low;
974
975 u32 timestamp_high;
976};
977
978
979enum ena_admin_aenq_group {
980 ENA_ADMIN_LINK_CHANGE = 0,
981 ENA_ADMIN_FATAL_ERROR = 1,
982 ENA_ADMIN_WARNING = 2,
983 ENA_ADMIN_NOTIFICATION = 3,
984 ENA_ADMIN_KEEP_ALIVE = 4,
985 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
986};
987
988enum ena_admin_aenq_notification_syndrom {
989 ENA_ADMIN_SUSPEND = 0,
990 ENA_ADMIN_RESUME = 1,
991 ENA_ADMIN_UPDATE_HINTS = 2,
992};
993
994struct ena_admin_aenq_entry {
995 struct ena_admin_aenq_common_desc aenq_common_desc;
996
997
998 u32 inline_data_w4[12];
999};
1000
1001struct ena_admin_aenq_link_change_desc {
1002 struct ena_admin_aenq_common_desc aenq_common_desc;
1003
1004
1005 u32 flags;
1006};
1007
1008struct ena_admin_aenq_keep_alive_desc {
1009 struct ena_admin_aenq_common_desc aenq_common_desc;
1010
1011 u32 rx_drops_low;
1012
1013 u32 rx_drops_high;
1014};
1015
1016struct ena_admin_ena_mmio_req_read_less_resp {
1017 u16 req_id;
1018
1019 u16 reg_off;
1020
1021
1022 u32 reg_val;
1023};
1024
1025
1026#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1027#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1028#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1029#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1030#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1031#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1032
1033
1034#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1035#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1036
1037
1038#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1039#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1040
1041
1042#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1043#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1044#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1045#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1046#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1047#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1048
1049
1050#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1051#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1052#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1053
1054
1055#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1056
1057
1058#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1059#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1060#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1061
1062
1063#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1064#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1065#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1066#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1067#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1068#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1069#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1070#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1071#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1072#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1073#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1074#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1075#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1076#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1077#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1078#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1079#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1080#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1081#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1082#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1083#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1084#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1085
1086
1087#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1088#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1089
1090
1091#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1092#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1093#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1094#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1095#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1096#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1097#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1098#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1099
1100
1101#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1102#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1103#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1104#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1105#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1106#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1107#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1108#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1109#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1110#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1111#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1112#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1113
1114
1115#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1116
1117
1118#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1119
1120#endif
1121