1/* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * DO NOT MODIFY!!! This file is automatically generated. 11 */ 12 13#ifndef _BNXT_HSI_H_ 14#define _BNXT_HSI_H_ 15 16/* hwrm_cmd_hdr (size:128b/16B) */ 17struct hwrm_cmd_hdr { 18 __le16 req_type; 19 __le16 cmpl_ring; 20 __le16 seq_id; 21 __le16 target_id; 22 __le64 resp_addr; 23}; 24 25/* hwrm_resp_hdr (size:64b/8B) */ 26struct hwrm_resp_hdr { 27 __le16 error_code; 28 __le16 req_type; 29 __le16 seq_id; 30 __le16 resp_len; 31}; 32 33#define CMD_DISCR_TLV_ENCAP 0x8000UL 34#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 35 36 37#define TLV_TYPE_HWRM_REQUEST 0x1UL 38#define TLV_TYPE_HWRM_RESPONSE 0x2UL 39#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 40#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 41#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 42#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL 43#define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL 44#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47#define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 48#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL 49#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 51 52 53/* tlv (size:64b/8B) */ 54struct tlv { 55 __le16 cmd_discr; 56 u8 reserved_8b; 57 u8 flags; 58 #define TLV_FLAGS_MORE 0x1UL 59 #define TLV_FLAGS_MORE_LAST 0x0UL 60 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 61 #define TLV_FLAGS_REQUIRED 0x2UL 62 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 63 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 64 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 65 __le16 tlv_type; 66 __le16 length; 67}; 68 69/* input (size:128b/16B) */ 70struct input { 71 __le16 req_type; 72 __le16 cmpl_ring; 73 __le16 seq_id; 74 __le16 target_id; 75 __le64 resp_addr; 76}; 77 78/* output (size:64b/8B) */ 79struct output { 80 __le16 error_code; 81 __le16 req_type; 82 __le16 seq_id; 83 __le16 resp_len; 84}; 85 86/* hwrm_short_input (size:128b/16B) */ 87struct hwrm_short_input { 88 __le16 req_type; 89 __le16 signature; 90 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 91 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 92 __le16 target_id; 93 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 94 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 95 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 96 __le16 size; 97 __le64 req_addr; 98}; 99 100/* cmd_nums (size:64b/8B) */ 101struct cmd_nums { 102 __le16 req_type; 103 #define HWRM_VER_GET 0x0UL 104 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 105 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 106 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 107 #define HWRM_FUNC_VF_CFG 0xfUL 108 #define HWRM_RESERVED1 0x10UL 109 #define HWRM_FUNC_RESET 0x11UL 110 #define HWRM_FUNC_GETFID 0x12UL 111 #define HWRM_FUNC_VF_ALLOC 0x13UL 112 #define HWRM_FUNC_VF_FREE 0x14UL 113 #define HWRM_FUNC_QCAPS 0x15UL 114 #define HWRM_FUNC_QCFG 0x16UL 115 #define HWRM_FUNC_CFG 0x17UL 116 #define HWRM_FUNC_QSTATS 0x18UL 117 #define HWRM_FUNC_CLR_STATS 0x19UL 118 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 119 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 120 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 121 #define HWRM_FUNC_DRV_RGTR 0x1dUL 122 #define HWRM_FUNC_DRV_QVER 0x1eUL 123 #define HWRM_FUNC_BUF_RGTR 0x1fUL 124 #define HWRM_PORT_PHY_CFG 0x20UL 125 #define HWRM_PORT_MAC_CFG 0x21UL 126 #define HWRM_PORT_TS_QUERY 0x22UL 127 #define HWRM_PORT_QSTATS 0x23UL 128 #define HWRM_PORT_LPBK_QSTATS 0x24UL 129 #define HWRM_PORT_CLR_STATS 0x25UL 130 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 131 #define HWRM_PORT_PHY_QCFG 0x27UL 132 #define HWRM_PORT_MAC_QCFG 0x28UL 133 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 134 #define HWRM_PORT_PHY_QCAPS 0x2aUL 135 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 136 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 137 #define HWRM_PORT_LED_CFG 0x2dUL 138 #define HWRM_PORT_LED_QCFG 0x2eUL 139 #define HWRM_PORT_LED_QCAPS 0x2fUL 140 #define HWRM_QUEUE_QPORTCFG 0x30UL 141 #define HWRM_QUEUE_QCFG 0x31UL 142 #define HWRM_QUEUE_CFG 0x32UL 143 #define HWRM_FUNC_VLAN_CFG 0x33UL 144 #define HWRM_FUNC_VLAN_QCFG 0x34UL 145 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 146 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 147 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 148 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 149 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 150 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 151 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 152 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 153 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 154 #define HWRM_VNIC_ALLOC 0x40UL 155 #define HWRM_VNIC_FREE 0x41UL 156 #define HWRM_VNIC_CFG 0x42UL 157 #define HWRM_VNIC_QCFG 0x43UL 158 #define HWRM_VNIC_TPA_CFG 0x44UL 159 #define HWRM_VNIC_TPA_QCFG 0x45UL 160 #define HWRM_VNIC_RSS_CFG 0x46UL 161 #define HWRM_VNIC_RSS_QCFG 0x47UL 162 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 163 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 164 #define HWRM_VNIC_QCAPS 0x4aUL 165 #define HWRM_RING_ALLOC 0x50UL 166 #define HWRM_RING_FREE 0x51UL 167 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 168 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 169 #define HWRM_RING_AGGINT_QCAPS 0x54UL 170 #define HWRM_RING_RESET 0x5eUL 171 #define HWRM_RING_GRP_ALLOC 0x60UL 172 #define HWRM_RING_GRP_FREE 0x61UL 173 #define HWRM_RESERVED5 0x64UL 174 #define HWRM_RESERVED6 0x65UL 175 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 176 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 177 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 178 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 179 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 180 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 181 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 182 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 183 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 184 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 185 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 186 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 187 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 188 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 189 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 190 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 191 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 192 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 193 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 194 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 195 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 196 #define HWRM_STAT_CTX_ALLOC 0xb0UL 197 #define HWRM_STAT_CTX_FREE 0xb1UL 198 #define HWRM_STAT_CTX_QUERY 0xb2UL 199 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 200 #define HWRM_PORT_QSTATS_EXT 0xb4UL 201 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 202 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 203 #define HWRM_FW_RESET 0xc0UL 204 #define HWRM_FW_QSTATUS 0xc1UL 205 #define HWRM_FW_HEALTH_CHECK 0xc2UL 206 #define HWRM_FW_SYNC 0xc3UL 207 #define HWRM_FW_SET_TIME 0xc8UL 208 #define HWRM_FW_GET_TIME 0xc9UL 209 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 210 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 211 #define HWRM_FW_IPC_MAILBOX 0xccUL 212 #define HWRM_EXEC_FWD_RESP 0xd0UL 213 #define HWRM_REJECT_FWD_RESP 0xd1UL 214 #define HWRM_FWD_RESP 0xd2UL 215 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 216 #define HWRM_OEM_CMD 0xd4UL 217 #define HWRM_PORT_PRBS_TEST 0xd5UL 218 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 219 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 220 #define HWRM_WOL_FILTER_FREE 0xf1UL 221 #define HWRM_WOL_FILTER_QCFG 0xf2UL 222 #define HWRM_WOL_REASON_QCFG 0xf3UL 223 #define HWRM_CFA_METER_QCAPS 0xf4UL 224 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 225 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 226 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 227 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 228 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 229 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 230 #define HWRM_CFA_VFR_ALLOC 0xfdUL 231 #define HWRM_CFA_VFR_FREE 0xfeUL 232 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 233 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 234 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 235 #define HWRM_CFA_FLOW_ALLOC 0x103UL 236 #define HWRM_CFA_FLOW_FREE 0x104UL 237 #define HWRM_CFA_FLOW_FLUSH 0x105UL 238 #define HWRM_CFA_FLOW_STATS 0x106UL 239 #define HWRM_CFA_FLOW_INFO 0x107UL 240 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 241 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 242 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 243 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 244 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 245 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 246 #define HWRM_CFA_PAIR_FREE 0x10eUL 247 #define HWRM_CFA_PAIR_INFO 0x10fUL 248 #define HWRM_FW_IPC_MSG 0x110UL 249 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 250 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 251 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 252 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 253 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 254 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 255 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 256 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 257 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 258 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 259 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 260 #define HWRM_CFA_COUNTER_CFG 0x11cUL 261 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 262 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 263 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 264 #define HWRM_CFA_EEM_QCAPS 0x120UL 265 #define HWRM_CFA_EEM_CFG 0x121UL 266 #define HWRM_CFA_EEM_QCFG 0x122UL 267 #define HWRM_CFA_EEM_OP 0x123UL 268 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 269 #define HWRM_CFA_TFLIB 0x125UL 270 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 271 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 272 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 273 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 274 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 275 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 276 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 277 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 278 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 279 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 280 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 281 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 282 #define HWRM_ENGINE_QG_QUERY 0x13dUL 283 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 284 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 285 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 286 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 287 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 288 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 289 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 290 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 291 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 292 #define HWRM_ENGINE_SG_QUERY 0x147UL 293 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 294 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 295 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 296 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 297 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 298 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 299 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 300 #define HWRM_ENGINE_STATS_QUERY 0x157UL 301 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 302 #define HWRM_ENGINE_RQ_FREE 0x15fUL 303 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 304 #define HWRM_ENGINE_CQ_FREE 0x161UL 305 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 306 #define HWRM_ENGINE_NQ_FREE 0x163UL 307 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 308 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 309 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 310 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 311 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 312 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 313 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 314 #define HWRM_FUNC_VF_BW_CFG 0x195UL 315 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 316 #define HWRM_SELFTEST_QLIST 0x200UL 317 #define HWRM_SELFTEST_EXEC 0x201UL 318 #define HWRM_SELFTEST_IRQ 0x202UL 319 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 320 #define HWRM_PCIE_QSTATS 0x204UL 321 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 322 #define HWRM_MFG_TIMERS_QUERY 0x206UL 323 #define HWRM_MFG_OTP_CFG 0x207UL 324 #define HWRM_MFG_OTP_QCFG 0x208UL 325 #define HWRM_MFG_HDMA_TEST 0x209UL 326 #define HWRM_DBG_READ_DIRECT 0xff10UL 327 #define HWRM_DBG_READ_INDIRECT 0xff11UL 328 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 329 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 330 #define HWRM_DBG_DUMP 0xff14UL 331 #define HWRM_DBG_ERASE_NVM 0xff15UL 332 #define HWRM_DBG_CFG 0xff16UL 333 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 334 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 335 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 336 #define HWRM_DBG_FW_CLI 0xff1aUL 337 #define HWRM_DBG_I2C_CMD 0xff1bUL 338 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 339 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 340 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 341 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 342 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 343 #define HWRM_NVM_FLUSH 0xfff0UL 344 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 345 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 346 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 347 #define HWRM_NVM_MODIFY 0xfff4UL 348 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 349 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 350 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 351 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 352 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 353 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 354 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 355 #define HWRM_NVM_RAW_DUMP 0xfffcUL 356 #define HWRM_NVM_READ 0xfffdUL 357 #define HWRM_NVM_WRITE 0xfffeUL 358 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 359 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 360 __le16 unused_0[3]; 361}; 362 363/* ret_codes (size:64b/8B) */ 364struct ret_codes { 365 __le16 error_code; 366 #define HWRM_ERR_CODE_SUCCESS 0x0UL 367 #define HWRM_ERR_CODE_FAIL 0x1UL 368 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 369 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 370 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 371 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 372 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 373 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 374 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 375 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 376 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 377 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 378 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 379 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 380 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 381 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 382 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 383 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 384 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 385 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 386 __le16 unused_0[3]; 387}; 388 389/* hwrm_err_output (size:128b/16B) */ 390struct hwrm_err_output { 391 __le16 error_code; 392 __le16 req_type; 393 __le16 seq_id; 394 __le16 resp_len; 395 __le32 opaque_0; 396 __le16 opaque_1; 397 u8 cmd_err; 398 u8 valid; 399}; 400#define HWRM_NA_SIGNATURE ((__le32)(-1)) 401#define HWRM_MAX_REQ_LEN 128 402#define HWRM_MAX_RESP_LEN 704 403#define HW_HASH_INDEX_SIZE 0x80 404#define HW_HASH_KEY_SIZE 40 405#define HWRM_RESP_VALID_KEY 1 406#define HWRM_TARGET_ID_BONO 0xFFF8 407#define HWRM_TARGET_ID_KONG 0xFFF9 408#define HWRM_TARGET_ID_APE 0xFFFA 409#define HWRM_TARGET_ID_TOOLS 0xFFFD 410#define HWRM_VERSION_MAJOR 1 411#define HWRM_VERSION_MINOR 10 412#define HWRM_VERSION_UPDATE 0 413#define HWRM_VERSION_RSVD 69 414#define HWRM_VERSION_STR "1.10.0.69" 415 416/* hwrm_ver_get_input (size:192b/24B) */ 417struct hwrm_ver_get_input { 418 __le16 req_type; 419 __le16 cmpl_ring; 420 __le16 seq_id; 421 __le16 target_id; 422 __le64 resp_addr; 423 u8 hwrm_intf_maj; 424 u8 hwrm_intf_min; 425 u8 hwrm_intf_upd; 426 u8 unused_0[5]; 427}; 428 429/* hwrm_ver_get_output (size:1408b/176B) */ 430struct hwrm_ver_get_output { 431 __le16 error_code; 432 __le16 req_type; 433 __le16 seq_id; 434 __le16 resp_len; 435 u8 hwrm_intf_maj_8b; 436 u8 hwrm_intf_min_8b; 437 u8 hwrm_intf_upd_8b; 438 u8 hwrm_intf_rsvd_8b; 439 u8 hwrm_fw_maj_8b; 440 u8 hwrm_fw_min_8b; 441 u8 hwrm_fw_bld_8b; 442 u8 hwrm_fw_rsvd_8b; 443 u8 mgmt_fw_maj_8b; 444 u8 mgmt_fw_min_8b; 445 u8 mgmt_fw_bld_8b; 446 u8 mgmt_fw_rsvd_8b; 447 u8 netctrl_fw_maj_8b; 448 u8 netctrl_fw_min_8b; 449 u8 netctrl_fw_bld_8b; 450 u8 netctrl_fw_rsvd_8b; 451 __le32 dev_caps_cfg; 452 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 453 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 454 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 455 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 456 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 457 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 458 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 459 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 460 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 461 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 462 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 463 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 464 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 465 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 466 u8 roce_fw_maj_8b; 467 u8 roce_fw_min_8b; 468 u8 roce_fw_bld_8b; 469 u8 roce_fw_rsvd_8b; 470 char hwrm_fw_name[16]; 471 char mgmt_fw_name[16]; 472 char netctrl_fw_name[16]; 473 char active_pkg_name[16]; 474 char roce_fw_name[16]; 475 __le16 chip_num; 476 u8 chip_rev; 477 u8 chip_metal; 478 u8 chip_bond_id; 479 u8 chip_platform_type; 480 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 481 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 482 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 483 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 484 __le16 max_req_win_len; 485 __le16 max_resp_len; 486 __le16 def_req_timeout; 487 u8 flags; 488 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 489 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 490 u8 unused_0[2]; 491 u8 always_1; 492 __le16 hwrm_intf_major; 493 __le16 hwrm_intf_minor; 494 __le16 hwrm_intf_build; 495 __le16 hwrm_intf_patch; 496 __le16 hwrm_fw_major; 497 __le16 hwrm_fw_minor; 498 __le16 hwrm_fw_build; 499 __le16 hwrm_fw_patch; 500 __le16 mgmt_fw_major; 501 __le16 mgmt_fw_minor; 502 __le16 mgmt_fw_build; 503 __le16 mgmt_fw_patch; 504 __le16 netctrl_fw_major; 505 __le16 netctrl_fw_minor; 506 __le16 netctrl_fw_build; 507 __le16 netctrl_fw_patch; 508 __le16 roce_fw_major; 509 __le16 roce_fw_minor; 510 __le16 roce_fw_build; 511 __le16 roce_fw_patch; 512 __le16 max_ext_req_len; 513 u8 unused_1[5]; 514 u8 valid; 515}; 516 517/* eject_cmpl (size:128b/16B) */ 518struct eject_cmpl { 519 __le16 type; 520 #define EJECT_CMPL_TYPE_MASK 0x3fUL 521 #define EJECT_CMPL_TYPE_SFT 0 522 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 523 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 524 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 525 #define EJECT_CMPL_FLAGS_SFT 6 526 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 527 __le16 len; 528 __le32 opaque; 529 __le16 v; 530 #define EJECT_CMPL_V 0x1UL 531 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 532 #define EJECT_CMPL_ERRORS_SFT 1 533 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 534 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 535 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 536 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 537 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 538 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 539 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 540 __le16 reserved16; 541 __le32 unused_2; 542}; 543 544/* hwrm_cmpl (size:128b/16B) */ 545struct hwrm_cmpl { 546 __le16 type; 547 #define CMPL_TYPE_MASK 0x3fUL 548 #define CMPL_TYPE_SFT 0 549 #define CMPL_TYPE_HWRM_DONE 0x20UL 550 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 551 __le16 sequence_id; 552 __le32 unused_1; 553 __le32 v; 554 #define CMPL_V 0x1UL 555 __le32 unused_3; 556}; 557 558/* hwrm_fwd_req_cmpl (size:128b/16B) */ 559struct hwrm_fwd_req_cmpl { 560 __le16 req_len_type; 561 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 562 #define FWD_REQ_CMPL_TYPE_SFT 0 563 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 564 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 565 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 566 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 567 __le16 source_id; 568 __le32 unused0; 569 __le32 req_buf_addr_v[2]; 570 #define FWD_REQ_CMPL_V 0x1UL 571 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 572 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 573}; 574 575/* hwrm_fwd_resp_cmpl (size:128b/16B) */ 576struct hwrm_fwd_resp_cmpl { 577 __le16 type; 578 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 579 #define FWD_RESP_CMPL_TYPE_SFT 0 580 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 581 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 582 __le16 source_id; 583 __le16 resp_len; 584 __le16 unused_1; 585 __le32 resp_buf_addr_v[2]; 586 #define FWD_RESP_CMPL_V 0x1UL 587 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 588 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 589}; 590 591/* hwrm_async_event_cmpl (size:128b/16B) */ 592struct hwrm_async_event_cmpl { 593 __le16 type; 594 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 595 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 596 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 597 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 598 __le16 event_id; 599 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 600 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 601 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 602 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 603 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 604 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 605 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 606 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 607 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 608 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 609 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 610 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 611 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 612 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 613 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 614 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 615 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 616 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 617 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 618 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 619 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 620 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 621 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 622 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 623 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 624 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 625 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 626 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 627 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 628 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 629 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 630 __le32 event_data2; 631 u8 opaque_v; 632 #define ASYNC_EVENT_CMPL_V 0x1UL 633 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 634 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 635 u8 timestamp_lo; 636 __le16 timestamp_hi; 637 __le32 event_data1; 638}; 639 640/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 641struct hwrm_async_event_cmpl_link_status_change { 642 __le16 type; 643 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 644 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 645 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 646 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 647 __le16 event_id; 648 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 649 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 650 __le32 event_data2; 651 u8 opaque_v; 652 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 653 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 654 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 655 u8 timestamp_lo; 656 __le16 timestamp_hi; 657 __le32 event_data1; 658 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 659 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 660 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 661 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 662 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 663 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 664 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 665 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 666 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 667 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 668}; 669 670/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 671struct hwrm_async_event_cmpl_port_conn_not_allowed { 672 __le16 type; 673 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 674 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 675 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 676 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 677 __le16 event_id; 678 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 679 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 680 __le32 event_data2; 681 u8 opaque_v; 682 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 683 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 684 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 685 u8 timestamp_lo; 686 __le16 timestamp_hi; 687 __le32 event_data1; 688 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 689 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 690 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 691 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 692 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 693 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 694 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 695 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 696 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 697}; 698 699/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 700struct hwrm_async_event_cmpl_link_speed_cfg_change { 701 __le16 type; 702 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 703 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 704 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 705 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 706 __le16 event_id; 707 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 708 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 709 __le32 event_data2; 710 u8 opaque_v; 711 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 712 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 713 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 714 u8 timestamp_lo; 715 __le16 timestamp_hi; 716 __le32 event_data1; 717 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 718 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 719 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 720 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 721}; 722 723/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 724struct hwrm_async_event_cmpl_reset_notify { 725 __le16 type; 726 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 727 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 728 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 729 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 730 __le16 event_id; 731 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 732 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 733 __le32 event_data2; 734 u8 opaque_v; 735 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 736 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 737 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 738 u8 timestamp_lo; 739 __le16 timestamp_hi; 740 __le32 event_data1; 741 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 742 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 743 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 744 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 745 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 746 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 747 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 748 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 749 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 750 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 751 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 752 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 753 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 754}; 755 756/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 757struct hwrm_async_event_cmpl_error_recovery { 758 __le16 type; 759 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 760 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 761 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 762 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 763 __le16 event_id; 764 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 765 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 766 __le32 event_data2; 767 u8 opaque_v; 768 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 769 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 770 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 771 u8 timestamp_lo; 772 __le16 timestamp_hi; 773 __le32 event_data1; 774 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 775 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 776 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 777 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 778}; 779 780/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 781struct hwrm_async_event_cmpl_vf_cfg_change { 782 __le16 type; 783 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 784 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 785 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 786 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 787 __le16 event_id; 788 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 789 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 790 __le32 event_data2; 791 u8 opaque_v; 792 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 793 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 794 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 795 u8 timestamp_lo; 796 __le16 timestamp_hi; 797 __le32 event_data1; 798 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 799 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 800 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 801 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 802 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 803}; 804 805/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 806struct hwrm_async_event_cmpl_hw_flow_aged { 807 __le16 type; 808 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 809 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 810 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 811 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 812 __le16 event_id; 813 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 814 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 815 __le32 event_data2; 816 u8 opaque_v; 817 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 818 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 819 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 820 u8 timestamp_lo; 821 __le16 timestamp_hi; 822 __le32 event_data1; 823 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 824 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 825 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 826 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 827 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 828 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 829}; 830 831/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 832struct hwrm_async_event_cmpl_eem_cache_flush_req { 833 __le16 type; 834 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 835 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 836 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 837 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 838 __le16 event_id; 839 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 840 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 841 __le32 event_data2; 842 u8 opaque_v; 843 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 844 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 845 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 846 u8 timestamp_lo; 847 __le16 timestamp_hi; 848 __le32 event_data1; 849}; 850 851/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 852struct hwrm_async_event_cmpl_eem_cache_flush_done { 853 __le16 type; 854 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 855 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 856 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 857 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 858 __le16 event_id; 859 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 860 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 861 __le32 event_data2; 862 u8 opaque_v; 863 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 864 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 865 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 866 u8 timestamp_lo; 867 __le16 timestamp_hi; 868 __le32 event_data1; 869 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 870 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 871}; 872 873/* hwrm_func_reset_input (size:192b/24B) */ 874struct hwrm_func_reset_input { 875 __le16 req_type; 876 __le16 cmpl_ring; 877 __le16 seq_id; 878 __le16 target_id; 879 __le64 resp_addr; 880 __le32 enables; 881 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 882 __le16 vf_id; 883 u8 func_reset_level; 884 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 885 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 886 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 887 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 888 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 889 u8 unused_0; 890}; 891 892/* hwrm_func_reset_output (size:128b/16B) */ 893struct hwrm_func_reset_output { 894 __le16 error_code; 895 __le16 req_type; 896 __le16 seq_id; 897 __le16 resp_len; 898 u8 unused_0[7]; 899 u8 valid; 900}; 901 902/* hwrm_func_getfid_input (size:192b/24B) */ 903struct hwrm_func_getfid_input { 904 __le16 req_type; 905 __le16 cmpl_ring; 906 __le16 seq_id; 907 __le16 target_id; 908 __le64 resp_addr; 909 __le32 enables; 910 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 911 __le16 pci_id; 912 u8 unused_0[2]; 913}; 914 915/* hwrm_func_getfid_output (size:128b/16B) */ 916struct hwrm_func_getfid_output { 917 __le16 error_code; 918 __le16 req_type; 919 __le16 seq_id; 920 __le16 resp_len; 921 __le16 fid; 922 u8 unused_0[5]; 923 u8 valid; 924}; 925 926/* hwrm_func_vf_alloc_input (size:192b/24B) */ 927struct hwrm_func_vf_alloc_input { 928 __le16 req_type; 929 __le16 cmpl_ring; 930 __le16 seq_id; 931 __le16 target_id; 932 __le64 resp_addr; 933 __le32 enables; 934 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 935 __le16 first_vf_id; 936 __le16 num_vfs; 937}; 938 939/* hwrm_func_vf_alloc_output (size:128b/16B) */ 940struct hwrm_func_vf_alloc_output { 941 __le16 error_code; 942 __le16 req_type; 943 __le16 seq_id; 944 __le16 resp_len; 945 __le16 first_vf_id; 946 u8 unused_0[5]; 947 u8 valid; 948}; 949 950/* hwrm_func_vf_free_input (size:192b/24B) */ 951struct hwrm_func_vf_free_input { 952 __le16 req_type; 953 __le16 cmpl_ring; 954 __le16 seq_id; 955 __le16 target_id; 956 __le64 resp_addr; 957 __le32 enables; 958 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 959 __le16 first_vf_id; 960 __le16 num_vfs; 961}; 962 963/* hwrm_func_vf_free_output (size:128b/16B) */ 964struct hwrm_func_vf_free_output { 965 __le16 error_code; 966 __le16 req_type; 967 __le16 seq_id; 968 __le16 resp_len; 969 u8 unused_0[7]; 970 u8 valid; 971}; 972 973/* hwrm_func_vf_cfg_input (size:448b/56B) */ 974struct hwrm_func_vf_cfg_input { 975 __le16 req_type; 976 __le16 cmpl_ring; 977 __le16 seq_id; 978 __le16 target_id; 979 __le64 resp_addr; 980 __le32 enables; 981 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 982 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 983 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 984 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 985 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 986 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 987 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 988 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 989 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 990 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 991 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 992 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 993 __le16 mtu; 994 __le16 guest_vlan; 995 __le16 async_event_cr; 996 u8 dflt_mac_addr[6]; 997 __le32 flags; 998 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 999 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1000 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1001 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1002 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1003 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1004 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1005 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1006 __le16 num_rsscos_ctxs; 1007 __le16 num_cmpl_rings; 1008 __le16 num_tx_rings; 1009 __le16 num_rx_rings; 1010 __le16 num_l2_ctxs; 1011 __le16 num_vnics; 1012 __le16 num_stat_ctxs; 1013 __le16 num_hw_ring_grps; 1014 u8 unused_0[4]; 1015}; 1016 1017/* hwrm_func_vf_cfg_output (size:128b/16B) */ 1018struct hwrm_func_vf_cfg_output { 1019 __le16 error_code; 1020 __le16 req_type; 1021 __le16 seq_id; 1022 __le16 resp_len; 1023 u8 unused_0[7]; 1024 u8 valid; 1025}; 1026 1027/* hwrm_func_qcaps_input (size:192b/24B) */ 1028struct hwrm_func_qcaps_input { 1029 __le16 req_type; 1030 __le16 cmpl_ring; 1031 __le16 seq_id; 1032 __le16 target_id; 1033 __le64 resp_addr; 1034 __le16 fid; 1035 u8 unused_0[6]; 1036}; 1037 1038/* hwrm_func_qcaps_output (size:640b/80B) */ 1039struct hwrm_func_qcaps_output { 1040 __le16 error_code; 1041 __le16 req_type; 1042 __le16 seq_id; 1043 __le16 resp_len; 1044 __le16 fid; 1045 __le16 port_id; 1046 __le32 flags; 1047 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1048 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1049 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1050 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1051 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1052 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1053 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1054 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1055 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1056 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1057 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1058 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1059 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1060 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1061 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1062 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1063 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1064 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1065 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1066 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1067 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1068 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1069 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1070 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1071 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1072 u8 mac_address[6]; 1073 __le16 max_rsscos_ctx; 1074 __le16 max_cmpl_rings; 1075 __le16 max_tx_rings; 1076 __le16 max_rx_rings; 1077 __le16 max_l2_ctxs; 1078 __le16 max_vnics; 1079 __le16 first_vf_id; 1080 __le16 max_vfs; 1081 __le16 max_stat_ctx; 1082 __le32 max_encap_records; 1083 __le32 max_decap_records; 1084 __le32 max_tx_em_flows; 1085 __le32 max_tx_wm_flows; 1086 __le32 max_rx_em_flows; 1087 __le32 max_rx_wm_flows; 1088 __le32 max_mcast_filters; 1089 __le32 max_flow_id; 1090 __le32 max_hw_ring_grps; 1091 __le16 max_sp_tx_rings; 1092 u8 unused_0; 1093 u8 valid; 1094}; 1095 1096/* hwrm_func_qcfg_input (size:192b/24B) */ 1097struct hwrm_func_qcfg_input { 1098 __le16 req_type; 1099 __le16 cmpl_ring; 1100 __le16 seq_id; 1101 __le16 target_id; 1102 __le64 resp_addr; 1103 __le16 fid; 1104 u8 unused_0[6]; 1105}; 1106 1107/* hwrm_func_qcfg_output (size:704b/88B) */ 1108struct hwrm_func_qcfg_output { 1109 __le16 error_code; 1110 __le16 req_type; 1111 __le16 seq_id; 1112 __le16 resp_len; 1113 __le16 fid; 1114 __le16 port_id; 1115 __le16 vlan; 1116 __le16 flags; 1117 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1118 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1119 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1120 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1121 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1122 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1123 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1124 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1125 u8 mac_address[6]; 1126 __le16 pci_id; 1127 __le16 alloc_rsscos_ctx; 1128 __le16 alloc_cmpl_rings; 1129 __le16 alloc_tx_rings; 1130 __le16 alloc_rx_rings; 1131 __le16 alloc_l2_ctx; 1132 __le16 alloc_vnics; 1133 __le16 mtu; 1134 __le16 mru; 1135 __le16 stat_ctx_id; 1136 u8 port_partition_type; 1137 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1138 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1139 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1140 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1141 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1142 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1143 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1144 u8 port_pf_cnt; 1145 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1146 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1147 __le16 dflt_vnic_id; 1148 __le16 max_mtu_configured; 1149 __le32 min_bw; 1150 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1151 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1152 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1153 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1154 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1155 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1156 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1157 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1158 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1159 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1160 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1161 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1162 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1163 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1164 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1165 __le32 max_bw; 1166 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1167 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1168 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1169 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1170 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1171 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1172 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1173 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1174 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1175 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1176 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1177 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1178 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1179 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1180 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1181 u8 evb_mode; 1182 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1183 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1184 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1185 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1186 u8 options; 1187 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1188 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1189 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1190 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1191 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1192 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1193 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1194 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1195 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1196 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1197 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1198 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1199 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1200 __le16 alloc_vfs; 1201 __le32 alloc_mcast_filters; 1202 __le32 alloc_hw_ring_grps; 1203 __le16 alloc_sp_tx_rings; 1204 __le16 alloc_stat_ctx; 1205 __le16 alloc_msix; 1206 __le16 registered_vfs; 1207 u8 unused_1[3]; 1208 u8 always_1; 1209 __le32 reset_addr_poll; 1210 u8 unused_2[3]; 1211 u8 valid; 1212}; 1213 1214/* hwrm_func_cfg_input (size:704b/88B) */ 1215struct hwrm_func_cfg_input { 1216 __le16 req_type; 1217 __le16 cmpl_ring; 1218 __le16 seq_id; 1219 __le16 target_id; 1220 __le64 resp_addr; 1221 __le16 fid; 1222 __le16 num_msix; 1223 __le32 flags; 1224 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1225 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1226 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1227 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1228 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1229 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1230 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1231 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1232 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1233 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1234 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1235 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1236 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1237 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1238 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1239 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1240 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1241 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1242 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1243 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1244 __le32 enables; 1245 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1246 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1247 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1248 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1249 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1250 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1251 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1252 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1253 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1254 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1255 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1256 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1257 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1258 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1259 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1260 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1261 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1262 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1263 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1264 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1265 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1266 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1267 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1268 __le16 mtu; 1269 __le16 mru; 1270 __le16 num_rsscos_ctxs; 1271 __le16 num_cmpl_rings; 1272 __le16 num_tx_rings; 1273 __le16 num_rx_rings; 1274 __le16 num_l2_ctxs; 1275 __le16 num_vnics; 1276 __le16 num_stat_ctxs; 1277 __le16 num_hw_ring_grps; 1278 u8 dflt_mac_addr[6]; 1279 __le16 dflt_vlan; 1280 __be32 dflt_ip_addr[4]; 1281 __le32 min_bw; 1282 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1283 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1284 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1285 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1286 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1287 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1288 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1289 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1290 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1291 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1292 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1293 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1294 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1295 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1296 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1297 __le32 max_bw; 1298 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1299 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1300 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1301 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1302 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1303 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1304 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1305 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1306 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1307 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1308 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1309 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1310 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1311 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1312 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1313 __le16 async_event_cr; 1314 u8 vlan_antispoof_mode; 1315 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1316 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1317 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1318 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1319 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1320 u8 allowed_vlan_pris; 1321 u8 evb_mode; 1322 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1323 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1324 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1325 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1326 u8 options; 1327 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1328 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1329 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1330 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1331 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1332 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1333 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1334 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1335 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1336 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1337 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1338 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1339 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1340 __le16 num_mcast_filters; 1341}; 1342 1343/* hwrm_func_cfg_output (size:128b/16B) */ 1344struct hwrm_func_cfg_output { 1345 __le16 error_code; 1346 __le16 req_type; 1347 __le16 seq_id; 1348 __le16 resp_len; 1349 u8 unused_0[7]; 1350 u8 valid; 1351}; 1352 1353/* hwrm_func_qstats_input (size:192b/24B) */ 1354struct hwrm_func_qstats_input { 1355 __le16 req_type; 1356 __le16 cmpl_ring; 1357 __le16 seq_id; 1358 __le16 target_id; 1359 __le64 resp_addr; 1360 __le16 fid; 1361 u8 unused_0[6]; 1362}; 1363 1364/* hwrm_func_qstats_output (size:1408b/176B) */ 1365struct hwrm_func_qstats_output { 1366 __le16 error_code; 1367 __le16 req_type; 1368 __le16 seq_id; 1369 __le16 resp_len; 1370 __le64 tx_ucast_pkts; 1371 __le64 tx_mcast_pkts; 1372 __le64 tx_bcast_pkts; 1373 __le64 tx_discard_pkts; 1374 __le64 tx_drop_pkts; 1375 __le64 tx_ucast_bytes; 1376 __le64 tx_mcast_bytes; 1377 __le64 tx_bcast_bytes; 1378 __le64 rx_ucast_pkts; 1379 __le64 rx_mcast_pkts; 1380 __le64 rx_bcast_pkts; 1381 __le64 rx_discard_pkts; 1382 __le64 rx_drop_pkts; 1383 __le64 rx_ucast_bytes; 1384 __le64 rx_mcast_bytes; 1385 __le64 rx_bcast_bytes; 1386 __le64 rx_agg_pkts; 1387 __le64 rx_agg_bytes; 1388 __le64 rx_agg_events; 1389 __le64 rx_agg_aborts; 1390 u8 unused_0[7]; 1391 u8 valid; 1392}; 1393 1394/* hwrm_func_clr_stats_input (size:192b/24B) */ 1395struct hwrm_func_clr_stats_input { 1396 __le16 req_type; 1397 __le16 cmpl_ring; 1398 __le16 seq_id; 1399 __le16 target_id; 1400 __le64 resp_addr; 1401 __le16 fid; 1402 u8 unused_0[6]; 1403}; 1404 1405/* hwrm_func_clr_stats_output (size:128b/16B) */ 1406struct hwrm_func_clr_stats_output { 1407 __le16 error_code; 1408 __le16 req_type; 1409 __le16 seq_id; 1410 __le16 resp_len; 1411 u8 unused_0[7]; 1412 u8 valid; 1413}; 1414 1415/* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1416struct hwrm_func_vf_resc_free_input { 1417 __le16 req_type; 1418 __le16 cmpl_ring; 1419 __le16 seq_id; 1420 __le16 target_id; 1421 __le64 resp_addr; 1422 __le16 vf_id; 1423 u8 unused_0[6]; 1424}; 1425 1426/* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1427struct hwrm_func_vf_resc_free_output { 1428 __le16 error_code; 1429 __le16 req_type; 1430 __le16 seq_id; 1431 __le16 resp_len; 1432 u8 unused_0[7]; 1433 u8 valid; 1434}; 1435 1436/* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1437struct hwrm_func_drv_rgtr_input { 1438 __le16 req_type; 1439 __le16 cmpl_ring; 1440 __le16 seq_id; 1441 __le16 target_id; 1442 __le64 resp_addr; 1443 __le32 flags; 1444 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1445 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1446 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1447 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1448 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1449 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1450 __le32 enables; 1451 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1452 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1453 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1454 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1455 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1456 __le16 os_type; 1457 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1458 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1459 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1460 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1461 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1462 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1463 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1464 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1465 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1466 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1467 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1468 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1469 u8 ver_maj_8b; 1470 u8 ver_min_8b; 1471 u8 ver_upd_8b; 1472 u8 unused_0[3]; 1473 __le32 timestamp; 1474 u8 unused_1[4]; 1475 __le32 vf_req_fwd[8]; 1476 __le32 async_event_fwd[8]; 1477 __le16 ver_maj; 1478 __le16 ver_min; 1479 __le16 ver_upd; 1480 __le16 ver_patch; 1481}; 1482 1483/* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1484struct hwrm_func_drv_rgtr_output { 1485 __le16 error_code; 1486 __le16 req_type; 1487 __le16 seq_id; 1488 __le16 resp_len; 1489 __le32 flags; 1490 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1491 u8 unused_0[3]; 1492 u8 valid; 1493}; 1494 1495/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1496struct hwrm_func_drv_unrgtr_input { 1497 __le16 req_type; 1498 __le16 cmpl_ring; 1499 __le16 seq_id; 1500 __le16 target_id; 1501 __le64 resp_addr; 1502 __le32 flags; 1503 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1504 u8 unused_0[4]; 1505}; 1506 1507/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1508struct hwrm_func_drv_unrgtr_output { 1509 __le16 error_code; 1510 __le16 req_type; 1511 __le16 seq_id; 1512 __le16 resp_len; 1513 u8 unused_0[7]; 1514 u8 valid; 1515}; 1516 1517/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1518struct hwrm_func_buf_rgtr_input { 1519 __le16 req_type; 1520 __le16 cmpl_ring; 1521 __le16 seq_id; 1522 __le16 target_id; 1523 __le64 resp_addr; 1524 __le32 enables; 1525 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1526 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1527 __le16 vf_id; 1528 __le16 req_buf_num_pages; 1529 __le16 req_buf_page_size; 1530 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1531 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1532 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1533 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1534 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1535 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1536 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1537 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1538 __le16 req_buf_len; 1539 __le16 resp_buf_len; 1540 u8 unused_0[2]; 1541 __le64 req_buf_page_addr0; 1542 __le64 req_buf_page_addr1; 1543 __le64 req_buf_page_addr2; 1544 __le64 req_buf_page_addr3; 1545 __le64 req_buf_page_addr4; 1546 __le64 req_buf_page_addr5; 1547 __le64 req_buf_page_addr6; 1548 __le64 req_buf_page_addr7; 1549 __le64 req_buf_page_addr8; 1550 __le64 req_buf_page_addr9; 1551 __le64 error_buf_addr; 1552 __le64 resp_buf_addr; 1553}; 1554 1555/* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1556struct hwrm_func_buf_rgtr_output { 1557 __le16 error_code; 1558 __le16 req_type; 1559 __le16 seq_id; 1560 __le16 resp_len; 1561 u8 unused_0[7]; 1562 u8 valid; 1563}; 1564 1565/* hwrm_func_drv_qver_input (size:192b/24B) */ 1566struct hwrm_func_drv_qver_input { 1567 __le16 req_type; 1568 __le16 cmpl_ring; 1569 __le16 seq_id; 1570 __le16 target_id; 1571 __le64 resp_addr; 1572 __le32 reserved; 1573 __le16 fid; 1574 u8 unused_0[2]; 1575}; 1576 1577/* hwrm_func_drv_qver_output (size:256b/32B) */ 1578struct hwrm_func_drv_qver_output { 1579 __le16 error_code; 1580 __le16 req_type; 1581 __le16 seq_id; 1582 __le16 resp_len; 1583 __le16 os_type; 1584 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1585 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1586 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1587 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1588 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1589 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1590 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1591 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1592 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1593 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1594 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1595 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1596 u8 ver_maj_8b; 1597 u8 ver_min_8b; 1598 u8 ver_upd_8b; 1599 u8 unused_0[3]; 1600 __le16 ver_maj; 1601 __le16 ver_min; 1602 __le16 ver_upd; 1603 __le16 ver_patch; 1604 u8 unused_1[7]; 1605 u8 valid; 1606}; 1607 1608/* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1609struct hwrm_func_resource_qcaps_input { 1610 __le16 req_type; 1611 __le16 cmpl_ring; 1612 __le16 seq_id; 1613 __le16 target_id; 1614 __le64 resp_addr; 1615 __le16 fid; 1616 u8 unused_0[6]; 1617}; 1618 1619/* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1620struct hwrm_func_resource_qcaps_output { 1621 __le16 error_code; 1622 __le16 req_type; 1623 __le16 seq_id; 1624 __le16 resp_len; 1625 __le16 max_vfs; 1626 __le16 max_msix; 1627 __le16 vf_reservation_strategy; 1628 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1629 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1630 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1631 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1632 __le16 min_rsscos_ctx; 1633 __le16 max_rsscos_ctx; 1634 __le16 min_cmpl_rings; 1635 __le16 max_cmpl_rings; 1636 __le16 min_tx_rings; 1637 __le16 max_tx_rings; 1638 __le16 min_rx_rings; 1639 __le16 max_rx_rings; 1640 __le16 min_l2_ctxs; 1641 __le16 max_l2_ctxs; 1642 __le16 min_vnics; 1643 __le16 max_vnics; 1644 __le16 min_stat_ctx; 1645 __le16 max_stat_ctx; 1646 __le16 min_hw_ring_grps; 1647 __le16 max_hw_ring_grps; 1648 __le16 max_tx_scheduler_inputs; 1649 __le16 flags; 1650 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1651 u8 unused_0[5]; 1652 u8 valid; 1653}; 1654 1655/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1656struct hwrm_func_vf_resource_cfg_input { 1657 __le16 req_type; 1658 __le16 cmpl_ring; 1659 __le16 seq_id; 1660 __le16 target_id; 1661 __le64 resp_addr; 1662 __le16 vf_id; 1663 __le16 max_msix; 1664 __le16 min_rsscos_ctx; 1665 __le16 max_rsscos_ctx; 1666 __le16 min_cmpl_rings; 1667 __le16 max_cmpl_rings; 1668 __le16 min_tx_rings; 1669 __le16 max_tx_rings; 1670 __le16 min_rx_rings; 1671 __le16 max_rx_rings; 1672 __le16 min_l2_ctxs; 1673 __le16 max_l2_ctxs; 1674 __le16 min_vnics; 1675 __le16 max_vnics; 1676 __le16 min_stat_ctx; 1677 __le16 max_stat_ctx; 1678 __le16 min_hw_ring_grps; 1679 __le16 max_hw_ring_grps; 1680 __le16 flags; 1681 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1682 u8 unused_0[2]; 1683}; 1684 1685/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1686struct hwrm_func_vf_resource_cfg_output { 1687 __le16 error_code; 1688 __le16 req_type; 1689 __le16 seq_id; 1690 __le16 resp_len; 1691 __le16 reserved_rsscos_ctx; 1692 __le16 reserved_cmpl_rings; 1693 __le16 reserved_tx_rings; 1694 __le16 reserved_rx_rings; 1695 __le16 reserved_l2_ctxs; 1696 __le16 reserved_vnics; 1697 __le16 reserved_stat_ctx; 1698 __le16 reserved_hw_ring_grps; 1699 u8 unused_0[7]; 1700 u8 valid; 1701}; 1702 1703/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1704struct hwrm_func_backing_store_qcaps_input { 1705 __le16 req_type; 1706 __le16 cmpl_ring; 1707 __le16 seq_id; 1708 __le16 target_id; 1709 __le64 resp_addr; 1710}; 1711 1712/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ 1713struct hwrm_func_backing_store_qcaps_output { 1714 __le16 error_code; 1715 __le16 req_type; 1716 __le16 seq_id; 1717 __le16 resp_len; 1718 __le32 qp_max_entries; 1719 __le16 qp_min_qp1_entries; 1720 __le16 qp_max_l2_entries; 1721 __le16 qp_entry_size; 1722 __le16 srq_max_l2_entries; 1723 __le32 srq_max_entries; 1724 __le16 srq_entry_size; 1725 __le16 cq_max_l2_entries; 1726 __le32 cq_max_entries; 1727 __le16 cq_entry_size; 1728 __le16 vnic_max_vnic_entries; 1729 __le16 vnic_max_ring_table_entries; 1730 __le16 vnic_entry_size; 1731 __le32 stat_max_entries; 1732 __le16 stat_entry_size; 1733 __le16 tqm_entry_size; 1734 __le32 tqm_min_entries_per_ring; 1735 __le32 tqm_max_entries_per_ring; 1736 __le32 mrav_max_entries; 1737 __le16 mrav_entry_size; 1738 __le16 tim_entry_size; 1739 __le32 tim_max_entries; 1740 __le16 mrav_num_entries_units; 1741 u8 tqm_entries_multiple; 1742 u8 valid; 1743}; 1744 1745/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1746struct hwrm_func_backing_store_cfg_input { 1747 __le16 req_type; 1748 __le16 cmpl_ring; 1749 __le16 seq_id; 1750 __le16 target_id; 1751 __le64 resp_addr; 1752 __le32 flags; 1753 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1754 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 1755 __le32 enables; 1756 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1757 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1758 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1759 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1760 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1761 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1762 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1763 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1764 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1765 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1766 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1767 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1768 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1769 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1770 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1771 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1772 u8 qpc_pg_size_qpc_lvl; 1773 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1774 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1775 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1776 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1777 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1778 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1779 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1780 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1781 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1782 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1783 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1784 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1785 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1786 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1787 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1788 u8 srq_pg_size_srq_lvl; 1789 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1790 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1791 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1792 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1793 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1794 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1795 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 1796 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 1797 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1798 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1799 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1800 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1801 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1802 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1803 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 1804 u8 cq_pg_size_cq_lvl; 1805 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 1806 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 1807 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 1808 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 1809 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 1810 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 1811 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 1812 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 1813 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1814 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1815 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1816 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1817 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1818 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1819 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 1820 u8 vnic_pg_size_vnic_lvl; 1821 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 1822 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 1823 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 1824 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 1825 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 1826 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 1827 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 1828 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 1829 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 1830 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 1831 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 1832 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 1833 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 1834 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 1835 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 1836 u8 stat_pg_size_stat_lvl; 1837 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 1838 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 1839 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 1840 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 1841 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 1842 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 1843 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 1844 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 1845 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 1846 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 1847 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 1848 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 1849 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 1850 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 1851 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 1852 u8 tqm_sp_pg_size_tqm_sp_lvl; 1853 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 1854 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 1855 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 1856 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 1857 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 1858 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 1859 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 1860 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 1861 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 1862 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 1863 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 1864 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 1865 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 1866 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 1867 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 1868 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 1869 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 1870 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 1871 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 1872 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 1873 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 1874 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 1875 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 1876 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 1877 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 1878 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 1879 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 1880 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 1881 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 1882 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 1883 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 1884 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 1885 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 1886 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 1887 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 1888 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 1889 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 1890 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 1891 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 1892 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 1893 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 1894 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 1895 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 1896 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 1897 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 1898 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 1899 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 1900 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 1901 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 1902 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 1903 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 1904 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 1905 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 1906 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 1907 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 1908 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 1909 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 1910 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 1911 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 1912 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 1913 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 1914 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 1915 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 1916 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 1917 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 1918 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 1919 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 1920 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 1921 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 1922 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 1923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 1924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 1925 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 1926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 1927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 1928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 1929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 1930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 1931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 1932 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 1933 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 1934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 1935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 1936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 1937 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 1938 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 1939 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 1940 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 1941 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 1942 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 1943 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 1944 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 1945 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 1946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 1947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 1948 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 1949 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 1950 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 1951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 1952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 1953 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 1954 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 1955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 1956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 1957 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 1958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 1959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 1960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 1961 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 1962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 1963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 1964 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 1965 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 1966 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 1967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 1968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 1969 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 1970 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 1971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 1972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 1973 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 1974 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 1975 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 1976 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 1977 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 1978 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 1979 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 1980 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 1981 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 1982 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 1983 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 1984 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 1985 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 1986 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 1987 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 1988 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 1989 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 1990 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 1991 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 1992 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 1993 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 1994 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 1995 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 1996 u8 mrav_pg_size_mrav_lvl; 1997 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 1998 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 1999 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2000 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2001 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2002 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2003 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2004 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2005 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2006 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2007 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2008 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2009 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2010 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2011 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2012 u8 tim_pg_size_tim_lvl; 2013 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2014 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2015 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2016 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2017 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2018 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2019 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2020 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2021 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2022 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2023 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2024 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2025 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2026 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2027 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2028 __le64 qpc_page_dir; 2029 __le64 srq_page_dir; 2030 __le64 cq_page_dir; 2031 __le64 vnic_page_dir; 2032 __le64 stat_page_dir; 2033 __le64 tqm_sp_page_dir; 2034 __le64 tqm_ring0_page_dir; 2035 __le64 tqm_ring1_page_dir; 2036 __le64 tqm_ring2_page_dir; 2037 __le64 tqm_ring3_page_dir; 2038 __le64 tqm_ring4_page_dir; 2039 __le64 tqm_ring5_page_dir; 2040 __le64 tqm_ring6_page_dir; 2041 __le64 tqm_ring7_page_dir; 2042 __le64 mrav_page_dir; 2043 __le64 tim_page_dir; 2044 __le32 qp_num_entries; 2045 __le32 srq_num_entries; 2046 __le32 cq_num_entries; 2047 __le32 stat_num_entries; 2048 __le32 tqm_sp_num_entries; 2049 __le32 tqm_ring0_num_entries; 2050 __le32 tqm_ring1_num_entries; 2051 __le32 tqm_ring2_num_entries; 2052 __le32 tqm_ring3_num_entries; 2053 __le32 tqm_ring4_num_entries; 2054 __le32 tqm_ring5_num_entries; 2055 __le32 tqm_ring6_num_entries; 2056 __le32 tqm_ring7_num_entries; 2057 __le32 mrav_num_entries; 2058 __le32 tim_num_entries; 2059 __le16 qp_num_qp1_entries; 2060 __le16 qp_num_l2_entries; 2061 __le16 qp_entry_size; 2062 __le16 srq_num_l2_entries; 2063 __le16 srq_entry_size; 2064 __le16 cq_num_l2_entries; 2065 __le16 cq_entry_size; 2066 __le16 vnic_num_vnic_entries; 2067 __le16 vnic_num_ring_table_entries; 2068 __le16 vnic_entry_size; 2069 __le16 stat_entry_size; 2070 __le16 tqm_entry_size; 2071 __le16 mrav_entry_size; 2072 __le16 tim_entry_size; 2073}; 2074 2075/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2076struct hwrm_func_backing_store_cfg_output { 2077 __le16 error_code; 2078 __le16 req_type; 2079 __le16 seq_id; 2080 __le16 resp_len; 2081 u8 unused_0[7]; 2082 u8 valid; 2083}; 2084 2085/* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2086struct hwrm_error_recovery_qcfg_input { 2087 __le16 req_type; 2088 __le16 cmpl_ring; 2089 __le16 seq_id; 2090 __le16 target_id; 2091 __le64 resp_addr; 2092 u8 unused_0[8]; 2093}; 2094 2095/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2096struct hwrm_error_recovery_qcfg_output { 2097 __le16 error_code; 2098 __le16 req_type; 2099 __le16 seq_id; 2100 __le16 resp_len; 2101 __le32 flags; 2102 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2103 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2104 __le32 driver_polling_freq; 2105 __le32 master_func_wait_period; 2106 __le32 normal_func_wait_period; 2107 __le32 master_func_wait_period_after_reset; 2108 __le32 max_bailout_time_after_reset; 2109 __le32 fw_health_status_reg; 2110 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2111 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2112 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2113 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2114 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2115 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2116 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2117 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2118 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2119 __le32 fw_heartbeat_reg; 2120 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2121 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2122 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2123 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2124 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2125 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2126 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2127 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2128 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2129 __le32 fw_reset_cnt_reg; 2130 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2131 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2132 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2133 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2134 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2135 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2136 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2137 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2138 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2139 __le32 reset_inprogress_reg; 2140 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2141 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2142 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2143 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2144 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2145 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2146 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2147 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2148 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2149 __le32 reset_inprogress_reg_mask; 2150 u8 unused_0[3]; 2151 u8 reg_array_cnt; 2152 __le32 reset_reg[16]; 2153 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2154 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2155 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2156 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2157 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2158 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2159 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2160 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2161 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2162 __le32 reset_reg_val[16]; 2163 u8 delay_after_reset[16]; 2164 u8 unused_1[7]; 2165 u8 valid; 2166}; 2167 2168/* hwrm_func_drv_if_change_input (size:192b/24B) */ 2169struct hwrm_func_drv_if_change_input { 2170 __le16 req_type; 2171 __le16 cmpl_ring; 2172 __le16 seq_id; 2173 __le16 target_id; 2174 __le64 resp_addr; 2175 __le32 flags; 2176 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2177 __le32 unused; 2178}; 2179 2180/* hwrm_func_drv_if_change_output (size:128b/16B) */ 2181struct hwrm_func_drv_if_change_output { 2182 __le16 error_code; 2183 __le16 req_type; 2184 __le16 seq_id; 2185 __le16 resp_len; 2186 __le32 flags; 2187 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2188 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2189 u8 unused_0[3]; 2190 u8 valid; 2191}; 2192 2193/* hwrm_port_phy_cfg_input (size:448b/56B) */ 2194struct hwrm_port_phy_cfg_input { 2195 __le16 req_type; 2196 __le16 cmpl_ring; 2197 __le16 seq_id; 2198 __le16 target_id; 2199 __le64 resp_addr; 2200 __le32 flags; 2201 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2202 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2203 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2204 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2205 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2206 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2207 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2208 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2209 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2210 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2211 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2212 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2213 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2214 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2215 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2216 __le32 enables; 2217 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2218 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2219 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2220 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2221 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2222 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2223 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2224 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2225 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2226 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2227 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2228 __le16 port_id; 2229 __le16 force_link_speed; 2230 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2231 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2232 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2233 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2234 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2235 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2236 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2237 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2238 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2239 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2240 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL 2241 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2242 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2243 u8 auto_mode; 2244 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2245 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2246 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2247 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2248 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2249 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2250 u8 auto_duplex; 2251 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2252 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2253 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2254 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2255 u8 auto_pause; 2256 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2257 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2258 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2259 u8 unused_0; 2260 __le16 auto_link_speed; 2261 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2262 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2263 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2264 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2265 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2266 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2267 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2268 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2269 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2270 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2271 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL 2272 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2273 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2274 __le16 auto_link_speed_mask; 2275 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2276 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2277 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2278 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2279 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2280 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2281 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2282 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2283 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2284 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2285 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2286 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2287 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2288 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2289 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2290 u8 wirespeed; 2291 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2292 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2293 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2294 u8 lpbk; 2295 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2296 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2297 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2298 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2299 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2300 u8 force_pause; 2301 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2302 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2303 u8 unused_1; 2304 __le32 preemphasis; 2305 __le16 eee_link_speed_mask; 2306 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2307 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2308 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2309 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2310 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2311 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2312 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2313 u8 unused_2[2]; 2314 __le32 tx_lpi_timer; 2315 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2316 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2317 __le32 unused_3; 2318}; 2319 2320/* hwrm_port_phy_cfg_output (size:128b/16B) */ 2321struct hwrm_port_phy_cfg_output { 2322 __le16 error_code; 2323 __le16 req_type; 2324 __le16 seq_id; 2325 __le16 resp_len; 2326 u8 unused_0[7]; 2327 u8 valid; 2328}; 2329 2330/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2331struct hwrm_port_phy_cfg_cmd_err { 2332 u8 code; 2333 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2334 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2335 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2336 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2337 u8 unused_0[7]; 2338}; 2339 2340/* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2341struct hwrm_port_phy_qcfg_input { 2342 __le16 req_type; 2343 __le16 cmpl_ring; 2344 __le16 seq_id; 2345 __le16 target_id; 2346 __le64 resp_addr; 2347 __le16 port_id; 2348 u8 unused_0[6]; 2349}; 2350 2351/* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2352struct hwrm_port_phy_qcfg_output { 2353 __le16 error_code; 2354 __le16 req_type; 2355 __le16 seq_id; 2356 __le16 resp_len; 2357 u8 link; 2358 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2359 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2360 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2361 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2362 u8 unused_0; 2363 __le16 link_speed; 2364 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2365 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2366 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2367 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2368 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2369 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2370 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2371 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2372 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2373 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2374 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2375 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2376 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2377 u8 duplex_cfg; 2378 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2379 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2380 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2381 u8 pause; 2382 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2383 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2384 __le16 support_speeds; 2385 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2386 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2387 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2388 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2389 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2390 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2391 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2392 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2393 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2394 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2395 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2396 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2397 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2398 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2399 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL 2400 __le16 force_link_speed; 2401 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2402 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2403 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2404 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2405 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2406 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2407 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2408 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2409 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2410 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2411 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL 2412 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2413 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2414 u8 auto_mode; 2415 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2416 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2417 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2418 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2419 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2420 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2421 u8 auto_pause; 2422 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2423 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2424 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2425 __le16 auto_link_speed; 2426 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2427 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2428 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2429 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2430 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2431 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2432 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2433 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2434 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2435 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2436 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL 2437 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2438 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2439 __le16 auto_link_speed_mask; 2440 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2441 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2442 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2443 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2444 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2445 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2446 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2447 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2448 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2449 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2450 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2451 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2452 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2453 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2454 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2455 u8 wirespeed; 2456 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2457 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2458 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2459 u8 lpbk; 2460 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2461 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2462 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2463 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2464 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2465 u8 force_pause; 2466 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2467 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2468 u8 module_status; 2469 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2470 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2471 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2472 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2473 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2474 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2475 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2476 __le32 preemphasis; 2477 u8 phy_maj; 2478 u8 phy_min; 2479 u8 phy_bld; 2480 u8 phy_type; 2481 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2482 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2483 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2484 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2485 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2486 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2487 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2488 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2489 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2490 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2491 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2492 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2493 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2494 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2495 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2496 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2497 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2498 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2499 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2500 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2501 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2502 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2503 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2504 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2505 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2506 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2507 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2508 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2509 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2510 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2511 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2512 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2513 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2514 u8 media_type; 2515 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2516 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2517 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2518 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2519 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2520 u8 xcvr_pkg_type; 2521 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2522 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2523 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2524 u8 eee_config_phy_addr; 2525 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2526 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2527 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2528 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2529 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2530 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2531 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2532 u8 parallel_detect; 2533 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2534 __le16 link_partner_adv_speeds; 2535 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2536 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2537 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2538 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2539 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2540 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2541 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2542 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2543 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2544 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2545 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2546 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2547 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2548 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2549 u8 link_partner_adv_auto_mode; 2550 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2551 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2552 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2553 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2554 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2555 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2556 u8 link_partner_adv_pause; 2557 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2558 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2559 __le16 adv_eee_link_speed_mask; 2560 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2561 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2562 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2563 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2564 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2565 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2566 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2567 __le16 link_partner_adv_eee_link_speed_mask; 2568 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2569 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2570 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2571 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2572 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2573 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2574 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2575 __le32 xcvr_identifier_type_tx_lpi_timer; 2576 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2577 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2578 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2579 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2580 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2581 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2582 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2583 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2584 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2585 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2586 __le16 fec_cfg; 2587 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2588 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2589 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2590 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2591 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2592 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2593 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2594 u8 duplex_state; 2595 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2596 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2597 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2598 u8 option_flags; 2599 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2600 char phy_vendor_name[16]; 2601 char phy_vendor_partnumber[16]; 2602 u8 unused_2[7]; 2603 u8 valid; 2604}; 2605 2606/* hwrm_port_mac_cfg_input (size:384b/48B) */ 2607struct hwrm_port_mac_cfg_input { 2608 __le16 req_type; 2609 __le16 cmpl_ring; 2610 __le16 seq_id; 2611 __le16 target_id; 2612 __le64 resp_addr; 2613 __le32 flags; 2614 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2615 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2616 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2617 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2618 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2619 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2620 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2621 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2622 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2623 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2624 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2625 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2626 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2627 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 2628 __le32 enables; 2629 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2630 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2631 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2632 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2633 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2634 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2635 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2636 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2637 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 2638 __le16 port_id; 2639 u8 ipg; 2640 u8 lpbk; 2641 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2642 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2643 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2644 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2645 u8 vlan_pri2cos_map_pri; 2646 u8 reserved1; 2647 u8 tunnel_pri2cos_map_pri; 2648 u8 dscp2pri_map_pri; 2649 __le16 rx_ts_capture_ptp_msg_type; 2650 __le16 tx_ts_capture_ptp_msg_type; 2651 u8 cos_field_cfg; 2652 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2653 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2654 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2655 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2656 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2657 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2658 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2659 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2660 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2661 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2662 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2663 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2664 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2665 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2666 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2667 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2668 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2669 u8 unused_0[3]; 2670 __s32 ptp_freq_adj_ppb; 2671 u8 unused_1[4]; 2672}; 2673 2674/* hwrm_port_mac_cfg_output (size:128b/16B) */ 2675struct hwrm_port_mac_cfg_output { 2676 __le16 error_code; 2677 __le16 req_type; 2678 __le16 seq_id; 2679 __le16 resp_len; 2680 __le16 mru; 2681 __le16 mtu; 2682 u8 ipg; 2683 u8 lpbk; 2684 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2685 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2686 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2687 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2688 u8 unused_0; 2689 u8 valid; 2690}; 2691 2692/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2693struct hwrm_port_mac_ptp_qcfg_input { 2694 __le16 req_type; 2695 __le16 cmpl_ring; 2696 __le16 seq_id; 2697 __le16 target_id; 2698 __le64 resp_addr; 2699 __le16 port_id; 2700 u8 unused_0[6]; 2701}; 2702 2703/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2704struct hwrm_port_mac_ptp_qcfg_output { 2705 __le16 error_code; 2706 __le16 req_type; 2707 __le16 seq_id; 2708 __le16 resp_len; 2709 u8 flags; 2710 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2711 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 2712 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 2713 u8 unused_0[3]; 2714 __le32 rx_ts_reg_off_lower; 2715 __le32 rx_ts_reg_off_upper; 2716 __le32 rx_ts_reg_off_seq_id; 2717 __le32 rx_ts_reg_off_src_id_0; 2718 __le32 rx_ts_reg_off_src_id_1; 2719 __le32 rx_ts_reg_off_src_id_2; 2720 __le32 rx_ts_reg_off_domain_id; 2721 __le32 rx_ts_reg_off_fifo; 2722 __le32 rx_ts_reg_off_fifo_adv; 2723 __le32 rx_ts_reg_off_granularity; 2724 __le32 tx_ts_reg_off_lower; 2725 __le32 tx_ts_reg_off_upper; 2726 __le32 tx_ts_reg_off_seq_id; 2727 __le32 tx_ts_reg_off_fifo; 2728 __le32 tx_ts_reg_off_granularity; 2729 u8 unused_1[7]; 2730 u8 valid; 2731}; 2732 2733/* tx_port_stats (size:3264b/408B) */ 2734struct tx_port_stats { 2735 __le64 tx_64b_frames; 2736 __le64 tx_65b_127b_frames; 2737 __le64 tx_128b_255b_frames; 2738 __le64 tx_256b_511b_frames; 2739 __le64 tx_512b_1023b_frames; 2740 __le64 tx_1024b_1518b_frames; 2741 __le64 tx_good_vlan_frames; 2742 __le64 tx_1519b_2047b_frames; 2743 __le64 tx_2048b_4095b_frames; 2744 __le64 tx_4096b_9216b_frames; 2745 __le64 tx_9217b_16383b_frames; 2746 __le64 tx_good_frames; 2747 __le64 tx_total_frames; 2748 __le64 tx_ucast_frames; 2749 __le64 tx_mcast_frames; 2750 __le64 tx_bcast_frames; 2751 __le64 tx_pause_frames; 2752 __le64 tx_pfc_frames; 2753 __le64 tx_jabber_frames; 2754 __le64 tx_fcs_err_frames; 2755 __le64 tx_control_frames; 2756 __le64 tx_oversz_frames; 2757 __le64 tx_single_dfrl_frames; 2758 __le64 tx_multi_dfrl_frames; 2759 __le64 tx_single_coll_frames; 2760 __le64 tx_multi_coll_frames; 2761 __le64 tx_late_coll_frames; 2762 __le64 tx_excessive_coll_frames; 2763 __le64 tx_frag_frames; 2764 __le64 tx_err; 2765 __le64 tx_tagged_frames; 2766 __le64 tx_dbl_tagged_frames; 2767 __le64 tx_runt_frames; 2768 __le64 tx_fifo_underruns; 2769 __le64 tx_pfc_ena_frames_pri0; 2770 __le64 tx_pfc_ena_frames_pri1; 2771 __le64 tx_pfc_ena_frames_pri2; 2772 __le64 tx_pfc_ena_frames_pri3; 2773 __le64 tx_pfc_ena_frames_pri4; 2774 __le64 tx_pfc_ena_frames_pri5; 2775 __le64 tx_pfc_ena_frames_pri6; 2776 __le64 tx_pfc_ena_frames_pri7; 2777 __le64 tx_eee_lpi_events; 2778 __le64 tx_eee_lpi_duration; 2779 __le64 tx_llfc_logical_msgs; 2780 __le64 tx_hcfc_msgs; 2781 __le64 tx_total_collisions; 2782 __le64 tx_bytes; 2783 __le64 tx_xthol_frames; 2784 __le64 tx_stat_discard; 2785 __le64 tx_stat_error; 2786}; 2787 2788/* rx_port_stats (size:4224b/528B) */ 2789struct rx_port_stats { 2790 __le64 rx_64b_frames; 2791 __le64 rx_65b_127b_frames; 2792 __le64 rx_128b_255b_frames; 2793 __le64 rx_256b_511b_frames; 2794 __le64 rx_512b_1023b_frames; 2795 __le64 rx_1024b_1518b_frames; 2796 __le64 rx_good_vlan_frames; 2797 __le64 rx_1519b_2047b_frames; 2798 __le64 rx_2048b_4095b_frames; 2799 __le64 rx_4096b_9216b_frames; 2800 __le64 rx_9217b_16383b_frames; 2801 __le64 rx_total_frames; 2802 __le64 rx_ucast_frames; 2803 __le64 rx_mcast_frames; 2804 __le64 rx_bcast_frames; 2805 __le64 rx_fcs_err_frames; 2806 __le64 rx_ctrl_frames; 2807 __le64 rx_pause_frames; 2808 __le64 rx_pfc_frames; 2809 __le64 rx_unsupported_opcode_frames; 2810 __le64 rx_unsupported_da_pausepfc_frames; 2811 __le64 rx_wrong_sa_frames; 2812 __le64 rx_align_err_frames; 2813 __le64 rx_oor_len_frames; 2814 __le64 rx_code_err_frames; 2815 __le64 rx_false_carrier_frames; 2816 __le64 rx_ovrsz_frames; 2817 __le64 rx_jbr_frames; 2818 __le64 rx_mtu_err_frames; 2819 __le64 rx_match_crc_frames; 2820 __le64 rx_promiscuous_frames; 2821 __le64 rx_tagged_frames; 2822 __le64 rx_double_tagged_frames; 2823 __le64 rx_trunc_frames; 2824 __le64 rx_good_frames; 2825 __le64 rx_pfc_xon2xoff_frames_pri0; 2826 __le64 rx_pfc_xon2xoff_frames_pri1; 2827 __le64 rx_pfc_xon2xoff_frames_pri2; 2828 __le64 rx_pfc_xon2xoff_frames_pri3; 2829 __le64 rx_pfc_xon2xoff_frames_pri4; 2830 __le64 rx_pfc_xon2xoff_frames_pri5; 2831 __le64 rx_pfc_xon2xoff_frames_pri6; 2832 __le64 rx_pfc_xon2xoff_frames_pri7; 2833 __le64 rx_pfc_ena_frames_pri0; 2834 __le64 rx_pfc_ena_frames_pri1; 2835 __le64 rx_pfc_ena_frames_pri2; 2836 __le64 rx_pfc_ena_frames_pri3; 2837 __le64 rx_pfc_ena_frames_pri4; 2838 __le64 rx_pfc_ena_frames_pri5; 2839 __le64 rx_pfc_ena_frames_pri6; 2840 __le64 rx_pfc_ena_frames_pri7; 2841 __le64 rx_sch_crc_err_frames; 2842 __le64 rx_undrsz_frames; 2843 __le64 rx_frag_frames; 2844 __le64 rx_eee_lpi_events; 2845 __le64 rx_eee_lpi_duration; 2846 __le64 rx_llfc_physical_msgs; 2847 __le64 rx_llfc_logical_msgs; 2848 __le64 rx_llfc_msgs_with_crc_err; 2849 __le64 rx_hcfc_msgs; 2850 __le64 rx_hcfc_msgs_with_crc_err; 2851 __le64 rx_bytes; 2852 __le64 rx_runt_bytes; 2853 __le64 rx_runt_frames; 2854 __le64 rx_stat_discard; 2855 __le64 rx_stat_err; 2856}; 2857 2858/* hwrm_port_qstats_input (size:320b/40B) */ 2859struct hwrm_port_qstats_input { 2860 __le16 req_type; 2861 __le16 cmpl_ring; 2862 __le16 seq_id; 2863 __le16 target_id; 2864 __le64 resp_addr; 2865 __le16 port_id; 2866 u8 unused_0[6]; 2867 __le64 tx_stat_host_addr; 2868 __le64 rx_stat_host_addr; 2869}; 2870 2871/* hwrm_port_qstats_output (size:128b/16B) */ 2872struct hwrm_port_qstats_output { 2873 __le16 error_code; 2874 __le16 req_type; 2875 __le16 seq_id; 2876 __le16 resp_len; 2877 __le16 tx_stat_size; 2878 __le16 rx_stat_size; 2879 u8 unused_0[3]; 2880 u8 valid; 2881}; 2882 2883/* tx_port_stats_ext (size:2048b/256B) */ 2884struct tx_port_stats_ext { 2885 __le64 tx_bytes_cos0; 2886 __le64 tx_bytes_cos1; 2887 __le64 tx_bytes_cos2; 2888 __le64 tx_bytes_cos3; 2889 __le64 tx_bytes_cos4; 2890 __le64 tx_bytes_cos5; 2891 __le64 tx_bytes_cos6; 2892 __le64 tx_bytes_cos7; 2893 __le64 tx_packets_cos0; 2894 __le64 tx_packets_cos1; 2895 __le64 tx_packets_cos2; 2896 __le64 tx_packets_cos3; 2897 __le64 tx_packets_cos4; 2898 __le64 tx_packets_cos5; 2899 __le64 tx_packets_cos6; 2900 __le64 tx_packets_cos7; 2901 __le64 pfc_pri0_tx_duration_us; 2902 __le64 pfc_pri0_tx_transitions; 2903 __le64 pfc_pri1_tx_duration_us; 2904 __le64 pfc_pri1_tx_transitions; 2905 __le64 pfc_pri2_tx_duration_us; 2906 __le64 pfc_pri2_tx_transitions; 2907 __le64 pfc_pri3_tx_duration_us; 2908 __le64 pfc_pri3_tx_transitions; 2909 __le64 pfc_pri4_tx_duration_us; 2910 __le64 pfc_pri4_tx_transitions; 2911 __le64 pfc_pri5_tx_duration_us; 2912 __le64 pfc_pri5_tx_transitions; 2913 __le64 pfc_pri6_tx_duration_us; 2914 __le64 pfc_pri6_tx_transitions; 2915 __le64 pfc_pri7_tx_duration_us; 2916 __le64 pfc_pri7_tx_transitions; 2917}; 2918 2919/* rx_port_stats_ext (size:2624b/328B) */ 2920struct rx_port_stats_ext { 2921 __le64 link_down_events; 2922 __le64 continuous_pause_events; 2923 __le64 resume_pause_events; 2924 __le64 continuous_roce_pause_events; 2925 __le64 resume_roce_pause_events; 2926 __le64 rx_bytes_cos0; 2927 __le64 rx_bytes_cos1; 2928 __le64 rx_bytes_cos2; 2929 __le64 rx_bytes_cos3; 2930 __le64 rx_bytes_cos4; 2931 __le64 rx_bytes_cos5; 2932 __le64 rx_bytes_cos6; 2933 __le64 rx_bytes_cos7; 2934 __le64 rx_packets_cos0; 2935 __le64 rx_packets_cos1; 2936 __le64 rx_packets_cos2; 2937 __le64 rx_packets_cos3; 2938 __le64 rx_packets_cos4; 2939 __le64 rx_packets_cos5; 2940 __le64 rx_packets_cos6; 2941 __le64 rx_packets_cos7; 2942 __le64 pfc_pri0_rx_duration_us; 2943 __le64 pfc_pri0_rx_transitions; 2944 __le64 pfc_pri1_rx_duration_us; 2945 __le64 pfc_pri1_rx_transitions; 2946 __le64 pfc_pri2_rx_duration_us; 2947 __le64 pfc_pri2_rx_transitions; 2948 __le64 pfc_pri3_rx_duration_us; 2949 __le64 pfc_pri3_rx_transitions; 2950 __le64 pfc_pri4_rx_duration_us; 2951 __le64 pfc_pri4_rx_transitions; 2952 __le64 pfc_pri5_rx_duration_us; 2953 __le64 pfc_pri5_rx_transitions; 2954 __le64 pfc_pri6_rx_duration_us; 2955 __le64 pfc_pri6_rx_transitions; 2956 __le64 pfc_pri7_rx_duration_us; 2957 __le64 pfc_pri7_rx_transitions; 2958 __le64 rx_bits; 2959 __le64 rx_buffer_passed_threshold; 2960 __le64 rx_pcs_symbol_err; 2961 __le64 rx_corrected_bits; 2962}; 2963 2964/* hwrm_port_qstats_ext_input (size:320b/40B) */ 2965struct hwrm_port_qstats_ext_input { 2966 __le16 req_type; 2967 __le16 cmpl_ring; 2968 __le16 seq_id; 2969 __le16 target_id; 2970 __le64 resp_addr; 2971 __le16 port_id; 2972 __le16 tx_stat_size; 2973 __le16 rx_stat_size; 2974 u8 unused_0[2]; 2975 __le64 tx_stat_host_addr; 2976 __le64 rx_stat_host_addr; 2977}; 2978 2979/* hwrm_port_qstats_ext_output (size:128b/16B) */ 2980struct hwrm_port_qstats_ext_output { 2981 __le16 error_code; 2982 __le16 req_type; 2983 __le16 seq_id; 2984 __le16 resp_len; 2985 __le16 tx_stat_size; 2986 __le16 rx_stat_size; 2987 __le16 total_active_cos_queues; 2988 u8 flags; 2989 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 2990 u8 valid; 2991}; 2992 2993/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 2994struct hwrm_port_lpbk_qstats_input { 2995 __le16 req_type; 2996 __le16 cmpl_ring; 2997 __le16 seq_id; 2998 __le16 target_id; 2999 __le64 resp_addr; 3000};
3001 3002/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3003struct hwrm_port_lpbk_qstats_output { 3004 __le16 error_code; 3005 __le16 req_type; 3006 __le16 seq_id; 3007 __le16 resp_len; 3008 __le64 lpbk_ucast_frames; 3009 __le64 lpbk_mcast_frames; 3010 __le64 lpbk_bcast_frames; 3011 __le64 lpbk_ucast_bytes; 3012 __le64 lpbk_mcast_bytes; 3013 __le64 lpbk_bcast_bytes; 3014 __le64 tx_stat_discard; 3015 __le64 tx_stat_error; 3016 __le64 rx_stat_discard; 3017 __le64 rx_stat_error; 3018 u8 unused_0[7]; 3019 u8 valid; 3020}; 3021 3022/* hwrm_port_clr_stats_input (size:192b/24B) */ 3023struct hwrm_port_clr_stats_input { 3024 __le16 req_type; 3025 __le16 cmpl_ring; 3026 __le16 seq_id; 3027 __le16 target_id; 3028 __le64 resp_addr; 3029 __le16 port_id; 3030 u8 flags; 3031 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3032 u8 unused_0[5]; 3033}; 3034 3035/* hwrm_port_clr_stats_output (size:128b/16B) */ 3036struct hwrm_port_clr_stats_output { 3037 __le16 error_code; 3038 __le16 req_type; 3039 __le16 seq_id; 3040 __le16 resp_len; 3041 u8 unused_0[7]; 3042 u8 valid; 3043}; 3044 3045/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3046struct hwrm_port_lpbk_clr_stats_input { 3047 __le16 req_type; 3048 __le16 cmpl_ring; 3049 __le16 seq_id; 3050 __le16 target_id; 3051 __le64 resp_addr; 3052}; 3053 3054/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3055struct hwrm_port_lpbk_clr_stats_output { 3056 __le16 error_code; 3057 __le16 req_type; 3058 __le16 seq_id; 3059 __le16 resp_len; 3060 u8 unused_0[7]; 3061 u8 valid; 3062}; 3063 3064/* hwrm_port_ts_query_input (size:192b/24B) */ 3065struct hwrm_port_ts_query_input { 3066 __le16 req_type; 3067 __le16 cmpl_ring; 3068 __le16 seq_id; 3069 __le16 target_id; 3070 __le64 resp_addr; 3071 __le32 flags; 3072 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3073 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3074 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3075 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3076 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3077 __le16 port_id; 3078 u8 unused_0[2]; 3079}; 3080 3081/* hwrm_port_ts_query_output (size:192b/24B) */ 3082struct hwrm_port_ts_query_output { 3083 __le16 error_code; 3084 __le16 req_type; 3085 __le16 seq_id; 3086 __le16 resp_len; 3087 __le64 ptp_msg_ts; 3088 __le16 ptp_msg_seqid; 3089 u8 unused_0[5]; 3090 u8 valid; 3091}; 3092 3093/* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3094struct hwrm_port_phy_qcaps_input { 3095 __le16 req_type; 3096 __le16 cmpl_ring; 3097 __le16 seq_id; 3098 __le16 target_id; 3099 __le64 resp_addr; 3100 __le16 port_id; 3101 u8 unused_0[6]; 3102}; 3103 3104/* hwrm_port_phy_qcaps_output (size:192b/24B) */ 3105struct hwrm_port_phy_qcaps_output { 3106 __le16 error_code; 3107 __le16 req_type; 3108 __le16 seq_id; 3109 __le16 resp_len; 3110 u8 flags; 3111 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3112 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3113 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL 3114 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2 3115 u8 port_cnt; 3116 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3117 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3118 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3119 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3120 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3121 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3122 __le16 supported_speeds_force_mode; 3123 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3124 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3125 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3126 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3127 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3128 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3129 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3130 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3131 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3132 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3133 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3134 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3135 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3136 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3137 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB 0x4000UL 3138 __le16 supported_speeds_auto_mode; 3139 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3140 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3141 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3142 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3143 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3144 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3145 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3146 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3147 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3148 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3149 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3150 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3151 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3152 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3153 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB 0x4000UL 3154 __le16 supported_speeds_eee_mode; 3155 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3156 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3157 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3158 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3159 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3160 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3161 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3162 __le32 tx_lpi_timer_low; 3163 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3164 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3165 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3166 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3167 __le32 valid_tx_lpi_timer_high; 3168 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3169 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3170 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 3171 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 3172}; 3173 3174/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3175struct hwrm_port_phy_i2c_read_input { 3176 __le16 req_type; 3177 __le16 cmpl_ring; 3178 __le16 seq_id; 3179 __le16 target_id; 3180 __le64 resp_addr; 3181 __le32 flags; 3182 __le32 enables; 3183 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3184 __le16 port_id; 3185 u8 i2c_slave_addr; 3186 u8 unused_0; 3187 __le16 page_number; 3188 __le16 page_offset; 3189 u8 data_length; 3190 u8 unused_1[7]; 3191}; 3192 3193/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3194struct hwrm_port_phy_i2c_read_output { 3195 __le16 error_code; 3196 __le16 req_type; 3197 __le16 seq_id; 3198 __le16 resp_len; 3199 __le32 data[16]; 3200 u8 unused_0[7]; 3201 u8 valid; 3202}; 3203 3204/* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3205struct hwrm_port_phy_mdio_write_input { 3206 __le16 req_type; 3207 __le16 cmpl_ring; 3208 __le16 seq_id; 3209 __le16 target_id; 3210 __le64 resp_addr; 3211 __le32 unused_0[2]; 3212 __le16 port_id; 3213 u8 phy_addr; 3214 u8 dev_addr; 3215 __le16 reg_addr; 3216 __le16 reg_data; 3217 u8 cl45_mdio; 3218 u8 unused_1[7]; 3219}; 3220 3221/* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3222struct hwrm_port_phy_mdio_write_output { 3223 __le16 error_code; 3224 __le16 req_type; 3225 __le16 seq_id; 3226 __le16 resp_len; 3227 u8 unused_0[7]; 3228 u8 valid; 3229}; 3230 3231/* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3232struct hwrm_port_phy_mdio_read_input { 3233 __le16 req_type; 3234 __le16 cmpl_ring; 3235 __le16 seq_id; 3236 __le16 target_id; 3237 __le64 resp_addr; 3238 __le32 unused_0[2]; 3239 __le16 port_id; 3240 u8 phy_addr; 3241 u8 dev_addr; 3242 __le16 reg_addr; 3243 u8 cl45_mdio; 3244 u8 unused_1; 3245}; 3246 3247/* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3248struct hwrm_port_phy_mdio_read_output { 3249 __le16 error_code; 3250 __le16 req_type; 3251 __le16 seq_id; 3252 __le16 resp_len; 3253 __le16 reg_data; 3254 u8 unused_0[5]; 3255 u8 valid; 3256}; 3257 3258/* hwrm_port_led_cfg_input (size:512b/64B) */ 3259struct hwrm_port_led_cfg_input { 3260 __le16 req_type; 3261 __le16 cmpl_ring; 3262 __le16 seq_id; 3263 __le16 target_id; 3264 __le64 resp_addr; 3265 __le32 enables; 3266 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3267 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3268 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3269 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3270 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3271 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3272 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3273 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3274 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3275 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3276 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3277 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3278 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3279 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3280 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3281 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3282 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3283 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3284 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3285 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3286 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3287 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3288 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3289 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3290 __le16 port_id; 3291 u8 num_leds; 3292 u8 rsvd; 3293 u8 led0_id; 3294 u8 led0_state; 3295 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3296 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3297 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3298 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3299 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3300 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3301 u8 led0_color; 3302 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3303 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3304 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3305 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3306 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3307 u8 unused_0; 3308 __le16 led0_blink_on; 3309 __le16 led0_blink_off; 3310 u8 led0_group_id; 3311 u8 rsvd0; 3312 u8 led1_id; 3313 u8 led1_state; 3314 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3315 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3316 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3317 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3318 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3319 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3320 u8 led1_color; 3321 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3322 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3323 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3324 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3325 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3326 u8 unused_1; 3327 __le16 led1_blink_on; 3328 __le16 led1_blink_off; 3329 u8 led1_group_id; 3330 u8 rsvd1; 3331 u8 led2_id; 3332 u8 led2_state; 3333 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3334 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3335 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3336 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3337 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3338 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3339 u8 led2_color; 3340 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3341 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3342 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3343 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3344 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3345 u8 unused_2; 3346 __le16 led2_blink_on; 3347 __le16 led2_blink_off; 3348 u8 led2_group_id; 3349 u8 rsvd2; 3350 u8 led3_id; 3351 u8 led3_state; 3352 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3353 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3354 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3355 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3356 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3357 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3358 u8 led3_color; 3359 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3360 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3361 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3362 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3363 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3364 u8 unused_3; 3365 __le16 led3_blink_on; 3366 __le16 led3_blink_off; 3367 u8 led3_group_id; 3368 u8 rsvd3; 3369}; 3370 3371/* hwrm_port_led_cfg_output (size:128b/16B) */ 3372struct hwrm_port_led_cfg_output { 3373 __le16 error_code; 3374 __le16 req_type; 3375 __le16 seq_id; 3376 __le16 resp_len; 3377 u8 unused_0[7]; 3378 u8 valid; 3379}; 3380 3381/* hwrm_port_led_qcfg_input (size:192b/24B) */ 3382struct hwrm_port_led_qcfg_input { 3383 __le16 req_type; 3384 __le16 cmpl_ring; 3385 __le16 seq_id; 3386 __le16 target_id; 3387 __le64 resp_addr; 3388 __le16 port_id; 3389 u8 unused_0[6]; 3390}; 3391 3392/* hwrm_port_led_qcfg_output (size:448b/56B) */ 3393struct hwrm_port_led_qcfg_output { 3394 __le16 error_code; 3395 __le16 req_type; 3396 __le16 seq_id; 3397 __le16 resp_len; 3398 u8 num_leds; 3399 u8 led0_id; 3400 u8 led0_type; 3401 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3402 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3403 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3404 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3405 u8 led0_state; 3406 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3407 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3408 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3409 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3410 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3411 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3412 u8 led0_color; 3413 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3414 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3415 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3416 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3417 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3418 u8 unused_0; 3419 __le16 led0_blink_on; 3420 __le16 led0_blink_off; 3421 u8 led0_group_id; 3422 u8 led1_id; 3423 u8 led1_type; 3424 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3425 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3426 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3427 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3428 u8 led1_state; 3429 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3430 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3431 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3432 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3433 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3434 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3435 u8 led1_color; 3436 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3437 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3438 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3439 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3440 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3441 u8 unused_1; 3442 __le16 led1_blink_on; 3443 __le16 led1_blink_off; 3444 u8 led1_group_id; 3445 u8 led2_id; 3446 u8 led2_type; 3447 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3448 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3449 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3450 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3451 u8 led2_state; 3452 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3453 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3454 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3455 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3456 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3457 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3458 u8 led2_color; 3459 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3460 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3461 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3462 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3463 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3464 u8 unused_2; 3465 __le16 led2_blink_on; 3466 __le16 led2_blink_off; 3467 u8 led2_group_id; 3468 u8 led3_id; 3469 u8 led3_type; 3470 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3471 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3472 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3473 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3474 u8 led3_state; 3475 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3476 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3477 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3478 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3479 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3480 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3481 u8 led3_color; 3482 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3483 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3484 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3485 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3486 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3487 u8 unused_3; 3488 __le16 led3_blink_on; 3489 __le16 led3_blink_off; 3490 u8 led3_group_id; 3491 u8 unused_4[6]; 3492 u8 valid; 3493}; 3494 3495/* hwrm_port_led_qcaps_input (size:192b/24B) */ 3496struct hwrm_port_led_qcaps_input { 3497 __le16 req_type; 3498 __le16 cmpl_ring; 3499 __le16 seq_id; 3500 __le16 target_id; 3501 __le64 resp_addr; 3502 __le16 port_id; 3503 u8 unused_0[6]; 3504}; 3505 3506/* hwrm_port_led_qcaps_output (size:384b/48B) */ 3507struct hwrm_port_led_qcaps_output { 3508 __le16 error_code; 3509 __le16 req_type; 3510 __le16 seq_id; 3511 __le16 resp_len; 3512 u8 num_leds; 3513 u8 unused[3]; 3514 u8 led0_id; 3515 u8 led0_type; 3516 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3517 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3518 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3519 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3520 u8 led0_group_id; 3521 u8 unused_0; 3522 __le16 led0_state_caps; 3523 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3524 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3525 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3526 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3527 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3528 __le16 led0_color_caps; 3529 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3530 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3531 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3532 u8 led1_id; 3533 u8 led1_type; 3534 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3535 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3536 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3537 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3538 u8 led1_group_id; 3539 u8 unused_1; 3540 __le16 led1_state_caps; 3541 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3542 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3543 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3544 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3545 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3546 __le16 led1_color_caps; 3547 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3548 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3549 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3550 u8 led2_id; 3551 u8 led2_type; 3552 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3553 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3554 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3555 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3556 u8 led2_group_id; 3557 u8 unused_2; 3558 __le16 led2_state_caps; 3559 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3560 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3561 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3562 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3563 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3564 __le16 led2_color_caps; 3565 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3566 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3567 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3568 u8 led3_id; 3569 u8 led3_type; 3570 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3571 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3572 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3573 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3574 u8 led3_group_id; 3575 u8 unused_3; 3576 __le16 led3_state_caps; 3577 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3578 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3579 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3580 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3581 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3582 __le16 led3_color_caps; 3583 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3584 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3585 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3586 u8 unused_4[3]; 3587 u8 valid; 3588}; 3589 3590/* hwrm_queue_qportcfg_input (size:192b/24B) */ 3591struct hwrm_queue_qportcfg_input { 3592 __le16 req_type; 3593 __le16 cmpl_ring; 3594 __le16 seq_id; 3595 __le16 target_id; 3596 __le64 resp_addr; 3597 __le32 flags; 3598 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3599 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3600 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3601 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3602 __le16 port_id; 3603 u8 drv_qmap_cap; 3604 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3605 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3606 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3607 u8 unused_0; 3608}; 3609 3610/* hwrm_queue_qportcfg_output (size:256b/32B) */ 3611struct hwrm_queue_qportcfg_output { 3612 __le16 error_code; 3613 __le16 req_type; 3614 __le16 seq_id; 3615 __le16 resp_len; 3616 u8 max_configurable_queues; 3617 u8 max_configurable_lossless_queues; 3618 u8 queue_cfg_allowed; 3619 u8 queue_cfg_info; 3620 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3621 u8 queue_pfcenable_cfg_allowed; 3622 u8 queue_pri2cos_cfg_allowed; 3623 u8 queue_cos2bw_cfg_allowed; 3624 u8 queue_id0; 3625 u8 queue_id0_service_profile; 3626 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3627 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3628 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3629 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3630 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3631 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3632 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3633 u8 queue_id1; 3634 u8 queue_id1_service_profile; 3635 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3636 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3637 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3638 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3639 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3640 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3641 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3642 u8 queue_id2; 3643 u8 queue_id2_service_profile; 3644 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3645 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3646 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3647 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3648 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3649 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3650 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3651 u8 queue_id3; 3652 u8 queue_id3_service_profile; 3653 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3654 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3655 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3656 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3657 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3658 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3659 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3660 u8 queue_id4; 3661 u8 queue_id4_service_profile; 3662 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3663 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3664 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3665 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3666 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3667 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3668 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3669 u8 queue_id5; 3670 u8 queue_id5_service_profile; 3671 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3672 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3673 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3674 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3675 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3676 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3677 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3678 u8 queue_id6; 3679 u8 queue_id6_service_profile; 3680 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3681 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3682 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3683 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3684 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3685 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3686 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3687 u8 queue_id7; 3688 u8 queue_id7_service_profile; 3689 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3690 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3691 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3692 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3693 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3694 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3695 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3696 u8 valid; 3697}; 3698 3699/* hwrm_queue_cfg_input (size:320b/40B) */ 3700struct hwrm_queue_cfg_input { 3701 __le16 req_type; 3702 __le16 cmpl_ring; 3703 __le16 seq_id; 3704 __le16 target_id; 3705 __le64 resp_addr; 3706 __le32 flags; 3707 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3708 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 3709 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 3710 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 3711 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3712 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 3713 __le32 enables; 3714 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 3715 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 3716 __le32 queue_id; 3717 __le32 dflt_len; 3718 u8 service_profile; 3719 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 3720 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 3721 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 3722 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 3723 u8 unused_0[7]; 3724}; 3725 3726/* hwrm_queue_cfg_output (size:128b/16B) */ 3727struct hwrm_queue_cfg_output { 3728 __le16 error_code; 3729 __le16 req_type; 3730 __le16 seq_id; 3731 __le16 resp_len; 3732 u8 unused_0[7]; 3733 u8 valid; 3734}; 3735 3736/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 3737struct hwrm_queue_pfcenable_qcfg_input { 3738 __le16 req_type; 3739 __le16 cmpl_ring; 3740 __le16 seq_id; 3741 __le16 target_id; 3742 __le64 resp_addr; 3743 __le16 port_id; 3744 u8 unused_0[6]; 3745}; 3746 3747/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 3748struct hwrm_queue_pfcenable_qcfg_output { 3749 __le16 error_code; 3750 __le16 req_type; 3751 __le16 seq_id; 3752 __le16 resp_len; 3753 __le32 flags; 3754 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 3755 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 3756 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 3757 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 3758 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 3759 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 3760 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 3761 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 3762 u8 unused_0[3]; 3763 u8 valid; 3764}; 3765 3766/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 3767struct hwrm_queue_pfcenable_cfg_input { 3768 __le16 req_type; 3769 __le16 cmpl_ring; 3770 __le16 seq_id; 3771 __le16 target_id; 3772 __le64 resp_addr; 3773 __le32 flags; 3774 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 3775 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 3776 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 3777 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 3778 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 3779 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 3780 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 3781 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 3782 __le16 port_id; 3783 u8 unused_0[2]; 3784}; 3785 3786/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 3787struct hwrm_queue_pfcenable_cfg_output { 3788 __le16 error_code; 3789 __le16 req_type; 3790 __le16 seq_id; 3791 __le16 resp_len; 3792 u8 unused_0[7]; 3793 u8 valid; 3794}; 3795 3796/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 3797struct hwrm_queue_pri2cos_qcfg_input { 3798 __le16 req_type; 3799 __le16 cmpl_ring; 3800 __le16 seq_id; 3801 __le16 target_id; 3802 __le64 resp_addr; 3803 __le32 flags; 3804 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 3805 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 3806 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 3807 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 3808 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 3809 u8 port_id; 3810 u8 unused_0[3]; 3811}; 3812 3813/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 3814struct hwrm_queue_pri2cos_qcfg_output { 3815 __le16 error_code; 3816 __le16 req_type; 3817 __le16 seq_id; 3818 __le16 resp_len; 3819 u8 pri0_cos_queue_id; 3820 u8 pri1_cos_queue_id; 3821 u8 pri2_cos_queue_id; 3822 u8 pri3_cos_queue_id; 3823 u8 pri4_cos_queue_id; 3824 u8 pri5_cos_queue_id; 3825 u8 pri6_cos_queue_id; 3826 u8 pri7_cos_queue_id; 3827 u8 queue_cfg_info; 3828 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3829 u8 unused_0[6]; 3830 u8 valid; 3831}; 3832 3833/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 3834struct hwrm_queue_pri2cos_cfg_input { 3835 __le16 req_type; 3836 __le16 cmpl_ring; 3837 __le16 seq_id; 3838 __le16 target_id; 3839 __le64 resp_addr; 3840 __le32 flags; 3841 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3842 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 3843 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 3844 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 3845 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3846 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 3847 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 3848 __le32 enables; 3849 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 3850 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 3851 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 3852 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 3853 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 3854 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 3855 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 3856 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 3857 u8 port_id; 3858 u8 pri0_cos_queue_id; 3859 u8 pri1_cos_queue_id; 3860 u8 pri2_cos_queue_id; 3861 u8 pri3_cos_queue_id; 3862 u8 pri4_cos_queue_id; 3863 u8 pri5_cos_queue_id; 3864 u8 pri6_cos_queue_id; 3865 u8 pri7_cos_queue_id; 3866 u8 unused_0[7]; 3867}; 3868 3869/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 3870struct hwrm_queue_pri2cos_cfg_output { 3871 __le16 error_code; 3872 __le16 req_type; 3873 __le16 seq_id; 3874 __le16 resp_len; 3875 u8 unused_0[7]; 3876 u8 valid; 3877}; 3878 3879/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 3880struct hwrm_queue_cos2bw_qcfg_input { 3881 __le16 req_type; 3882 __le16 cmpl_ring; 3883 __le16 seq_id; 3884 __le16 target_id; 3885 __le64 resp_addr; 3886 __le16 port_id; 3887 u8 unused_0[6]; 3888}; 3889 3890/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 3891struct hwrm_queue_cos2bw_qcfg_output { 3892 __le16 error_code; 3893 __le16 req_type; 3894 __le16 seq_id; 3895 __le16 resp_len; 3896 u8 queue_id0; 3897 u8 unused_0; 3898 __le16 unused_1; 3899 __le32 queue_id0_min_bw; 3900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3903 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 3906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3910 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3915 __le32 queue_id0_max_bw; 3916 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3917 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3918 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3919 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 3922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3931 u8 queue_id0_tsa_assign; 3932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3934 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3935 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3936 u8 queue_id0_pri_lvl; 3937 u8 queue_id0_bw_weight; 3938 u8 queue_id1; 3939 __le32 queue_id1_min_bw; 3940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 3946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3950 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3955 __le32 queue_id1_max_bw; 3956 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3957 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3958 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3959 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 3962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3971 u8 queue_id1_tsa_assign; 3972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3974 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3975 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3976 u8 queue_id1_pri_lvl; 3977 u8 queue_id1_bw_weight; 3978 u8 queue_id2; 3979 __le32 queue_id2_min_bw; 3980 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3981 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3982 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3983 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 3986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3995 __le32 queue_id2_max_bw; 3996 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3997 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3998 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3999 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
4001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4011 u8 queue_id2_tsa_assign; 4012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4015 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4016 u8 queue_id2_pri_lvl; 4017 u8 queue_id2_bw_weight; 4018 u8 queue_id3; 4019 __le32 queue_id3_min_bw; 4020 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4035 __le32 queue_id3_max_bw; 4036 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4037 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4038 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4039 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4040 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4044 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4051 u8 queue_id3_tsa_assign; 4052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4054 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4055 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4056 u8 queue_id3_pri_lvl; 4057 u8 queue_id3_bw_weight; 4058 u8 queue_id4; 4059 __le32 queue_id4_min_bw; 4060 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4061 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4062 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4063 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4065 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4066 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4067 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4068 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4070 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4071 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4072 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4075 __le32 queue_id4_max_bw; 4076 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4077 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4078 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4079 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4080 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4084 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4091 u8 queue_id4_tsa_assign; 4092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4094 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4095 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4096 u8 queue_id4_pri_lvl; 4097 u8 queue_id4_bw_weight; 4098 u8 queue_id5; 4099 __le32 queue_id5_min_bw; 4100 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4101 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4102 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4103 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4105 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4106 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4107 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4108 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4110 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4111 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4112 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4115 __le32 queue_id5_max_bw; 4116 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4117 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4118 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4119 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4131 u8 queue_id5_tsa_assign; 4132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4135 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4136 u8 queue_id5_pri_lvl; 4137 u8 queue_id5_bw_weight; 4138 u8 queue_id6; 4139 __le32 queue_id6_min_bw; 4140 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4145 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4146 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4147 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4148 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4150 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4151 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4152 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4153 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4154 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4155 __le32 queue_id6_max_bw; 4156 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4157 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4158 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4159 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4160 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4161 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4162 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4163 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4164 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4165 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4171 u8 queue_id6_tsa_assign; 4172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4176 u8 queue_id6_pri_lvl; 4177 u8 queue_id6_bw_weight; 4178 u8 queue_id7; 4179 __le32 queue_id7_min_bw; 4180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4186 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4188 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4192 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4195 __le32 queue_id7_max_bw; 4196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4197 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4198 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4199 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4200 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4202 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4203 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4204 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4205 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4207 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4208 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4209 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4210 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4211 u8 queue_id7_tsa_assign; 4212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4216 u8 queue_id7_pri_lvl; 4217 u8 queue_id7_bw_weight; 4218 u8 unused_2[4]; 4219 u8 valid; 4220}; 4221 4222/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4223struct hwrm_queue_cos2bw_cfg_input { 4224 __le16 req_type; 4225 __le16 cmpl_ring; 4226 __le16 seq_id; 4227 __le16 target_id; 4228 __le64 resp_addr; 4229 __le32 flags; 4230 __le32 enables; 4231 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4232 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4233 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4234 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4235 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4236 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4237 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4238 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4239 __le16 port_id; 4240 u8 queue_id0; 4241 u8 unused_0; 4242 __le32 queue_id0_min_bw; 4243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4253 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4258 __le32 queue_id0_max_bw; 4259 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4260 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4261 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4262 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4274 u8 queue_id0_tsa_assign; 4275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4279 u8 queue_id0_pri_lvl; 4280 u8 queue_id0_bw_weight; 4281 u8 queue_id1; 4282 __le32 queue_id1_min_bw; 4283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4298 __le32 queue_id1_max_bw; 4299 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4300 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4301 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4302 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4314 u8 queue_id1_tsa_assign; 4315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4319 u8 queue_id1_pri_lvl; 4320 u8 queue_id1_bw_weight; 4321 u8 queue_id2; 4322 __le32 queue_id2_min_bw; 4323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4338 __le32 queue_id2_max_bw; 4339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4340 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4354 u8 queue_id2_tsa_assign; 4355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4359 u8 queue_id2_pri_lvl; 4360 u8 queue_id2_bw_weight; 4361 u8 queue_id3; 4362 __le32 queue_id3_min_bw; 4363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4378 __le32 queue_id3_max_bw; 4379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4380 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4381 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4382 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4394 u8 queue_id3_tsa_assign; 4395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4397 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4398 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4399 u8 queue_id3_pri_lvl; 4400 u8 queue_id3_bw_weight; 4401 u8 queue_id4; 4402 __le32 queue_id4_min_bw; 4403 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4404 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4405 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4406 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4418 __le32 queue_id4_max_bw; 4419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4420 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4421 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4422 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4427 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4434 u8 queue_id4_tsa_assign; 4435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4438 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4439 u8 queue_id4_pri_lvl; 4440 u8 queue_id4_bw_weight; 4441 u8 queue_id5; 4442 __le32 queue_id5_min_bw; 4443 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4458 __le32 queue_id5_max_bw; 4459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4462 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4474 u8 queue_id5_tsa_assign; 4475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4479 u8 queue_id5_pri_lvl; 4480 u8 queue_id5_bw_weight; 4481 u8 queue_id6; 4482 __le32 queue_id6_min_bw; 4483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4498 __le32 queue_id6_max_bw; 4499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4500 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4501 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4502 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4514 u8 queue_id6_tsa_assign; 4515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4519 u8 queue_id6_pri_lvl; 4520 u8 queue_id6_bw_weight; 4521 u8 queue_id7; 4522 __le32 queue_id7_min_bw; 4523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4529 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4538 __le32 queue_id7_max_bw; 4539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4540 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4543 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4547 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4554 u8 queue_id7_tsa_assign; 4555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4559 u8 queue_id7_pri_lvl; 4560 u8 queue_id7_bw_weight; 4561 u8 unused_1[5]; 4562}; 4563 4564/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4565struct hwrm_queue_cos2bw_cfg_output { 4566 __le16 error_code; 4567 __le16 req_type; 4568 __le16 seq_id; 4569 __le16 resp_len; 4570 u8 unused_0[7]; 4571 u8 valid; 4572}; 4573 4574/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4575struct hwrm_queue_dscp_qcaps_input { 4576 __le16 req_type; 4577 __le16 cmpl_ring; 4578 __le16 seq_id; 4579 __le16 target_id; 4580 __le64 resp_addr; 4581 u8 port_id; 4582 u8 unused_0[7]; 4583}; 4584 4585/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4586struct hwrm_queue_dscp_qcaps_output { 4587 __le16 error_code; 4588 __le16 req_type; 4589 __le16 seq_id; 4590 __le16 resp_len; 4591 u8 num_dscp_bits; 4592 u8 unused_0; 4593 __le16 max_entries; 4594 u8 unused_1[3]; 4595 u8 valid; 4596}; 4597 4598/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4599struct hwrm_queue_dscp2pri_qcfg_input { 4600 __le16 req_type; 4601 __le16 cmpl_ring; 4602 __le16 seq_id; 4603 __le16 target_id; 4604 __le64 resp_addr; 4605 __le64 dest_data_addr; 4606 u8 port_id; 4607 u8 unused_0; 4608 __le16 dest_data_buffer_size; 4609 u8 unused_1[4]; 4610}; 4611 4612/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4613struct hwrm_queue_dscp2pri_qcfg_output { 4614 __le16 error_code; 4615 __le16 req_type; 4616 __le16 seq_id; 4617 __le16 resp_len; 4618 __le16 entry_cnt; 4619 u8 default_pri; 4620 u8 unused_0[4]; 4621 u8 valid; 4622}; 4623 4624/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4625struct hwrm_queue_dscp2pri_cfg_input { 4626 __le16 req_type; 4627 __le16 cmpl_ring; 4628 __le16 seq_id; 4629 __le16 target_id; 4630 __le64 resp_addr; 4631 __le64 src_data_addr; 4632 __le32 flags; 4633 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4634 __le32 enables; 4635 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4636 u8 port_id; 4637 u8 default_pri; 4638 __le16 entry_cnt; 4639 u8 unused_0[4]; 4640}; 4641 4642/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4643struct hwrm_queue_dscp2pri_cfg_output { 4644 __le16 error_code; 4645 __le16 req_type; 4646 __le16 seq_id; 4647 __le16 resp_len; 4648 u8 unused_0[7]; 4649 u8 valid; 4650}; 4651 4652/* hwrm_vnic_alloc_input (size:192b/24B) */ 4653struct hwrm_vnic_alloc_input { 4654 __le16 req_type; 4655 __le16 cmpl_ring; 4656 __le16 seq_id; 4657 __le16 target_id; 4658 __le64 resp_addr; 4659 __le32 flags; 4660 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 4661 u8 unused_0[4]; 4662}; 4663 4664/* hwrm_vnic_alloc_output (size:128b/16B) */ 4665struct hwrm_vnic_alloc_output { 4666 __le16 error_code; 4667 __le16 req_type; 4668 __le16 seq_id; 4669 __le16 resp_len; 4670 __le32 vnic_id; 4671 u8 unused_0[3]; 4672 u8 valid; 4673}; 4674 4675/* hwrm_vnic_free_input (size:192b/24B) */ 4676struct hwrm_vnic_free_input { 4677 __le16 req_type; 4678 __le16 cmpl_ring; 4679 __le16 seq_id; 4680 __le16 target_id; 4681 __le64 resp_addr; 4682 __le32 vnic_id; 4683 u8 unused_0[4]; 4684}; 4685 4686/* hwrm_vnic_free_output (size:128b/16B) */ 4687struct hwrm_vnic_free_output { 4688 __le16 error_code; 4689 __le16 req_type; 4690 __le16 seq_id; 4691 __le16 resp_len; 4692 u8 unused_0[7]; 4693 u8 valid; 4694}; 4695 4696/* hwrm_vnic_cfg_input (size:320b/40B) */ 4697struct hwrm_vnic_cfg_input { 4698 __le16 req_type; 4699 __le16 cmpl_ring; 4700 __le16 seq_id; 4701 __le16 target_id; 4702 __le64 resp_addr; 4703 __le32 flags; 4704 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 4705 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 4706 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 4707 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 4708 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 4709 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4710 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4711 __le32 enables; 4712 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4713 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4714 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4715 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4716 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4717 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 4718 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 4719 __le16 vnic_id; 4720 __le16 dflt_ring_grp; 4721 __le16 rss_rule; 4722 __le16 cos_rule; 4723 __le16 lb_rule; 4724 __le16 mru; 4725 __le16 default_rx_ring_id; 4726 __le16 default_cmpl_ring_id; 4727}; 4728 4729/* hwrm_vnic_cfg_output (size:128b/16B) */ 4730struct hwrm_vnic_cfg_output { 4731 __le16 error_code; 4732 __le16 req_type; 4733 __le16 seq_id; 4734 __le16 resp_len; 4735 u8 unused_0[7]; 4736 u8 valid; 4737}; 4738 4739/* hwrm_vnic_qcaps_input (size:192b/24B) */ 4740struct hwrm_vnic_qcaps_input { 4741 __le16 req_type; 4742 __le16 cmpl_ring; 4743 __le16 seq_id; 4744 __le16 target_id; 4745 __le64 resp_addr; 4746 __le32 enables; 4747 u8 unused_0[4]; 4748}; 4749 4750/* hwrm_vnic_qcaps_output (size:192b/24B) */ 4751struct hwrm_vnic_qcaps_output { 4752 __le16 error_code; 4753 __le16 req_type; 4754 __le16 seq_id; 4755 __le16 resp_len; 4756 __le16 mru; 4757 u8 unused_0[2]; 4758 __le32 flags; 4759 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 4760 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 4761 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 4762 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 4763 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4764 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4765 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4766 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 4767 __le16 max_aggs_supported; 4768 u8 unused_1[5]; 4769 u8 valid; 4770}; 4771 4772/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 4773struct hwrm_vnic_tpa_cfg_input { 4774 __le16 req_type; 4775 __le16 cmpl_ring; 4776 __le16 seq_id; 4777 __le16 target_id; 4778 __le64 resp_addr; 4779 __le32 flags; 4780 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 4781 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 4782 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 4783 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 4784 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 4785 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4786 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 4787 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 4788 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 4789 __le32 enables; 4790 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 4791 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 4792 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 4793 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 4794 __le16 vnic_id; 4795 __le16 max_agg_segs; 4796 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 4797 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 4798 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 4799 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 4800 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 4801 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 4802 __le16 max_aggs; 4803 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 4804 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 4805 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 4806 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 4807 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 4808 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 4809 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 4810 u8 unused_0[2]; 4811 __le32 max_agg_timer; 4812 __le32 min_agg_len; 4813}; 4814 4815/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 4816struct hwrm_vnic_tpa_cfg_output { 4817 __le16 error_code; 4818 __le16 req_type; 4819 __le16 seq_id; 4820 __le16 resp_len; 4821 u8 unused_0[7]; 4822 u8 valid; 4823}; 4824 4825/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 4826struct hwrm_vnic_tpa_qcfg_input { 4827 __le16 req_type; 4828 __le16 cmpl_ring; 4829 __le16 seq_id; 4830 __le16 target_id; 4831 __le64 resp_addr; 4832 __le16 vnic_id; 4833 u8 unused_0[6]; 4834}; 4835 4836/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 4837struct hwrm_vnic_tpa_qcfg_output { 4838 __le16 error_code; 4839 __le16 req_type; 4840 __le16 seq_id; 4841 __le16 resp_len; 4842 __le32 flags; 4843 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 4844 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 4845 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 4846 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 4847 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 4848 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4849 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 4850 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 4851 __le16 max_agg_segs; 4852 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 4853 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 4854 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 4855 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 4856 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 4857 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 4858 __le16 max_aggs; 4859 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 4860 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 4861 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 4862 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 4863 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 4864 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 4865 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 4866 __le32 max_agg_timer; 4867 __le32 min_agg_len; 4868 u8 unused_0[7]; 4869 u8 valid; 4870}; 4871 4872/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 4873struct hwrm_vnic_rss_cfg_input { 4874 __le16 req_type; 4875 __le16 cmpl_ring; 4876 __le16 seq_id; 4877 __le16 target_id; 4878 __le64 resp_addr; 4879 __le32 hash_type; 4880 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 4881 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 4882 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 4883 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 4884 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 4885 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 4886 __le16 vnic_id; 4887 u8 ring_table_pair_index; 4888 u8 hash_mode_flags; 4889 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 4890 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 4891 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 4892 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 4893 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 4894 __le64 ring_grp_tbl_addr; 4895 __le64 hash_key_tbl_addr; 4896 __le16 rss_ctx_idx; 4897 u8 unused_1[6]; 4898}; 4899 4900/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 4901struct hwrm_vnic_rss_cfg_output { 4902 __le16 error_code; 4903 __le16 req_type; 4904 __le16 seq_id; 4905 __le16 resp_len; 4906 u8 unused_0[7]; 4907 u8 valid; 4908}; 4909 4910/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 4911struct hwrm_vnic_plcmodes_cfg_input { 4912 __le16 req_type; 4913 __le16 cmpl_ring; 4914 __le16 seq_id; 4915 __le16 target_id; 4916 __le64 resp_addr; 4917 __le32 flags; 4918 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 4919 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 4920 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 4921 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 4922 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 4923 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 4924 __le32 enables; 4925 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 4926 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 4927 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 4928 __le32 vnic_id; 4929 __le16 jumbo_thresh; 4930 __le16 hds_offset; 4931 __le16 hds_threshold; 4932 u8 unused_0[6]; 4933}; 4934 4935/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 4936struct hwrm_vnic_plcmodes_cfg_output { 4937 __le16 error_code; 4938 __le16 req_type; 4939 __le16 seq_id; 4940 __le16 resp_len; 4941 u8 unused_0[7]; 4942 u8 valid; 4943}; 4944 4945/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 4946struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 4947 __le16 req_type; 4948 __le16 cmpl_ring; 4949 __le16 seq_id; 4950 __le16 target_id; 4951 __le64 resp_addr; 4952}; 4953 4954/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 4955struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 4956 __le16 error_code; 4957 __le16 req_type; 4958 __le16 seq_id; 4959 __le16 resp_len; 4960 __le16 rss_cos_lb_ctx_id; 4961 u8 unused_0[5]; 4962 u8 valid; 4963}; 4964 4965/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 4966struct hwrm_vnic_rss_cos_lb_ctx_free_input { 4967 __le16 req_type; 4968 __le16 cmpl_ring; 4969 __le16 seq_id; 4970 __le16 target_id; 4971 __le64 resp_addr; 4972 __le16 rss_cos_lb_ctx_id; 4973 u8 unused_0[6]; 4974}; 4975 4976/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 4977struct hwrm_vnic_rss_cos_lb_ctx_free_output { 4978 __le16 error_code; 4979 __le16 req_type; 4980 __le16 seq_id; 4981 __le16 resp_len; 4982 u8 unused_0[7]; 4983 u8 valid; 4984}; 4985 4986/* hwrm_ring_alloc_input (size:704b/88B) */ 4987struct hwrm_ring_alloc_input { 4988 __le16 req_type; 4989 __le16 cmpl_ring; 4990 __le16 seq_id; 4991 __le16 target_id; 4992 __le64 resp_addr; 4993 __le32 enables; 4994 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 4995 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 4996 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 4997 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 4998 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 4999 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5000 u8 ring_type;
5001 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5002 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5003 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5004 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5005 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5006 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5007 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5008 u8 unused_0; 5009 __le16 flags; 5010 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5011 __le64 page_tbl_addr; 5012 __le32 fbo; 5013 u8 page_size; 5014 u8 page_tbl_depth; 5015 u8 unused_1[2]; 5016 __le32 length; 5017 __le16 logical_id; 5018 __le16 cmpl_ring_id; 5019 __le16 queue_id; 5020 __le16 rx_buf_size; 5021 __le16 rx_ring_id; 5022 __le16 nq_ring_id; 5023 __le16 ring_arb_cfg; 5024 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5025 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5026 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5027 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5028 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5029 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5030 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5031 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5032 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5033 __le16 unused_3; 5034 __le32 reserved3; 5035 __le32 stat_ctx_id; 5036 __le32 reserved4; 5037 __le32 max_bw; 5038 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5039 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5040 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5041 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5042 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5043 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5044 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5045 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5046 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5047 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5048 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5049 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5050 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5051 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5052 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5053 u8 int_mode; 5054 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5055 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5056 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5057 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5058 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5059 u8 unused_4[3]; 5060 __le64 cq_handle; 5061}; 5062 5063/* hwrm_ring_alloc_output (size:128b/16B) */ 5064struct hwrm_ring_alloc_output { 5065 __le16 error_code; 5066 __le16 req_type; 5067 __le16 seq_id; 5068 __le16 resp_len; 5069 __le16 ring_id; 5070 __le16 logical_ring_id; 5071 u8 unused_0[3]; 5072 u8 valid; 5073}; 5074 5075/* hwrm_ring_free_input (size:192b/24B) */ 5076struct hwrm_ring_free_input { 5077 __le16 req_type; 5078 __le16 cmpl_ring; 5079 __le16 seq_id; 5080 __le16 target_id; 5081 __le64 resp_addr; 5082 u8 ring_type; 5083 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5084 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5085 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5086 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5087 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5088 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5089 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5090 u8 unused_0; 5091 __le16 ring_id; 5092 u8 unused_1[4]; 5093}; 5094 5095/* hwrm_ring_free_output (size:128b/16B) */ 5096struct hwrm_ring_free_output { 5097 __le16 error_code; 5098 __le16 req_type; 5099 __le16 seq_id; 5100 __le16 resp_len; 5101 u8 unused_0[7]; 5102 u8 valid; 5103}; 5104 5105/* hwrm_ring_reset_input (size:192b/24B) */ 5106struct hwrm_ring_reset_input { 5107 __le16 req_type; 5108 __le16 cmpl_ring; 5109 __le16 seq_id; 5110 __le16 target_id; 5111 __le64 resp_addr; 5112 u8 ring_type; 5113 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5114 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5115 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5116 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5117 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL 5118 u8 unused_0; 5119 __le16 ring_id; 5120 u8 unused_1[4]; 5121}; 5122 5123/* hwrm_ring_reset_output (size:128b/16B) */ 5124struct hwrm_ring_reset_output { 5125 __le16 error_code; 5126 __le16 req_type; 5127 __le16 seq_id; 5128 __le16 resp_len; 5129 u8 unused_0[4]; 5130 u8 consumer_idx[3]; 5131 u8 valid; 5132}; 5133 5134/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5135struct hwrm_ring_aggint_qcaps_input { 5136 __le16 req_type; 5137 __le16 cmpl_ring; 5138 __le16 seq_id; 5139 __le16 target_id; 5140 __le64 resp_addr; 5141}; 5142 5143/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5144struct hwrm_ring_aggint_qcaps_output { 5145 __le16 error_code; 5146 __le16 req_type; 5147 __le16 seq_id; 5148 __le16 resp_len; 5149 __le32 cmpl_params; 5150 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5151 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5152 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5153 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5154 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5155 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5156 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5157 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5158 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5159 __le32 nq_params; 5160 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5161 __le16 num_cmpl_dma_aggr_min; 5162 __le16 num_cmpl_dma_aggr_max; 5163 __le16 num_cmpl_dma_aggr_during_int_min; 5164 __le16 num_cmpl_dma_aggr_during_int_max; 5165 __le16 cmpl_aggr_dma_tmr_min; 5166 __le16 cmpl_aggr_dma_tmr_max; 5167 __le16 cmpl_aggr_dma_tmr_during_int_min; 5168 __le16 cmpl_aggr_dma_tmr_during_int_max; 5169 __le16 int_lat_tmr_min_min; 5170 __le16 int_lat_tmr_min_max; 5171 __le16 int_lat_tmr_max_min; 5172 __le16 int_lat_tmr_max_max; 5173 __le16 num_cmpl_aggr_int_min; 5174 __le16 num_cmpl_aggr_int_max; 5175 __le16 timer_units; 5176 u8 unused_0[1]; 5177 u8 valid; 5178}; 5179 5180/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5181struct hwrm_ring_cmpl_ring_qaggint_params_input { 5182 __le16 req_type; 5183 __le16 cmpl_ring; 5184 __le16 seq_id; 5185 __le16 target_id; 5186 __le64 resp_addr; 5187 __le16 ring_id; 5188 u8 unused_0[6]; 5189}; 5190 5191/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5192struct hwrm_ring_cmpl_ring_qaggint_params_output { 5193 __le16 error_code; 5194 __le16 req_type; 5195 __le16 seq_id; 5196 __le16 resp_len; 5197 __le16 flags; 5198 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5199 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5200 __le16 num_cmpl_dma_aggr; 5201 __le16 num_cmpl_dma_aggr_during_int; 5202 __le16 cmpl_aggr_dma_tmr; 5203 __le16 cmpl_aggr_dma_tmr_during_int; 5204 __le16 int_lat_tmr_min; 5205 __le16 int_lat_tmr_max; 5206 __le16 num_cmpl_aggr_int; 5207 u8 unused_0[7]; 5208 u8 valid; 5209}; 5210 5211/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5212struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5213 __le16 req_type; 5214 __le16 cmpl_ring; 5215 __le16 seq_id; 5216 __le16 target_id; 5217 __le64 resp_addr; 5218 __le16 ring_id; 5219 __le16 flags; 5220 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5221 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5222 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5223 __le16 num_cmpl_dma_aggr; 5224 __le16 num_cmpl_dma_aggr_during_int; 5225 __le16 cmpl_aggr_dma_tmr; 5226 __le16 cmpl_aggr_dma_tmr_during_int; 5227 __le16 int_lat_tmr_min; 5228 __le16 int_lat_tmr_max; 5229 __le16 num_cmpl_aggr_int; 5230 __le16 enables; 5231 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5232 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5233 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5234 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5235 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5236 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5237 u8 unused_0[4]; 5238}; 5239 5240/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5241struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5242 __le16 error_code; 5243 __le16 req_type; 5244 __le16 seq_id; 5245 __le16 resp_len; 5246 u8 unused_0[7]; 5247 u8 valid; 5248}; 5249 5250/* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5251struct hwrm_ring_grp_alloc_input { 5252 __le16 req_type; 5253 __le16 cmpl_ring; 5254 __le16 seq_id; 5255 __le16 target_id; 5256 __le64 resp_addr; 5257 __le16 cr; 5258 __le16 rr; 5259 __le16 ar; 5260 __le16 sc; 5261}; 5262 5263/* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5264struct hwrm_ring_grp_alloc_output { 5265 __le16 error_code; 5266 __le16 req_type; 5267 __le16 seq_id; 5268 __le16 resp_len; 5269 __le32 ring_group_id; 5270 u8 unused_0[3]; 5271 u8 valid; 5272}; 5273 5274/* hwrm_ring_grp_free_input (size:192b/24B) */ 5275struct hwrm_ring_grp_free_input { 5276 __le16 req_type; 5277 __le16 cmpl_ring; 5278 __le16 seq_id; 5279 __le16 target_id; 5280 __le64 resp_addr; 5281 __le32 ring_group_id; 5282 u8 unused_0[4]; 5283}; 5284 5285/* hwrm_ring_grp_free_output (size:128b/16B) */ 5286struct hwrm_ring_grp_free_output { 5287 __le16 error_code; 5288 __le16 req_type; 5289 __le16 seq_id; 5290 __le16 resp_len; 5291 u8 unused_0[7]; 5292 u8 valid; 5293}; 5294#define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5295#define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5296#define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5297#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5298 5299/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5300struct hwrm_cfa_l2_filter_alloc_input { 5301 __le16 req_type; 5302 __le16 cmpl_ring; 5303 __le16 seq_id; 5304 __le16 target_id; 5305 __le64 resp_addr; 5306 __le32 flags; 5307 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5308 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5309 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5310 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5311 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5312 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5313 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5314 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5315 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5316 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5317 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5318 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5319 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5320 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5321 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5322 __le32 enables; 5323 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5324 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5325 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5326 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5327 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5328 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5329 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5330 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5331 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5332 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5333 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5334 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5335 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5336 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5337 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5338 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5339 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5340 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 5341 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 5342 u8 l2_addr[6]; 5343 u8 num_vlans; 5344 u8 t_num_vlans; 5345 u8 l2_addr_mask[6]; 5346 __le16 l2_ovlan; 5347 __le16 l2_ovlan_mask; 5348 __le16 l2_ivlan; 5349 __le16 l2_ivlan_mask; 5350 u8 unused_1[2]; 5351 u8 t_l2_addr[6]; 5352 u8 unused_2[2]; 5353 u8 t_l2_addr_mask[6]; 5354 __le16 t_l2_ovlan; 5355 __le16 t_l2_ovlan_mask; 5356 __le16 t_l2_ivlan; 5357 __le16 t_l2_ivlan_mask; 5358 u8 src_type; 5359 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5360 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5361 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5362 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5363 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5364 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5365 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5366 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5367 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5368 u8 unused_3; 5369 __le32 src_id; 5370 u8 tunnel_type; 5371 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5372 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5373 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5374 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5375 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5376 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5377 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5378 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5379 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5380 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5381 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5382 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5383 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5384 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5385 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5386 u8 unused_4; 5387 __le16 dst_id; 5388 __le16 mirror_vnic_id; 5389 u8 pri_hint; 5390 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5391 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5392 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5393 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5394 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5395 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5396 u8 unused_5; 5397 __le32 unused_6; 5398 __le64 l2_filter_id_hint; 5399}; 5400 5401/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5402struct hwrm_cfa_l2_filter_alloc_output { 5403 __le16 error_code; 5404 __le16 req_type; 5405 __le16 seq_id; 5406 __le16 resp_len; 5407 __le64 l2_filter_id; 5408 __le32 flow_id; 5409 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5410 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5411 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5412 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5413 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5414 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5415 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5416 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5417 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5418 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5419 u8 unused_0[3]; 5420 u8 valid; 5421}; 5422 5423/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5424struct hwrm_cfa_l2_filter_free_input { 5425 __le16 req_type; 5426 __le16 cmpl_ring; 5427 __le16 seq_id; 5428 __le16 target_id; 5429 __le64 resp_addr; 5430 __le64 l2_filter_id; 5431}; 5432 5433/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5434struct hwrm_cfa_l2_filter_free_output { 5435 __le16 error_code; 5436 __le16 req_type; 5437 __le16 seq_id; 5438 __le16 resp_len; 5439 u8 unused_0[7]; 5440 u8 valid; 5441}; 5442 5443/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5444struct hwrm_cfa_l2_filter_cfg_input { 5445 __le16 req_type; 5446 __le16 cmpl_ring; 5447 __le16 seq_id; 5448 __le16 target_id; 5449 __le64 resp_addr; 5450 __le32 flags; 5451 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5452 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5453 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5454 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5455 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5456 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5457 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5458 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5459 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5460 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5461 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5462 __le32 enables; 5463 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5464 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5465 __le64 l2_filter_id; 5466 __le32 dst_id; 5467 __le32 new_mirror_vnic_id; 5468}; 5469 5470/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5471struct hwrm_cfa_l2_filter_cfg_output { 5472 __le16 error_code; 5473 __le16 req_type; 5474 __le16 seq_id; 5475 __le16 resp_len; 5476 u8 unused_0[7]; 5477 u8 valid; 5478}; 5479 5480/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5481struct hwrm_cfa_l2_set_rx_mask_input { 5482 __le16 req_type; 5483 __le16 cmpl_ring; 5484 __le16 seq_id; 5485 __le16 target_id; 5486 __le64 resp_addr; 5487 __le32 vnic_id; 5488 __le32 mask; 5489 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5490 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5491 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5492 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5493 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5494 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5495 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5496 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5497 __le64 mc_tbl_addr; 5498 __le32 num_mc_entries; 5499 u8 unused_0[4]; 5500 __le64 vlan_tag_tbl_addr; 5501 __le32 num_vlan_tags; 5502 u8 unused_1[4]; 5503}; 5504 5505/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5506struct hwrm_cfa_l2_set_rx_mask_output { 5507 __le16 error_code; 5508 __le16 req_type; 5509 __le16 seq_id; 5510 __le16 resp_len; 5511 u8 unused_0[7]; 5512 u8 valid; 5513}; 5514 5515/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5516struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5517 u8 code; 5518 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5519 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5520 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5521 u8 unused_0[7]; 5522}; 5523 5524/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5525struct hwrm_cfa_tunnel_filter_alloc_input { 5526 __le16 req_type; 5527 __le16 cmpl_ring; 5528 __le16 seq_id; 5529 __le16 target_id; 5530 __le64 resp_addr; 5531 __le32 flags; 5532 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5533 __le32 enables; 5534 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5535 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5536 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5537 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5538 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5539 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5540 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5541 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5542 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5543 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5544 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5545 __le64 l2_filter_id; 5546 u8 l2_addr[6]; 5547 __le16 l2_ivlan; 5548 __le32 l3_addr[4]; 5549 __le32 t_l3_addr[4]; 5550 u8 l3_addr_type; 5551 u8 t_l3_addr_type; 5552 u8 tunnel_type; 5553 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5554 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5555 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5556 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5557 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5558 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5559 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5560 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5561 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5562 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5563 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5564 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5565 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5566 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5567 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5568 u8 tunnel_flags; 5569 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5570 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5571 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5572 __le32 vni; 5573 __le32 dst_vnic_id; 5574 __le32 mirror_vnic_id; 5575}; 5576 5577/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5578struct hwrm_cfa_tunnel_filter_alloc_output { 5579 __le16 error_code; 5580 __le16 req_type; 5581 __le16 seq_id; 5582 __le16 resp_len; 5583 __le64 tunnel_filter_id; 5584 __le32 flow_id; 5585 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5586 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5587 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5588 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5589 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5590 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5591 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5592 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5593 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5594 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5595 u8 unused_0[3]; 5596 u8 valid; 5597}; 5598 5599/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5600struct hwrm_cfa_tunnel_filter_free_input { 5601 __le16 req_type; 5602 __le16 cmpl_ring; 5603 __le16 seq_id; 5604 __le16 target_id; 5605 __le64 resp_addr; 5606 __le64 tunnel_filter_id; 5607}; 5608 5609/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5610struct hwrm_cfa_tunnel_filter_free_output { 5611 __le16 error_code; 5612 __le16 req_type; 5613 __le16 seq_id; 5614 __le16 resp_len; 5615 u8 unused_0[7]; 5616 u8 valid; 5617}; 5618 5619/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5620struct hwrm_vxlan_ipv4_hdr { 5621 u8 ver_hlen; 5622 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5623 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5624 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5625 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 5626 u8 tos; 5627 __be16 ip_id; 5628 __be16 flags_frag_offset; 5629 u8 ttl; 5630 u8 protocol; 5631 __be32 src_ip_addr; 5632 __be32 dest_ip_addr; 5633}; 5634 5635/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 5636struct hwrm_vxlan_ipv6_hdr { 5637 __be32 ver_tc_flow_label; 5638 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 5639 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 5640 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 5641 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 5642 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 5643 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 5644 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 5645 __be16 payload_len; 5646 u8 next_hdr; 5647 u8 ttl; 5648 __be32 src_ip_addr[4]; 5649 __be32 dest_ip_addr[4]; 5650}; 5651 5652/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 5653struct hwrm_cfa_encap_data_vxlan { 5654 u8 src_mac_addr[6]; 5655 __le16 unused_0; 5656 u8 dst_mac_addr[6]; 5657 u8 num_vlan_tags; 5658 u8 unused_1; 5659 __be16 ovlan_tpid; 5660 __be16 ovlan_tci; 5661 __be16 ivlan_tpid; 5662 __be16 ivlan_tci; 5663 __le32 l3[10]; 5664 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 5665 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 5666 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 5667 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 5668 __be16 src_port; 5669 __be16 dst_port; 5670 __be32 vni; 5671 u8 hdr_rsvd0[3]; 5672 u8 hdr_rsvd1; 5673 u8 hdr_flags; 5674 u8 unused[3]; 5675}; 5676 5677/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 5678struct hwrm_cfa_encap_record_alloc_input { 5679 __le16 req_type; 5680 __le16 cmpl_ring; 5681 __le16 seq_id; 5682 __le16 target_id; 5683 __le64 resp_addr; 5684 __le32 flags; 5685 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5686 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 5687 u8 encap_type; 5688 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 5689 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 5690 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 5691 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 5692 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 5693 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 5694 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 5695 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 5696 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 5697 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 5698 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 5699 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 5700 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 5701 u8 unused_0[3]; 5702 __le32 encap_data[20]; 5703}; 5704 5705/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 5706struct hwrm_cfa_encap_record_alloc_output { 5707 __le16 error_code; 5708 __le16 req_type; 5709 __le16 seq_id; 5710 __le16 resp_len; 5711 __le32 encap_record_id; 5712 u8 unused_0[3]; 5713 u8 valid; 5714}; 5715 5716/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 5717struct hwrm_cfa_encap_record_free_input { 5718 __le16 req_type; 5719 __le16 cmpl_ring; 5720 __le16 seq_id; 5721 __le16 target_id; 5722 __le64 resp_addr; 5723 __le32 encap_record_id; 5724 u8 unused_0[4]; 5725}; 5726 5727/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 5728struct hwrm_cfa_encap_record_free_output { 5729 __le16 error_code; 5730 __le16 req_type; 5731 __le16 seq_id; 5732 __le16 resp_len; 5733 u8 unused_0[7]; 5734 u8 valid; 5735}; 5736 5737/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */ 5738struct hwrm_cfa_ntuple_filter_alloc_input { 5739 __le16 req_type; 5740 __le16 cmpl_ring; 5741 __le16 seq_id; 5742 __le16 target_id; 5743 __le64 resp_addr; 5744 __le32 flags; 5745 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5746 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 5747 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 5748 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 5749 __le32 enables; 5750 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5751 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 5752 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 5753 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 5754 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 5755 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 5756 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 5757 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 5758 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 5759 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 5760 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 5761 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 5762 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 5763 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 5764 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 5765 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 5766 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 5767 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 5768 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 5769 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 5770 __le64 l2_filter_id; 5771 u8 src_macaddr[6]; 5772 __be16 ethertype; 5773 u8 ip_addr_type; 5774 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5775 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5776 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5777 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5778 u8 ip_protocol; 5779 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5780 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5781 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5782 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5783 __le16 dst_id; 5784 __le16 mirror_vnic_id; 5785 u8 tunnel_type; 5786 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5787 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5788 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5789 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5790 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5791 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5792 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5793 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5794 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5795 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5796 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5797 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5798 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5799 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5800 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5801 u8 pri_hint; 5802 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5803 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 5804 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 5805 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 5806 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 5807 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 5808 __be32 src_ipaddr[4]; 5809 __be32 src_ipaddr_mask[4]; 5810 __be32 dst_ipaddr[4]; 5811 __be32 dst_ipaddr_mask[4]; 5812 __be16 src_port; 5813 __be16 src_port_mask; 5814 __be16 dst_port; 5815 __be16 dst_port_mask; 5816 __le64 ntuple_filter_id_hint; 5817 __le16 rfs_ring_tbl_idx; 5818 u8 unused_0[6]; 5819}; 5820 5821/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 5822struct hwrm_cfa_ntuple_filter_alloc_output { 5823 __le16 error_code; 5824 __le16 req_type; 5825 __le16 seq_id; 5826 __le16 resp_len; 5827 __le64 ntuple_filter_id; 5828 __le32 flow_id; 5829 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5830 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5831 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5832 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5833 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5834 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5835 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5836 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5837 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5838 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5839 u8 unused_0[3]; 5840 u8 valid; 5841}; 5842 5843/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 5844struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 5845 u8 code; 5846 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 5847 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 5848 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 5849 u8 unused_0[7]; 5850}; 5851 5852/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 5853struct hwrm_cfa_ntuple_filter_free_input { 5854 __le16 req_type; 5855 __le16 cmpl_ring; 5856 __le16 seq_id; 5857 __le16 target_id; 5858 __le64 resp_addr; 5859 __le64 ntuple_filter_id; 5860}; 5861 5862/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 5863struct hwrm_cfa_ntuple_filter_free_output { 5864 __le16 error_code; 5865 __le16 req_type; 5866 __le16 seq_id; 5867 __le16 resp_len; 5868 u8 unused_0[7]; 5869 u8 valid; 5870}; 5871 5872/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 5873struct hwrm_cfa_ntuple_filter_cfg_input { 5874 __le16 req_type; 5875 __le16 cmpl_ring; 5876 __le16 seq_id; 5877 __le16 target_id; 5878 __le64 resp_addr; 5879 __le32 enables; 5880 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 5881 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5882 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 5883 __le32 flags; 5884 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 5885 __le64 ntuple_filter_id; 5886 __le32 new_dst_id; 5887 __le32 new_mirror_vnic_id; 5888 __le16 new_meter_instance_id; 5889 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 5890 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 5891 u8 unused_1[6]; 5892}; 5893 5894/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 5895struct hwrm_cfa_ntuple_filter_cfg_output { 5896 __le16 error_code; 5897 __le16 req_type; 5898 __le16 seq_id; 5899 __le16 resp_len; 5900 u8 unused_0[7]; 5901 u8 valid; 5902}; 5903 5904/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 5905struct hwrm_cfa_decap_filter_alloc_input { 5906 __le16 req_type; 5907 __le16 cmpl_ring; 5908 __le16 seq_id; 5909 __le16 target_id; 5910 __le64 resp_addr; 5911 __le32 flags; 5912 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 5913 __le32 enables; 5914 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 5915 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 5916 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 5917 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 5918 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 5919 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 5920 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 5921 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 5922 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 5923 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 5924 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 5925 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 5926 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 5927 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 5928 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 5929 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5930 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5931 __be32 tunnel_id; 5932 u8 tunnel_type; 5933 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5934 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5935 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5936 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5937 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5938 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5939 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5940 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5941 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5942 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5943 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5944 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5945 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5946 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5947 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5948 u8 unused_0; 5949 __le16 unused_1; 5950 u8 src_macaddr[6]; 5951 u8 unused_2[2]; 5952 u8 dst_macaddr[6]; 5953 __be16 ovlan_vid; 5954 __be16 ivlan_vid; 5955 __be16 t_ovlan_vid; 5956 __be16 t_ivlan_vid; 5957 __be16 ethertype; 5958 u8 ip_addr_type; 5959 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5960 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5961 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5962 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5963 u8 ip_protocol; 5964 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5965 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5966 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5967 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5968 __le16 unused_3; 5969 __le32 unused_4; 5970 __be32 src_ipaddr[4]; 5971 __be32 dst_ipaddr[4]; 5972 __be16 src_port; 5973 __be16 dst_port; 5974 __le16 dst_id; 5975 __le16 l2_ctxt_ref_id; 5976}; 5977 5978/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 5979struct hwrm_cfa_decap_filter_alloc_output { 5980 __le16 error_code; 5981 __le16 req_type; 5982 __le16 seq_id; 5983 __le16 resp_len; 5984 __le32 decap_filter_id; 5985 u8 unused_0[3]; 5986 u8 valid; 5987}; 5988 5989/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 5990struct hwrm_cfa_decap_filter_free_input { 5991 __le16 req_type; 5992 __le16 cmpl_ring; 5993 __le16 seq_id; 5994 __le16 target_id; 5995 __le64 resp_addr; 5996 __le32 decap_filter_id; 5997 u8 unused_0[4]; 5998}; 5999 6000/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
6001struct hwrm_cfa_decap_filter_free_output { 6002 __le16 error_code; 6003 __le16 req_type; 6004 __le16 seq_id; 6005 __le16 resp_len; 6006 u8 unused_0[7]; 6007 u8 valid; 6008}; 6009 6010/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6011struct hwrm_cfa_flow_alloc_input { 6012 __le16 req_type; 6013 __le16 cmpl_ring; 6014 __le16 seq_id; 6015 __le16 target_id; 6016 __le64 resp_addr; 6017 __le16 flags; 6018 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6019 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6020 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6021 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6022 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6023 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6024 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6025 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6026 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6027 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6028 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6029 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6030 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6031 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6032 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6033 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6034 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6035 __le16 src_fid; 6036 __le32 tunnel_handle; 6037 __le16 action_flags; 6038 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6039 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6040 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6041 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6042 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6043 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6044 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6045 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6046 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6047 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6048 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6049 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6050 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6051 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6052 __le16 dst_fid; 6053 __be16 l2_rewrite_vlan_tpid; 6054 __be16 l2_rewrite_vlan_tci; 6055 __le16 act_meter_id; 6056 __le16 ref_flow_handle; 6057 __be16 ethertype; 6058 __be16 outer_vlan_tci; 6059 __be16 dmac[3]; 6060 __be16 inner_vlan_tci; 6061 __be16 smac[3]; 6062 u8 ip_dst_mask_len; 6063 u8 ip_src_mask_len; 6064 __be32 ip_dst[4]; 6065 __be32 ip_src[4]; 6066 __be16 l4_src_port; 6067 __be16 l4_src_port_mask; 6068 __be16 l4_dst_port; 6069 __be16 l4_dst_port_mask; 6070 __be32 nat_ip_address[4]; 6071 __be16 l2_rewrite_dmac[3]; 6072 __be16 nat_port; 6073 __be16 l2_rewrite_smac[3]; 6074 u8 ip_proto; 6075 u8 tunnel_type; 6076 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6077 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6078 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6079 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6080 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6081 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6082 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6083 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6084 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6085 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6086 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6087 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6088 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6089 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6090 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6091}; 6092 6093/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6094struct hwrm_cfa_flow_alloc_output { 6095 __le16 error_code; 6096 __le16 req_type; 6097 __le16 seq_id; 6098 __le16 resp_len; 6099 __le16 flow_handle; 6100 u8 unused_0[2]; 6101 __le32 flow_id; 6102 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6103 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6104 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6105 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6106 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6107 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6108 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6109 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6110 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6111 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6112 __le64 ext_flow_handle; 6113 __le32 flow_counter_id; 6114 u8 unused_1[3]; 6115 u8 valid; 6116}; 6117 6118/* hwrm_cfa_flow_free_input (size:256b/32B) */ 6119struct hwrm_cfa_flow_free_input { 6120 __le16 req_type; 6121 __le16 cmpl_ring; 6122 __le16 seq_id; 6123 __le16 target_id; 6124 __le64 resp_addr; 6125 __le16 flow_handle; 6126 __le16 unused_0; 6127 __le32 flow_counter_id; 6128 __le64 ext_flow_handle; 6129}; 6130 6131/* hwrm_cfa_flow_free_output (size:256b/32B) */ 6132struct hwrm_cfa_flow_free_output { 6133 __le16 error_code; 6134 __le16 req_type; 6135 __le16 seq_id; 6136 __le16 resp_len; 6137 __le64 packet; 6138 __le64 byte; 6139 u8 unused_0[7]; 6140 u8 valid; 6141}; 6142 6143/* hwrm_cfa_flow_info_input (size:256b/32B) */ 6144struct hwrm_cfa_flow_info_input { 6145 __le16 req_type; 6146 __le16 cmpl_ring; 6147 __le16 seq_id; 6148 __le16 target_id; 6149 __le64 resp_addr; 6150 __le16 flow_handle; 6151 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6152 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6153 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6154 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6155 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6156 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6157 u8 unused_0[6]; 6158 __le64 ext_flow_handle; 6159}; 6160 6161/* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6162struct hwrm_cfa_flow_info_output { 6163 __le16 error_code; 6164 __le16 req_type; 6165 __le16 seq_id; 6166 __le16 resp_len; 6167 u8 flags; 6168 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6169 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6170 u8 profile; 6171 __le16 src_fid; 6172 __le16 dst_fid; 6173 __le16 l2_ctxt_id; 6174 __le64 em_info; 6175 __le64 tcam_info; 6176 __le64 vfp_tcam_info; 6177 __le16 ar_id; 6178 __le16 flow_handle; 6179 __le32 tunnel_handle; 6180 __le16 flow_timer; 6181 u8 unused_0[6]; 6182 __le32 flow_key_data[130]; 6183 __le32 flow_action_info[30]; 6184 u8 unused_1[7]; 6185 u8 valid; 6186}; 6187 6188/* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6189struct hwrm_cfa_flow_stats_input { 6190 __le16 req_type; 6191 __le16 cmpl_ring; 6192 __le16 seq_id; 6193 __le16 target_id; 6194 __le64 resp_addr; 6195 __le16 num_flows; 6196 __le16 flow_handle_0; 6197 __le16 flow_handle_1; 6198 __le16 flow_handle_2; 6199 __le16 flow_handle_3; 6200 __le16 flow_handle_4; 6201 __le16 flow_handle_5; 6202 __le16 flow_handle_6; 6203 __le16 flow_handle_7; 6204 __le16 flow_handle_8; 6205 __le16 flow_handle_9; 6206 u8 unused_0[2]; 6207 __le32 flow_id_0; 6208 __le32 flow_id_1; 6209 __le32 flow_id_2; 6210 __le32 flow_id_3; 6211 __le32 flow_id_4; 6212 __le32 flow_id_5; 6213 __le32 flow_id_6; 6214 __le32 flow_id_7; 6215 __le32 flow_id_8; 6216 __le32 flow_id_9; 6217}; 6218 6219/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6220struct hwrm_cfa_flow_stats_output { 6221 __le16 error_code; 6222 __le16 req_type; 6223 __le16 seq_id; 6224 __le16 resp_len; 6225 __le64 packet_0; 6226 __le64 packet_1; 6227 __le64 packet_2; 6228 __le64 packet_3; 6229 __le64 packet_4; 6230 __le64 packet_5; 6231 __le64 packet_6; 6232 __le64 packet_7; 6233 __le64 packet_8; 6234 __le64 packet_9; 6235 __le64 byte_0; 6236 __le64 byte_1; 6237 __le64 byte_2; 6238 __le64 byte_3; 6239 __le64 byte_4; 6240 __le64 byte_5; 6241 __le64 byte_6; 6242 __le64 byte_7; 6243 __le64 byte_8; 6244 __le64 byte_9; 6245 u8 unused_0[7]; 6246 u8 valid; 6247}; 6248 6249/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6250struct hwrm_cfa_vfr_alloc_input { 6251 __le16 req_type; 6252 __le16 cmpl_ring; 6253 __le16 seq_id; 6254 __le16 target_id; 6255 __le64 resp_addr; 6256 __le16 vf_id; 6257 __le16 reserved; 6258 u8 unused_0[4]; 6259 char vfr_name[32]; 6260}; 6261 6262/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6263struct hwrm_cfa_vfr_alloc_output { 6264 __le16 error_code; 6265 __le16 req_type; 6266 __le16 seq_id; 6267 __le16 resp_len; 6268 __le16 rx_cfa_code; 6269 __le16 tx_cfa_action; 6270 u8 unused_0[3]; 6271 u8 valid; 6272}; 6273 6274/* hwrm_cfa_vfr_free_input (size:384b/48B) */ 6275struct hwrm_cfa_vfr_free_input { 6276 __le16 req_type; 6277 __le16 cmpl_ring; 6278 __le16 seq_id; 6279 __le16 target_id; 6280 __le64 resp_addr; 6281 char vfr_name[32]; 6282}; 6283 6284/* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6285struct hwrm_cfa_vfr_free_output { 6286 __le16 error_code; 6287 __le16 req_type; 6288 __le16 seq_id; 6289 __le16 resp_len; 6290 u8 unused_0[7]; 6291 u8 valid; 6292}; 6293 6294/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6295struct hwrm_cfa_eem_qcaps_input { 6296 __le16 req_type; 6297 __le16 cmpl_ring; 6298 __le16 seq_id; 6299 __le16 target_id; 6300 __le64 resp_addr; 6301 __le32 flags; 6302 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6303 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6304 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6305 __le32 unused_0; 6306}; 6307 6308/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */ 6309struct hwrm_cfa_eem_qcaps_output { 6310 __le16 error_code; 6311 __le16 req_type; 6312 __le16 seq_id; 6313 __le16 resp_len; 6314 __le32 flags; 6315 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6316 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6317 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 6318 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 6319 __le32 unused_0; 6320 __le32 supported; 6321 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6322 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6323 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6324 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6325 __le32 max_entries_supported; 6326 __le16 key_entry_size; 6327 __le16 record_entry_size; 6328 __le16 efc_entry_size; 6329 u8 unused_1; 6330 u8 valid; 6331}; 6332 6333/* hwrm_cfa_eem_cfg_input (size:320b/40B) */ 6334struct hwrm_cfa_eem_cfg_input { 6335 __le16 req_type; 6336 __le16 cmpl_ring; 6337 __le16 seq_id; 6338 __le16 target_id; 6339 __le64 resp_addr; 6340 __le32 flags; 6341 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6342 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6343 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6344 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 6345 __le16 group_id; 6346 __le16 unused_0; 6347 __le32 num_entries; 6348 __le32 unused_1; 6349 __le16 key0_ctx_id; 6350 __le16 key1_ctx_id; 6351 __le16 record_ctx_id; 6352 __le16 efc_ctx_id; 6353}; 6354 6355/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6356struct hwrm_cfa_eem_cfg_output { 6357 __le16 error_code; 6358 __le16 req_type; 6359 __le16 seq_id; 6360 __le16 resp_len; 6361 u8 unused_0[7]; 6362 u8 valid; 6363}; 6364 6365/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6366struct hwrm_cfa_eem_qcfg_input { 6367 __le16 req_type; 6368 __le16 cmpl_ring; 6369 __le16 seq_id; 6370 __le16 target_id; 6371 __le64 resp_addr; 6372 __le32 flags; 6373 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6374 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6375 __le32 unused_0; 6376}; 6377 6378/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */ 6379struct hwrm_cfa_eem_qcfg_output { 6380 __le16 error_code; 6381 __le16 req_type; 6382 __le16 seq_id; 6383 __le16 resp_len; 6384 __le32 flags; 6385 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6386 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6387 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6388 __le32 num_entries; 6389 u8 unused_0[7]; 6390 u8 valid; 6391}; 6392 6393/* hwrm_cfa_eem_op_input (size:192b/24B) */ 6394struct hwrm_cfa_eem_op_input { 6395 __le16 req_type; 6396 __le16 cmpl_ring; 6397 __le16 seq_id; 6398 __le16 target_id; 6399 __le64 resp_addr; 6400 __le32 flags; 6401 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6402 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6403 __le16 unused_0; 6404 __le16 op; 6405 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6406 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6407 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6408 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6409 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6410}; 6411 6412/* hwrm_cfa_eem_op_output (size:128b/16B) */ 6413struct hwrm_cfa_eem_op_output { 6414 __le16 error_code; 6415 __le16 req_type; 6416 __le16 seq_id; 6417 __le16 resp_len; 6418 u8 unused_0[7]; 6419 u8 valid; 6420}; 6421 6422/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 6423struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 6424 __le16 req_type; 6425 __le16 cmpl_ring; 6426 __le16 seq_id; 6427 __le16 target_id; 6428 __le64 resp_addr; 6429 __le32 unused_0[4]; 6430}; 6431 6432/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 6433struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 6434 __le16 error_code; 6435 __le16 req_type; 6436 __le16 seq_id; 6437 __le16 resp_len; 6438 __le32 flags; 6439 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6440 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6441 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6442 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6443 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6444 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6445 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6446 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6447 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 6448 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 6449 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 6450 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 6451 u8 unused_0[3]; 6452 u8 valid; 6453}; 6454 6455/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6456struct hwrm_tunnel_dst_port_query_input { 6457 __le16 req_type; 6458 __le16 cmpl_ring; 6459 __le16 seq_id; 6460 __le16 target_id; 6461 __le64 resp_addr; 6462 u8 tunnel_type; 6463 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6464 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6465 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6466 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6467 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6468 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6469 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6470 u8 unused_0[7]; 6471}; 6472 6473/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 6474struct hwrm_tunnel_dst_port_query_output { 6475 __le16 error_code; 6476 __le16 req_type; 6477 __le16 seq_id; 6478 __le16 resp_len; 6479 __le16 tunnel_dst_port_id; 6480 __be16 tunnel_dst_port_val; 6481 u8 unused_0[3]; 6482 u8 valid; 6483}; 6484 6485/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 6486struct hwrm_tunnel_dst_port_alloc_input { 6487 __le16 req_type; 6488 __le16 cmpl_ring; 6489 __le16 seq_id; 6490 __le16 target_id; 6491 __le64 resp_addr; 6492 u8 tunnel_type; 6493 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6494 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6495 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6496 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6497 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6498 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6499 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6500 u8 unused_0; 6501 __be16 tunnel_dst_port_val; 6502 u8 unused_1[4]; 6503}; 6504 6505/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 6506struct hwrm_tunnel_dst_port_alloc_output { 6507 __le16 error_code; 6508 __le16 req_type; 6509 __le16 seq_id; 6510 __le16 resp_len; 6511 __le16 tunnel_dst_port_id; 6512 u8 unused_0[5]; 6513 u8 valid; 6514}; 6515 6516/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 6517struct hwrm_tunnel_dst_port_free_input { 6518 __le16 req_type; 6519 __le16 cmpl_ring; 6520 __le16 seq_id; 6521 __le16 target_id; 6522 __le64 resp_addr; 6523 u8 tunnel_type; 6524 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6525 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6526 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6527 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6528 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6529 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6530 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6531 u8 unused_0; 6532 __le16 tunnel_dst_port_id; 6533 u8 unused_1[4]; 6534}; 6535 6536/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 6537struct hwrm_tunnel_dst_port_free_output { 6538 __le16 error_code; 6539 __le16 req_type; 6540 __le16 seq_id; 6541 __le16 resp_len; 6542 u8 unused_1[7]; 6543 u8 valid; 6544}; 6545 6546/* ctx_hw_stats (size:1280b/160B) */ 6547struct ctx_hw_stats { 6548 __le64 rx_ucast_pkts; 6549 __le64 rx_mcast_pkts; 6550 __le64 rx_bcast_pkts; 6551 __le64 rx_discard_pkts; 6552 __le64 rx_drop_pkts; 6553 __le64 rx_ucast_bytes; 6554 __le64 rx_mcast_bytes; 6555 __le64 rx_bcast_bytes; 6556 __le64 tx_ucast_pkts; 6557 __le64 tx_mcast_pkts; 6558 __le64 tx_bcast_pkts; 6559 __le64 tx_discard_pkts; 6560 __le64 tx_drop_pkts; 6561 __le64 tx_ucast_bytes; 6562 __le64 tx_mcast_bytes; 6563 __le64 tx_bcast_bytes; 6564 __le64 tpa_pkts; 6565 __le64 tpa_bytes; 6566 __le64 tpa_events; 6567 __le64 tpa_aborts; 6568}; 6569 6570/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 6571struct hwrm_stat_ctx_alloc_input { 6572 __le16 req_type; 6573 __le16 cmpl_ring; 6574 __le16 seq_id; 6575 __le16 target_id; 6576 __le64 resp_addr; 6577 __le64 stats_dma_addr; 6578 __le32 update_period_ms; 6579 u8 stat_ctx_flags; 6580 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 6581 u8 unused_0[3]; 6582}; 6583 6584/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 6585struct hwrm_stat_ctx_alloc_output { 6586 __le16 error_code; 6587 __le16 req_type; 6588 __le16 seq_id; 6589 __le16 resp_len; 6590 __le32 stat_ctx_id; 6591 u8 unused_0[3]; 6592 u8 valid; 6593}; 6594 6595/* hwrm_stat_ctx_free_input (size:192b/24B) */ 6596struct hwrm_stat_ctx_free_input { 6597 __le16 req_type; 6598 __le16 cmpl_ring; 6599 __le16 seq_id; 6600 __le16 target_id; 6601 __le64 resp_addr; 6602 __le32 stat_ctx_id; 6603 u8 unused_0[4]; 6604}; 6605 6606/* hwrm_stat_ctx_free_output (size:128b/16B) */ 6607struct hwrm_stat_ctx_free_output { 6608 __le16 error_code; 6609 __le16 req_type; 6610 __le16 seq_id; 6611 __le16 resp_len; 6612 __le32 stat_ctx_id; 6613 u8 unused_0[3]; 6614 u8 valid; 6615}; 6616 6617/* hwrm_stat_ctx_query_input (size:192b/24B) */ 6618struct hwrm_stat_ctx_query_input { 6619 __le16 req_type; 6620 __le16 cmpl_ring; 6621 __le16 seq_id; 6622 __le16 target_id; 6623 __le64 resp_addr; 6624 __le32 stat_ctx_id; 6625 u8 unused_0[4]; 6626}; 6627 6628/* hwrm_stat_ctx_query_output (size:1408b/176B) */ 6629struct hwrm_stat_ctx_query_output { 6630 __le16 error_code; 6631 __le16 req_type; 6632 __le16 seq_id; 6633 __le16 resp_len; 6634 __le64 tx_ucast_pkts; 6635 __le64 tx_mcast_pkts; 6636 __le64 tx_bcast_pkts; 6637 __le64 tx_err_pkts; 6638 __le64 tx_drop_pkts; 6639 __le64 tx_ucast_bytes; 6640 __le64 tx_mcast_bytes; 6641 __le64 tx_bcast_bytes; 6642 __le64 rx_ucast_pkts; 6643 __le64 rx_mcast_pkts; 6644 __le64 rx_bcast_pkts; 6645 __le64 rx_err_pkts; 6646 __le64 rx_drop_pkts; 6647 __le64 rx_ucast_bytes; 6648 __le64 rx_mcast_bytes; 6649 __le64 rx_bcast_bytes; 6650 __le64 rx_agg_pkts; 6651 __le64 rx_agg_bytes; 6652 __le64 rx_agg_events; 6653 __le64 rx_agg_aborts; 6654 u8 unused_0[7]; 6655 u8 valid; 6656}; 6657 6658/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 6659struct hwrm_stat_ctx_clr_stats_input { 6660 __le16 req_type; 6661 __le16 cmpl_ring; 6662 __le16 seq_id; 6663 __le16 target_id; 6664 __le64 resp_addr; 6665 __le32 stat_ctx_id; 6666 u8 unused_0[4]; 6667}; 6668 6669/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 6670struct hwrm_stat_ctx_clr_stats_output { 6671 __le16 error_code; 6672 __le16 req_type; 6673 __le16 seq_id; 6674 __le16 resp_len; 6675 u8 unused_0[7]; 6676 u8 valid; 6677}; 6678 6679/* hwrm_pcie_qstats_input (size:256b/32B) */ 6680struct hwrm_pcie_qstats_input { 6681 __le16 req_type; 6682 __le16 cmpl_ring; 6683 __le16 seq_id; 6684 __le16 target_id; 6685 __le64 resp_addr; 6686 __le16 pcie_stat_size; 6687 u8 unused_0[6]; 6688 __le64 pcie_stat_host_addr; 6689}; 6690 6691/* hwrm_pcie_qstats_output (size:128b/16B) */ 6692struct hwrm_pcie_qstats_output { 6693 __le16 error_code; 6694 __le16 req_type; 6695 __le16 seq_id; 6696 __le16 resp_len; 6697 __le16 pcie_stat_size; 6698 u8 unused_0[5]; 6699 u8 valid; 6700}; 6701 6702/* pcie_ctx_hw_stats (size:768b/96B) */ 6703struct pcie_ctx_hw_stats { 6704 __le64 pcie_pl_signal_integrity; 6705 __le64 pcie_dl_signal_integrity; 6706 __le64 pcie_tl_signal_integrity; 6707 __le64 pcie_link_integrity; 6708 __le64 pcie_tx_traffic_rate; 6709 __le64 pcie_rx_traffic_rate; 6710 __le64 pcie_tx_dllp_statistics; 6711 __le64 pcie_rx_dllp_statistics; 6712 __le64 pcie_equalization_time; 6713 __le32 pcie_ltssm_histogram[4]; 6714 __le64 pcie_recovery_histogram; 6715}; 6716 6717/* hwrm_fw_reset_input (size:192b/24B) */ 6718struct hwrm_fw_reset_input { 6719 __le16 req_type; 6720 __le16 cmpl_ring; 6721 __le16 seq_id; 6722 __le16 target_id; 6723 __le64 resp_addr; 6724 u8 embedded_proc_type; 6725 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6726 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6727 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6728 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6729 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6730 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6731 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6732 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 6733 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 6734 u8 selfrst_status; 6735 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 6736 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 6737 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6738 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6739 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 6740 u8 host_idx; 6741 u8 flags; 6742 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 6743 u8 unused_0[4]; 6744}; 6745 6746/* hwrm_fw_reset_output (size:128b/16B) */ 6747struct hwrm_fw_reset_output { 6748 __le16 error_code; 6749 __le16 req_type; 6750 __le16 seq_id; 6751 __le16 resp_len; 6752 u8 selfrst_status; 6753 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6754 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6755 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6756 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6757 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 6758 u8 unused_0[6]; 6759 u8 valid; 6760}; 6761 6762/* hwrm_fw_qstatus_input (size:192b/24B) */ 6763struct hwrm_fw_qstatus_input { 6764 __le16 req_type; 6765 __le16 cmpl_ring; 6766 __le16 seq_id; 6767 __le16 target_id; 6768 __le64 resp_addr; 6769 u8 embedded_proc_type; 6770 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6771 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6772 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6773 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6774 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6775 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6776 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6777 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 6778 u8 unused_0[7]; 6779}; 6780 6781/* hwrm_fw_qstatus_output (size:128b/16B) */ 6782struct hwrm_fw_qstatus_output { 6783 __le16 error_code; 6784 __le16 req_type; 6785 __le16 seq_id; 6786 __le16 resp_len; 6787 u8 selfrst_status; 6788 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6789 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6790 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6791 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 6792 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 6793 u8 unused_0[6]; 6794 u8 valid; 6795}; 6796 6797/* hwrm_fw_set_time_input (size:256b/32B) */ 6798struct hwrm_fw_set_time_input { 6799 __le16 req_type; 6800 __le16 cmpl_ring; 6801 __le16 seq_id; 6802 __le16 target_id; 6803 __le64 resp_addr; 6804 __le16 year; 6805 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 6806 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 6807 u8 month; 6808 u8 day; 6809 u8 hour; 6810 u8 minute; 6811 u8 second; 6812 u8 unused_0; 6813 __le16 millisecond; 6814 __le16 zone; 6815 #define FW_SET_TIME_REQ_ZONE_UTC 0 6816 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 6817 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 6818 u8 unused_1[4]; 6819}; 6820 6821/* hwrm_fw_set_time_output (size:128b/16B) */ 6822struct hwrm_fw_set_time_output { 6823 __le16 error_code; 6824 __le16 req_type; 6825 __le16 seq_id; 6826 __le16 resp_len; 6827 u8 unused_0[7]; 6828 u8 valid; 6829}; 6830 6831/* hwrm_struct_hdr (size:128b/16B) */ 6832struct hwrm_struct_hdr { 6833 __le16 struct_id; 6834 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6835 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6836 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6837 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6838 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6839 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6840 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6841 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 6842 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6843 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6844 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6845 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 6846 __le16 len; 6847 u8 version; 6848 u8 count; 6849 __le16 subtype; 6850 __le16 next_offset; 6851 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6852 u8 unused_0[6]; 6853}; 6854 6855/* hwrm_struct_data_dcbx_app (size:64b/8B) */ 6856struct hwrm_struct_data_dcbx_app { 6857 __be16 protocol_id; 6858 u8 protocol_selector; 6859 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6860 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6861 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6862 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6863 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 6864 u8 priority; 6865 u8 valid; 6866 u8 unused_0[3]; 6867}; 6868 6869/* hwrm_fw_set_structured_data_input (size:256b/32B) */ 6870struct hwrm_fw_set_structured_data_input { 6871 __le16 req_type; 6872 __le16 cmpl_ring; 6873 __le16 seq_id; 6874 __le16 target_id; 6875 __le64 resp_addr; 6876 __le64 src_data_addr; 6877 __le16 data_len; 6878 u8 hdr_cnt; 6879 u8 unused_0[5]; 6880}; 6881 6882/* hwrm_fw_set_structured_data_output (size:128b/16B) */ 6883struct hwrm_fw_set_structured_data_output { 6884 __le16 error_code; 6885 __le16 req_type; 6886 __le16 seq_id; 6887 __le16 resp_len; 6888 u8 unused_0[7]; 6889 u8 valid; 6890}; 6891 6892/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 6893struct hwrm_fw_set_structured_data_cmd_err { 6894 u8 code; 6895 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6896 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 6897 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 6898 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6899 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6900 u8 unused_0[7]; 6901}; 6902 6903/* hwrm_fw_get_structured_data_input (size:256b/32B) */ 6904struct hwrm_fw_get_structured_data_input { 6905 __le16 req_type; 6906 __le16 cmpl_ring; 6907 __le16 seq_id; 6908 __le16 target_id; 6909 __le64 resp_addr; 6910 __le64 dest_data_addr; 6911 __le16 data_len; 6912 __le16 structure_id; 6913 __le16 subtype; 6914 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 6915 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 6916 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 6917 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 6918 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 6919 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 6920 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 6921 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 6922 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 6923 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 6924 u8 count; 6925 u8 unused_0; 6926}; 6927 6928/* hwrm_fw_get_structured_data_output (size:128b/16B) */ 6929struct hwrm_fw_get_structured_data_output { 6930 __le16 error_code; 6931 __le16 req_type; 6932 __le16 seq_id; 6933 __le16 resp_len; 6934 u8 hdr_cnt; 6935 u8 unused_0[6]; 6936 u8 valid; 6937}; 6938 6939/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 6940struct hwrm_fw_get_structured_data_cmd_err { 6941 u8 code; 6942 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6943 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6944 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6945 u8 unused_0[7]; 6946}; 6947 6948/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 6949struct hwrm_exec_fwd_resp_input { 6950 __le16 req_type; 6951 __le16 cmpl_ring; 6952 __le16 seq_id; 6953 __le16 target_id; 6954 __le64 resp_addr; 6955 __le32 encap_request[26]; 6956 __le16 encap_resp_target_id; 6957 u8 unused_0[6]; 6958}; 6959 6960/* hwrm_exec_fwd_resp_output (size:128b/16B) */ 6961struct hwrm_exec_fwd_resp_output { 6962 __le16 error_code; 6963 __le16 req_type; 6964 __le16 seq_id; 6965 __le16 resp_len; 6966 u8 unused_0[7]; 6967 u8 valid; 6968}; 6969 6970/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 6971struct hwrm_reject_fwd_resp_input { 6972 __le16 req_type; 6973 __le16 cmpl_ring; 6974 __le16 seq_id; 6975 __le16 target_id; 6976 __le64 resp_addr; 6977 __le32 encap_request[26]; 6978 __le16 encap_resp_target_id; 6979 u8 unused_0[6]; 6980}; 6981 6982/* hwrm_reject_fwd_resp_output (size:128b/16B) */ 6983struct hwrm_reject_fwd_resp_output { 6984 __le16 error_code; 6985 __le16 req_type; 6986 __le16 seq_id; 6987 __le16 resp_len; 6988 u8 unused_0[7]; 6989 u8 valid; 6990}; 6991 6992/* hwrm_fwd_resp_input (size:1024b/128B) */ 6993struct hwrm_fwd_resp_input { 6994 __le16 req_type; 6995 __le16 cmpl_ring; 6996 __le16 seq_id; 6997 __le16 target_id; 6998 __le64 resp_addr; 6999 __le16 encap_resp_target_id; 7000 __le16 encap_resp_cmpl_ring;
7001 __le16 encap_resp_len; 7002 u8 unused_0; 7003 u8 unused_1; 7004 __le64 encap_resp_addr; 7005 __le32 encap_resp[24]; 7006}; 7007 7008/* hwrm_fwd_resp_output (size:128b/16B) */ 7009struct hwrm_fwd_resp_output { 7010 __le16 error_code; 7011 __le16 req_type; 7012 __le16 seq_id; 7013 __le16 resp_len; 7014 u8 unused_0[7]; 7015 u8 valid; 7016}; 7017 7018/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7019struct hwrm_fwd_async_event_cmpl_input { 7020 __le16 req_type; 7021 __le16 cmpl_ring; 7022 __le16 seq_id; 7023 __le16 target_id; 7024 __le64 resp_addr; 7025 __le16 encap_async_event_target_id; 7026 u8 unused_0[6]; 7027 __le32 encap_async_event_cmpl[4]; 7028}; 7029 7030/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7031struct hwrm_fwd_async_event_cmpl_output { 7032 __le16 error_code; 7033 __le16 req_type; 7034 __le16 seq_id; 7035 __le16 resp_len; 7036 u8 unused_0[7]; 7037 u8 valid; 7038}; 7039 7040/* hwrm_temp_monitor_query_input (size:128b/16B) */ 7041struct hwrm_temp_monitor_query_input { 7042 __le16 req_type; 7043 __le16 cmpl_ring; 7044 __le16 seq_id; 7045 __le16 target_id; 7046 __le64 resp_addr; 7047}; 7048 7049/* hwrm_temp_monitor_query_output (size:128b/16B) */ 7050struct hwrm_temp_monitor_query_output { 7051 __le16 error_code; 7052 __le16 req_type; 7053 __le16 seq_id; 7054 __le16 resp_len; 7055 u8 temp; 7056 u8 unused_0[6]; 7057 u8 valid; 7058}; 7059 7060/* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7061struct hwrm_wol_filter_alloc_input { 7062 __le16 req_type; 7063 __le16 cmpl_ring; 7064 __le16 seq_id; 7065 __le16 target_id; 7066 __le64 resp_addr; 7067 __le32 flags; 7068 __le32 enables; 7069 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7070 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7071 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7072 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7073 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7074 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7075 __le16 port_id; 7076 u8 wol_type; 7077 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7078 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7079 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7080 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7081 u8 unused_0[5]; 7082 u8 mac_address[6]; 7083 __le16 pattern_offset; 7084 __le16 pattern_buf_size; 7085 __le16 pattern_mask_size; 7086 u8 unused_1[4]; 7087 __le64 pattern_buf_addr; 7088 __le64 pattern_mask_addr; 7089}; 7090 7091/* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7092struct hwrm_wol_filter_alloc_output { 7093 __le16 error_code; 7094 __le16 req_type; 7095 __le16 seq_id; 7096 __le16 resp_len; 7097 u8 wol_filter_id; 7098 u8 unused_0[6]; 7099 u8 valid; 7100}; 7101 7102/* hwrm_wol_filter_free_input (size:256b/32B) */ 7103struct hwrm_wol_filter_free_input { 7104 __le16 req_type; 7105 __le16 cmpl_ring; 7106 __le16 seq_id; 7107 __le16 target_id; 7108 __le64 resp_addr; 7109 __le32 flags; 7110 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7111 __le32 enables; 7112 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7113 __le16 port_id; 7114 u8 wol_filter_id; 7115 u8 unused_0[5]; 7116}; 7117 7118/* hwrm_wol_filter_free_output (size:128b/16B) */ 7119struct hwrm_wol_filter_free_output { 7120 __le16 error_code; 7121 __le16 req_type; 7122 __le16 seq_id; 7123 __le16 resp_len; 7124 u8 unused_0[7]; 7125 u8 valid; 7126}; 7127 7128/* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7129struct hwrm_wol_filter_qcfg_input { 7130 __le16 req_type; 7131 __le16 cmpl_ring; 7132 __le16 seq_id; 7133 __le16 target_id; 7134 __le64 resp_addr; 7135 __le16 port_id; 7136 __le16 handle; 7137 u8 unused_0[4]; 7138 __le64 pattern_buf_addr; 7139 __le16 pattern_buf_size; 7140 u8 unused_1[6]; 7141 __le64 pattern_mask_addr; 7142 __le16 pattern_mask_size; 7143 u8 unused_2[6]; 7144}; 7145 7146/* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7147struct hwrm_wol_filter_qcfg_output { 7148 __le16 error_code; 7149 __le16 req_type; 7150 __le16 seq_id; 7151 __le16 resp_len; 7152 __le16 next_handle; 7153 u8 wol_filter_id; 7154 u8 wol_type; 7155 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7156 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7157 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7158 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7159 __le32 unused_0; 7160 u8 mac_address[6]; 7161 __le16 pattern_offset; 7162 __le16 pattern_size; 7163 __le16 pattern_mask_size; 7164 u8 unused_1[3]; 7165 u8 valid; 7166}; 7167 7168/* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7169struct hwrm_wol_reason_qcfg_input { 7170 __le16 req_type; 7171 __le16 cmpl_ring; 7172 __le16 seq_id; 7173 __le16 target_id; 7174 __le64 resp_addr; 7175 __le16 port_id; 7176 u8 unused_0[6]; 7177 __le64 wol_pkt_buf_addr; 7178 __le16 wol_pkt_buf_size; 7179 u8 unused_1[6]; 7180}; 7181 7182/* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7183struct hwrm_wol_reason_qcfg_output { 7184 __le16 error_code; 7185 __le16 req_type; 7186 __le16 seq_id; 7187 __le16 resp_len; 7188 u8 wol_filter_id; 7189 u8 wol_reason; 7190 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7191 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7192 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7193 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7194 u8 wol_pkt_len; 7195 u8 unused_0[4]; 7196 u8 valid; 7197}; 7198 7199/* coredump_segment_record (size:128b/16B) */ 7200struct coredump_segment_record { 7201 __le16 component_id; 7202 __le16 segment_id; 7203 __le16 max_instances; 7204 u8 version_hi; 7205 u8 version_low; 7206 u8 seg_flags; 7207 u8 unused_0[7]; 7208}; 7209 7210/* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7211struct hwrm_dbg_coredump_list_input { 7212 __le16 req_type; 7213 __le16 cmpl_ring; 7214 __le16 seq_id; 7215 __le16 target_id; 7216 __le64 resp_addr; 7217 __le64 host_dest_addr; 7218 __le32 host_buf_len; 7219 __le16 seq_no; 7220 u8 flags; 7221 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 7222 u8 unused_0[1]; 7223}; 7224 7225/* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7226struct hwrm_dbg_coredump_list_output { 7227 __le16 error_code; 7228 __le16 req_type; 7229 __le16 seq_id; 7230 __le16 resp_len; 7231 u8 flags; 7232 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7233 u8 unused_0; 7234 __le16 total_segments; 7235 __le16 data_len; 7236 u8 unused_1; 7237 u8 valid; 7238}; 7239 7240/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7241struct hwrm_dbg_coredump_initiate_input { 7242 __le16 req_type; 7243 __le16 cmpl_ring; 7244 __le16 seq_id; 7245 __le16 target_id; 7246 __le64 resp_addr; 7247 __le16 component_id; 7248 __le16 segment_id; 7249 __le16 instance; 7250 __le16 unused_0; 7251 u8 seg_flags; 7252 u8 unused_1[7]; 7253}; 7254 7255/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7256struct hwrm_dbg_coredump_initiate_output { 7257 __le16 error_code; 7258 __le16 req_type; 7259 __le16 seq_id; 7260 __le16 resp_len; 7261 u8 unused_0[7]; 7262 u8 valid; 7263}; 7264 7265/* coredump_data_hdr (size:128b/16B) */ 7266struct coredump_data_hdr { 7267 __le32 address; 7268 __le32 flags_length; 7269 __le32 instance; 7270 __le32 next_offset; 7271}; 7272 7273/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 7274struct hwrm_dbg_coredump_retrieve_input { 7275 __le16 req_type; 7276 __le16 cmpl_ring; 7277 __le16 seq_id; 7278 __le16 target_id; 7279 __le64 resp_addr; 7280 __le64 host_dest_addr; 7281 __le32 host_buf_len; 7282 __le32 unused_0; 7283 __le16 component_id; 7284 __le16 segment_id; 7285 __le16 instance; 7286 __le16 unused_1; 7287 u8 seg_flags; 7288 u8 unused_2; 7289 __le16 unused_3; 7290 __le32 unused_4; 7291 __le32 seq_no; 7292 __le32 unused_5; 7293}; 7294 7295/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 7296struct hwrm_dbg_coredump_retrieve_output { 7297 __le16 error_code; 7298 __le16 req_type; 7299 __le16 seq_id; 7300 __le16 resp_len; 7301 u8 flags; 7302 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 7303 u8 unused_0; 7304 __le16 data_len; 7305 u8 unused_1[3]; 7306 u8 valid; 7307}; 7308 7309/* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 7310struct hwrm_dbg_ring_info_get_input { 7311 __le16 req_type; 7312 __le16 cmpl_ring; 7313 __le16 seq_id; 7314 __le16 target_id; 7315 __le64 resp_addr; 7316 u8 ring_type; 7317 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 7318 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 7319 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 7320 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX 7321 u8 unused_0[3]; 7322 __le32 fw_ring_id; 7323}; 7324 7325/* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 7326struct hwrm_dbg_ring_info_get_output { 7327 __le16 error_code; 7328 __le16 req_type; 7329 __le16 seq_id; 7330 __le16 resp_len; 7331 __le32 producer_index; 7332 __le32 consumer_index; 7333 u8 unused_0[7]; 7334 u8 valid; 7335}; 7336 7337/* hwrm_nvm_read_input (size:320b/40B) */ 7338struct hwrm_nvm_read_input { 7339 __le16 req_type; 7340 __le16 cmpl_ring; 7341 __le16 seq_id; 7342 __le16 target_id; 7343 __le64 resp_addr; 7344 __le64 host_dest_addr; 7345 __le16 dir_idx; 7346 u8 unused_0[2]; 7347 __le32 offset; 7348 __le32 len; 7349 u8 unused_1[4]; 7350}; 7351 7352/* hwrm_nvm_read_output (size:128b/16B) */ 7353struct hwrm_nvm_read_output { 7354 __le16 error_code; 7355 __le16 req_type; 7356 __le16 seq_id; 7357 __le16 resp_len; 7358 u8 unused_0[7]; 7359 u8 valid; 7360}; 7361 7362/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 7363struct hwrm_nvm_get_dir_entries_input { 7364 __le16 req_type; 7365 __le16 cmpl_ring; 7366 __le16 seq_id; 7367 __le16 target_id; 7368 __le64 resp_addr; 7369 __le64 host_dest_addr; 7370}; 7371 7372/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 7373struct hwrm_nvm_get_dir_entries_output { 7374 __le16 error_code; 7375 __le16 req_type; 7376 __le16 seq_id; 7377 __le16 resp_len; 7378 u8 unused_0[7]; 7379 u8 valid; 7380}; 7381 7382/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 7383struct hwrm_nvm_get_dir_info_input { 7384 __le16 req_type; 7385 __le16 cmpl_ring; 7386 __le16 seq_id; 7387 __le16 target_id; 7388 __le64 resp_addr; 7389}; 7390 7391/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 7392struct hwrm_nvm_get_dir_info_output { 7393 __le16 error_code; 7394 __le16 req_type; 7395 __le16 seq_id; 7396 __le16 resp_len; 7397 __le32 entries; 7398 __le32 entry_length; 7399 u8 unused_0[7]; 7400 u8 valid; 7401}; 7402 7403/* hwrm_nvm_write_input (size:384b/48B) */ 7404struct hwrm_nvm_write_input { 7405 __le16 req_type; 7406 __le16 cmpl_ring; 7407 __le16 seq_id; 7408 __le16 target_id; 7409 __le64 resp_addr; 7410 __le64 host_src_addr; 7411 __le16 dir_type; 7412 __le16 dir_ordinal; 7413 __le16 dir_ext; 7414 __le16 dir_attr; 7415 __le32 dir_data_length; 7416 __le16 option; 7417 __le16 flags; 7418 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 7419 __le32 dir_item_length; 7420 __le32 unused_0; 7421}; 7422 7423/* hwrm_nvm_write_output (size:128b/16B) */ 7424struct hwrm_nvm_write_output { 7425 __le16 error_code; 7426 __le16 req_type; 7427 __le16 seq_id; 7428 __le16 resp_len; 7429 __le32 dir_item_length; 7430 __le16 dir_idx; 7431 u8 unused_0; 7432 u8 valid; 7433}; 7434 7435/* hwrm_nvm_write_cmd_err (size:64b/8B) */ 7436struct hwrm_nvm_write_cmd_err { 7437 u8 code; 7438 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 7439 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7440 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 7441 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 7442 u8 unused_0[7]; 7443}; 7444 7445/* hwrm_nvm_modify_input (size:320b/40B) */ 7446struct hwrm_nvm_modify_input { 7447 __le16 req_type; 7448 __le16 cmpl_ring; 7449 __le16 seq_id; 7450 __le16 target_id; 7451 __le64 resp_addr; 7452 __le64 host_src_addr; 7453 __le16 dir_idx; 7454 u8 unused_0[2]; 7455 __le32 offset; 7456 __le32 len; 7457 u8 unused_1[4]; 7458}; 7459 7460/* hwrm_nvm_modify_output (size:128b/16B) */ 7461struct hwrm_nvm_modify_output { 7462 __le16 error_code; 7463 __le16 req_type; 7464 __le16 seq_id; 7465 __le16 resp_len; 7466 u8 unused_0[7]; 7467 u8 valid; 7468}; 7469 7470/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 7471struct hwrm_nvm_find_dir_entry_input { 7472 __le16 req_type; 7473 __le16 cmpl_ring; 7474 __le16 seq_id; 7475 __le16 target_id; 7476 __le64 resp_addr; 7477 __le32 enables; 7478 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 7479 __le16 dir_idx; 7480 __le16 dir_type; 7481 __le16 dir_ordinal; 7482 __le16 dir_ext; 7483 u8 opt_ordinal; 7484 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 7485 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 7486 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 7487 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 7488 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 7489 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 7490 u8 unused_0[3]; 7491}; 7492 7493/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 7494struct hwrm_nvm_find_dir_entry_output { 7495 __le16 error_code; 7496 __le16 req_type; 7497 __le16 seq_id; 7498 __le16 resp_len; 7499 __le32 dir_item_length; 7500 __le32 dir_data_length; 7501 __le32 fw_ver; 7502 __le16 dir_ordinal; 7503 __le16 dir_idx; 7504 u8 unused_0[7]; 7505 u8 valid; 7506}; 7507 7508/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 7509struct hwrm_nvm_erase_dir_entry_input { 7510 __le16 req_type; 7511 __le16 cmpl_ring; 7512 __le16 seq_id; 7513 __le16 target_id; 7514 __le64 resp_addr; 7515 __le16 dir_idx; 7516 u8 unused_0[6]; 7517}; 7518 7519/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 7520struct hwrm_nvm_erase_dir_entry_output { 7521 __le16 error_code; 7522 __le16 req_type; 7523 __le16 seq_id; 7524 __le16 resp_len; 7525 u8 unused_0[7]; 7526 u8 valid; 7527}; 7528 7529/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 7530struct hwrm_nvm_get_dev_info_input { 7531 __le16 req_type; 7532 __le16 cmpl_ring; 7533 __le16 seq_id; 7534 __le16 target_id; 7535 __le64 resp_addr; 7536}; 7537 7538/* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 7539struct hwrm_nvm_get_dev_info_output { 7540 __le16 error_code; 7541 __le16 req_type; 7542 __le16 seq_id; 7543 __le16 resp_len; 7544 __le16 manufacturer_id; 7545 __le16 device_id; 7546 __le32 sector_size; 7547 __le32 nvram_size; 7548 __le32 reserved_size; 7549 __le32 available_size; 7550 u8 nvm_cfg_ver_maj; 7551 u8 nvm_cfg_ver_min; 7552 u8 nvm_cfg_ver_upd; 7553 u8 valid; 7554}; 7555 7556/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 7557struct hwrm_nvm_mod_dir_entry_input { 7558 __le16 req_type; 7559 __le16 cmpl_ring; 7560 __le16 seq_id; 7561 __le16 target_id; 7562 __le64 resp_addr; 7563 __le32 enables; 7564 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 7565 __le16 dir_idx; 7566 __le16 dir_ordinal; 7567 __le16 dir_ext; 7568 __le16 dir_attr; 7569 __le32 checksum; 7570}; 7571 7572/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 7573struct hwrm_nvm_mod_dir_entry_output { 7574 __le16 error_code; 7575 __le16 req_type; 7576 __le16 seq_id; 7577 __le16 resp_len; 7578 u8 unused_0[7]; 7579 u8 valid; 7580}; 7581 7582/* hwrm_nvm_verify_update_input (size:192b/24B) */ 7583struct hwrm_nvm_verify_update_input { 7584 __le16 req_type; 7585 __le16 cmpl_ring; 7586 __le16 seq_id; 7587 __le16 target_id; 7588 __le64 resp_addr; 7589 __le16 dir_type; 7590 __le16 dir_ordinal; 7591 __le16 dir_ext; 7592 u8 unused_0[2]; 7593}; 7594 7595/* hwrm_nvm_verify_update_output (size:128b/16B) */ 7596struct hwrm_nvm_verify_update_output { 7597 __le16 error_code; 7598 __le16 req_type; 7599 __le16 seq_id; 7600 __le16 resp_len; 7601 u8 unused_0[7]; 7602 u8 valid; 7603}; 7604 7605/* hwrm_nvm_install_update_input (size:192b/24B) */ 7606struct hwrm_nvm_install_update_input { 7607 __le16 req_type; 7608 __le16 cmpl_ring; 7609 __le16 seq_id; 7610 __le16 target_id; 7611 __le64 resp_addr; 7612 __le32 install_type; 7613 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 7614 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 7615 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 7616 __le16 flags; 7617 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 7618 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 7619 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 7620 u8 unused_0[2]; 7621}; 7622 7623/* hwrm_nvm_install_update_output (size:192b/24B) */ 7624struct hwrm_nvm_install_update_output { 7625 __le16 error_code; 7626 __le16 req_type; 7627 __le16 seq_id; 7628 __le16 resp_len; 7629 __le64 installed_items; 7630 u8 result; 7631 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 7632 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 7633 u8 problem_item; 7634 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 7635 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 7636 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 7637 u8 reset_required; 7638 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 7639 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 7640 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 7641 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 7642 u8 unused_0[4]; 7643 u8 valid; 7644}; 7645 7646/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 7647struct hwrm_nvm_install_update_cmd_err { 7648 u8 code; 7649 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 7650 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7651 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 7652 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 7653 u8 unused_0[7]; 7654}; 7655 7656/* hwrm_nvm_get_variable_input (size:320b/40B) */ 7657struct hwrm_nvm_get_variable_input { 7658 __le16 req_type; 7659 __le16 cmpl_ring; 7660 __le16 seq_id; 7661 __le16 target_id; 7662 __le64 resp_addr; 7663 __le64 dest_data_addr; 7664 __le16 data_len; 7665 __le16 option_num; 7666 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7667 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7668 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7669 __le16 dimensions; 7670 __le16 index_0; 7671 __le16 index_1; 7672 __le16 index_2; 7673 __le16 index_3; 7674 u8 flags; 7675 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 7676 u8 unused_0; 7677}; 7678 7679/* hwrm_nvm_get_variable_output (size:128b/16B) */ 7680struct hwrm_nvm_get_variable_output { 7681 __le16 error_code; 7682 __le16 req_type; 7683 __le16 seq_id; 7684 __le16 resp_len; 7685 __le16 data_len; 7686 __le16 option_num; 7687 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 7688 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 7689 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 7690 u8 unused_0[3]; 7691 u8 valid; 7692}; 7693 7694/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 7695struct hwrm_nvm_get_variable_cmd_err { 7696 u8 code; 7697 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7698 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7699 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7700 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 7701 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 7702 u8 unused_0[7]; 7703}; 7704 7705/* hwrm_nvm_set_variable_input (size:320b/40B) */ 7706struct hwrm_nvm_set_variable_input { 7707 __le16 req_type; 7708 __le16 cmpl_ring; 7709 __le16 seq_id; 7710 __le16 target_id; 7711 __le64 resp_addr; 7712 __le64 src_data_addr; 7713 __le16 data_len; 7714 __le16 option_num; 7715 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7716 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7717 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7718 __le16 dimensions; 7719 __le16 index_0; 7720 __le16 index_1; 7721 __le16 index_2; 7722 __le16 index_3; 7723 u8 flags; 7724 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 7725 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 7726 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 7727 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 7728 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 7729 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 7730 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 7731 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 7732 u8 unused_0; 7733}; 7734 7735/* hwrm_nvm_set_variable_output (size:128b/16B) */ 7736struct hwrm_nvm_set_variable_output { 7737 __le16 error_code; 7738 __le16 req_type; 7739 __le16 seq_id; 7740 __le16 resp_len; 7741 u8 unused_0[7]; 7742 u8 valid; 7743}; 7744 7745/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 7746struct hwrm_nvm_set_variable_cmd_err { 7747 u8 code; 7748 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7749 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7750 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7751 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 7752 u8 unused_0[7]; 7753}; 7754 7755/* hwrm_selftest_qlist_input (size:128b/16B) */ 7756struct hwrm_selftest_qlist_input { 7757 __le16 req_type; 7758 __le16 cmpl_ring; 7759 __le16 seq_id; 7760 __le16 target_id; 7761 __le64 resp_addr; 7762}; 7763 7764/* hwrm_selftest_qlist_output (size:2240b/280B) */ 7765struct hwrm_selftest_qlist_output { 7766 __le16 error_code; 7767 __le16 req_type; 7768 __le16 seq_id; 7769 __le16 resp_len; 7770 u8 num_tests; 7771 u8 available_tests; 7772 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 7773 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 7774 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 7775 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 7776 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 7777 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7778 u8 offline_tests; 7779 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 7780 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 7781 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 7782 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 7783 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 7784 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7785 u8 unused_0; 7786 __le16 test_timeout; 7787 u8 unused_1[2]; 7788 char test0_name[32]; 7789 char test1_name[32]; 7790 char test2_name[32]; 7791 char test3_name[32]; 7792 char test4_name[32]; 7793 char test5_name[32]; 7794 char test6_name[32]; 7795 char test7_name[32]; 7796 u8 unused_2[7]; 7797 u8 valid; 7798}; 7799 7800/* hwrm_selftest_exec_input (size:192b/24B) */ 7801struct hwrm_selftest_exec_input { 7802 __le16 req_type; 7803 __le16 cmpl_ring; 7804 __le16 seq_id; 7805 __le16 target_id; 7806 __le64 resp_addr; 7807 u8 flags; 7808 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 7809 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 7810 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 7811 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 7812 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 7813 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 7814 u8 unused_0[7]; 7815}; 7816 7817/* hwrm_selftest_exec_output (size:128b/16B) */ 7818struct hwrm_selftest_exec_output { 7819 __le16 error_code; 7820 __le16 req_type; 7821 __le16 seq_id; 7822 __le16 resp_len; 7823 u8 requested_tests; 7824 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 7825 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 7826 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 7827 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 7828 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 7829 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 7830 u8 test_success; 7831 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 7832 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 7833 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 7834 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 7835 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 7836 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 7837 u8 unused_0[5]; 7838 u8 valid; 7839}; 7840 7841/* hwrm_selftest_irq_input (size:128b/16B) */ 7842struct hwrm_selftest_irq_input { 7843 __le16 req_type; 7844 __le16 cmpl_ring; 7845 __le16 seq_id; 7846 __le16 target_id; 7847 __le64 resp_addr; 7848}; 7849 7850/* hwrm_selftest_irq_output (size:128b/16B) */ 7851struct hwrm_selftest_irq_output { 7852 __le16 error_code; 7853 __le16 req_type; 7854 __le16 seq_id; 7855 __le16 resp_len; 7856 u8 unused_0[7]; 7857 u8 valid; 7858}; 7859 7860#endif /* _BNXT_HSI_H_ */ 7861