LXR linux/drivers/net/ethernet/cavium/liquidio/cn66xx

   1/**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2016 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17 ***********************************************************************/
  18/*! \file  cn66xx_device.h
  19 *  \brief Host Driver: Routines that perform CN66XX specific operations.
  20 */
  21
  22#ifndef __CN66XX_DEVICE_H__
  23#define  __CN66XX_DEVICE_H__
  24
  25/* Register address and configuration for a CN6XXX devices.
  26 * If device specific changes need to be made then add a struct to include
  27 * device specific fields as shown in the commented section
  28 */
  29struct octeon_cn6xxx {
  30        /** PCI interrupt summary register */
  31        u8 __iomem *intr_sum_reg64;
  32
  33        /** PCI interrupt enable register */
  34        u8 __iomem *intr_enb_reg64;
  35
  36        /** The PCI interrupt mask used by interrupt handler */
  37        u64 intr_mask64;
  38
  39        struct octeon_config *conf;
  40
  41        /* Example additional fields - not used currently
  42         *  struct {
  43         *  }cn6xyz;
  44         */
  45
  46        /* For the purpose of atomic access to interrupt enable reg */
  47        spinlock_t lock_for_droq_int_enb_reg;
  48
  49};
  50
  51enum octeon_pcie_mps {
  52        PCIE_MPS_DEFAULT = -1,  /* Use the default setup by BIOS */
  53        PCIE_MPS_128B = 0,
  54        PCIE_MPS_256B = 1
  55};
  56
  57enum octeon_pcie_mrrs {
  58        PCIE_MRRS_DEFAULT = -1, /* Use the default setup by BIOS */
  59        PCIE_MRRS_128B = 0,
  60        PCIE_MRRS_256B = 1,
  61        PCIE_MRRS_512B = 2,
  62        PCIE_MRRS_1024B = 3,
  63        PCIE_MRRS_2048B = 4,
  64        PCIE_MRRS_4096B = 5
  65};
  66
  67/* Common functions for 66xx and 68xx */
  68int lio_cn6xxx_soft_reset(struct octeon_device *oct);
  69void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct);
  70void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct,
  71                               enum octeon_pcie_mps mps);
  72void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct,
  73                                enum octeon_pcie_mrrs mrrs);
  74void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct);
  75void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct);
  76void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
  77void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
  78int lio_cn6xxx_enable_io_queues(struct octeon_device *oct);
  79void lio_cn6xxx_disable_io_queues(struct octeon_device *oct);
  80irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev);
  81void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
  82                               u32 idx, int valid);
  83void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask);
  84u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx);
  85u32
  86lio_cn6xxx_update_read_index(struct octeon_instr_queue *iq);
  87void lio_cn6xxx_enable_interrupt(struct octeon_device *oct, u8 unused);
  88void lio_cn6xxx_disable_interrupt(struct octeon_device *oct, u8 unused);
  89void cn6xxx_get_pcie_qlmport(struct octeon_device *oct);
  90void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip,
  91                                  struct octeon_reg_list *reg_list);
  92u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct);
  93u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
  94int lio_setup_cn66xx_octeon_device(struct octeon_device *oct);
  95int lio_validate_cn6xxx_config_info(struct octeon_device *oct,
  96                                    struct octeon_config *conf6xxx);
  97
  98#endif
  99