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16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/spinlock.h>
21#include <linux/slab.h>
22#include <linux/dma-mapping.h>
23#include <linux/cache.h>
24#include <linux/interrupt.h>
25#include <linux/reset.h>
26#include <linux/clk.h>
27#include <linux/of.h>
28#include <linux/of_mdio.h>
29#include <linux/of_net.h>
30#include <linux/of_platform.h>
31#include <linux/etherdevice.h>
32#include <linux/if_vlan.h>
33#include <linux/skbuff.h>
34#include <linux/phy.h>
35#include <linux/crc32.h>
36#include <linux/ethtool.h>
37#include <linux/tcp.h>
38#include <linux/u64_stats_sync.h>
39
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43
44#include "gemini.h"
45
46#define DRV_NAME "gmac-gemini"
47#define DRV_VERSION "1.0"
48
49#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
50static int debug = -1;
51module_param(debug, int, 0);
52MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
53
54#define HSIZE_8 0x00
55#define HSIZE_16 0x01
56#define HSIZE_32 0x02
57
58#define HBURST_SINGLE 0x00
59#define HBURST_INCR 0x01
60#define HBURST_INCR4 0x02
61#define HBURST_INCR8 0x03
62
63#define HPROT_DATA_CACHE BIT(0)
64#define HPROT_PRIVILIGED BIT(1)
65#define HPROT_BUFFERABLE BIT(2)
66#define HPROT_CACHABLE BIT(3)
67
68#define DEFAULT_RX_COALESCE_NSECS 0
69#define DEFAULT_GMAC_RXQ_ORDER 9
70#define DEFAULT_GMAC_TXQ_ORDER 8
71#define DEFAULT_RX_BUF_ORDER 11
72#define DEFAULT_NAPI_WEIGHT 64
73#define TX_MAX_FRAGS 16
74#define TX_QUEUE_NUM 1
75#define RX_MAX_ALLOC_ORDER 2
76
77#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
78 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
79#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
80 GMAC0_SWTQ00_FIN_INT_BIT)
81#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
82
83#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
84 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
85 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
86
87
88
89
90struct gmac_queue_page {
91 struct page *page;
92 dma_addr_t mapping;
93};
94
95struct gmac_txq {
96 struct gmac_txdesc *ring;
97 struct sk_buff **skb;
98 unsigned int cptr;
99 unsigned int noirq_packets;
100};
101
102struct gemini_ethernet;
103
104struct gemini_ethernet_port {
105 u8 id;
106
107 struct gemini_ethernet *geth;
108 struct net_device *netdev;
109 struct device *dev;
110 void __iomem *dma_base;
111 void __iomem *gmac_base;
112 struct clk *pclk;
113 struct reset_control *reset;
114 int irq;
115 __le32 mac_addr[3];
116
117 void __iomem *rxq_rwptr;
118 struct gmac_rxdesc *rxq_ring;
119 unsigned int rxq_order;
120
121 struct napi_struct napi;
122 struct hrtimer rx_coalesce_timer;
123 unsigned int rx_coalesce_nsecs;
124 unsigned int freeq_refill;
125 struct gmac_txq txq[TX_QUEUE_NUM];
126 unsigned int txq_order;
127 unsigned int irq_every_tx_packets;
128
129 dma_addr_t rxq_dma_base;
130 dma_addr_t txq_dma_base;
131
132 unsigned int msg_enable;
133 spinlock_t config_lock;
134
135 struct u64_stats_sync tx_stats_syncp;
136 struct u64_stats_sync rx_stats_syncp;
137 struct u64_stats_sync ir_stats_syncp;
138
139 struct rtnl_link_stats64 stats;
140 u64 hw_stats[RX_STATS_NUM];
141 u64 rx_stats[RX_STATUS_NUM];
142 u64 rx_csum_stats[RX_CHKSUM_NUM];
143 u64 rx_napi_exits;
144 u64 tx_frag_stats[TX_MAX_FRAGS];
145 u64 tx_frags_linearized;
146 u64 tx_hw_csummed;
147};
148
149struct gemini_ethernet {
150 struct device *dev;
151 void __iomem *base;
152 struct gemini_ethernet_port *port0;
153 struct gemini_ethernet_port *port1;
154 bool initialized;
155
156 spinlock_t irq_lock;
157 unsigned int freeq_order;
158 unsigned int freeq_frag_order;
159 struct gmac_rxdesc *freeq_ring;
160 dma_addr_t freeq_dma_base;
161 struct gmac_queue_page *freeq_pages;
162 unsigned int num_freeq_pages;
163 spinlock_t freeq_lock;
164};
165
166#define GMAC_STATS_NUM ( \
167 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
168 TX_MAX_FRAGS + 2)
169
170static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
171 "GMAC_IN_DISCARDS",
172 "GMAC_IN_ERRORS",
173 "GMAC_IN_MCAST",
174 "GMAC_IN_BCAST",
175 "GMAC_IN_MAC1",
176 "GMAC_IN_MAC2",
177 "RX_STATUS_GOOD_FRAME",
178 "RX_STATUS_TOO_LONG_GOOD_CRC",
179 "RX_STATUS_RUNT_FRAME",
180 "RX_STATUS_SFD_NOT_FOUND",
181 "RX_STATUS_CRC_ERROR",
182 "RX_STATUS_TOO_LONG_BAD_CRC",
183 "RX_STATUS_ALIGNMENT_ERROR",
184 "RX_STATUS_TOO_LONG_BAD_ALIGN",
185 "RX_STATUS_RX_ERR",
186 "RX_STATUS_DA_FILTERED",
187 "RX_STATUS_BUFFER_FULL",
188 "RX_STATUS_11",
189 "RX_STATUS_12",
190 "RX_STATUS_13",
191 "RX_STATUS_14",
192 "RX_STATUS_15",
193 "RX_CHKSUM_IP_UDP_TCP_OK",
194 "RX_CHKSUM_IP_OK_ONLY",
195 "RX_CHKSUM_NONE",
196 "RX_CHKSUM_3",
197 "RX_CHKSUM_IP_ERR_UNKNOWN",
198 "RX_CHKSUM_IP_ERR",
199 "RX_CHKSUM_TCP_UDP_ERR",
200 "RX_CHKSUM_7",
201 "RX_NAPI_EXITS",
202 "TX_FRAGS[1]",
203 "TX_FRAGS[2]",
204 "TX_FRAGS[3]",
205 "TX_FRAGS[4]",
206 "TX_FRAGS[5]",
207 "TX_FRAGS[6]",
208 "TX_FRAGS[7]",
209 "TX_FRAGS[8]",
210 "TX_FRAGS[9]",
211 "TX_FRAGS[10]",
212 "TX_FRAGS[11]",
213 "TX_FRAGS[12]",
214 "TX_FRAGS[13]",
215 "TX_FRAGS[14]",
216 "TX_FRAGS[15]",
217 "TX_FRAGS[16+]",
218 "TX_FRAGS_LINEARIZED",
219 "TX_HW_CSUMMED",
220};
221
222static void gmac_dump_dma_state(struct net_device *netdev);
223
224static void gmac_update_config0_reg(struct net_device *netdev,
225 u32 val, u32 vmask)
226{
227 struct gemini_ethernet_port *port = netdev_priv(netdev);
228 unsigned long flags;
229 u32 reg;
230
231 spin_lock_irqsave(&port->config_lock, flags);
232
233 reg = readl(port->gmac_base + GMAC_CONFIG0);
234 reg = (reg & ~vmask) | val;
235 writel(reg, port->gmac_base + GMAC_CONFIG0);
236
237 spin_unlock_irqrestore(&port->config_lock, flags);
238}
239
240static void gmac_enable_tx_rx(struct net_device *netdev)
241{
242 struct gemini_ethernet_port *port = netdev_priv(netdev);
243 unsigned long flags;
244 u32 reg;
245
246 spin_lock_irqsave(&port->config_lock, flags);
247
248 reg = readl(port->gmac_base + GMAC_CONFIG0);
249 reg &= ~CONFIG0_TX_RX_DISABLE;
250 writel(reg, port->gmac_base + GMAC_CONFIG0);
251
252 spin_unlock_irqrestore(&port->config_lock, flags);
253}
254
255static void gmac_disable_tx_rx(struct net_device *netdev)
256{
257 struct gemini_ethernet_port *port = netdev_priv(netdev);
258 unsigned long flags;
259 u32 val;
260
261 spin_lock_irqsave(&port->config_lock, flags);
262
263 val = readl(port->gmac_base + GMAC_CONFIG0);
264 val |= CONFIG0_TX_RX_DISABLE;
265 writel(val, port->gmac_base + GMAC_CONFIG0);
266
267 spin_unlock_irqrestore(&port->config_lock, flags);
268
269 mdelay(10);
270}
271
272static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
273{
274 struct gemini_ethernet_port *port = netdev_priv(netdev);
275 unsigned long flags;
276 u32 val;
277
278 spin_lock_irqsave(&port->config_lock, flags);
279
280 val = readl(port->gmac_base + GMAC_CONFIG0);
281 val &= ~CONFIG0_FLOW_CTL;
282 if (tx)
283 val |= CONFIG0_FLOW_TX;
284 if (rx)
285 val |= CONFIG0_FLOW_RX;
286 writel(val, port->gmac_base + GMAC_CONFIG0);
287
288 spin_unlock_irqrestore(&port->config_lock, flags);
289}
290
291static void gmac_speed_set(struct net_device *netdev)
292{
293 struct gemini_ethernet_port *port = netdev_priv(netdev);
294 struct phy_device *phydev = netdev->phydev;
295 union gmac_status status, old_status;
296 int pause_tx = 0;
297 int pause_rx = 0;
298
299 status.bits32 = readl(port->gmac_base + GMAC_STATUS);
300 old_status.bits32 = status.bits32;
301 status.bits.link = phydev->link;
302 status.bits.duplex = phydev->duplex;
303
304 switch (phydev->speed) {
305 case 1000:
306 status.bits.speed = GMAC_SPEED_1000;
307 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
308 status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
309 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n",
310 phydev_name(phydev));
311 break;
312 case 100:
313 status.bits.speed = GMAC_SPEED_100;
314 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
315 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
316 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n",
317 phydev_name(phydev));
318 break;
319 case 10:
320 status.bits.speed = GMAC_SPEED_10;
321 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
322 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
323 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n",
324 phydev_name(phydev));
325 break;
326 default:
327 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n",
328 phydev->speed, phydev_name(phydev));
329 }
330
331 if (phydev->duplex == DUPLEX_FULL) {
332 u16 lcladv = phy_read(phydev, MII_ADVERTISE);
333 u16 rmtadv = phy_read(phydev, MII_LPA);
334 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
335
336 if (cap & FLOW_CTRL_RX)
337 pause_rx = 1;
338 if (cap & FLOW_CTRL_TX)
339 pause_tx = 1;
340 }
341
342 gmac_set_flow_control(netdev, pause_tx, pause_rx);
343
344 if (old_status.bits32 == status.bits32)
345 return;
346
347 if (netif_msg_link(port)) {
348 phy_print_status(phydev);
349 netdev_info(netdev, "link flow control: %s\n",
350 phydev->pause
351 ? (phydev->asym_pause ? "tx" : "both")
352 : (phydev->asym_pause ? "rx" : "none")
353 );
354 }
355
356 gmac_disable_tx_rx(netdev);
357 writel(status.bits32, port->gmac_base + GMAC_STATUS);
358 gmac_enable_tx_rx(netdev);
359}
360
361static int gmac_setup_phy(struct net_device *netdev)
362{
363 struct gemini_ethernet_port *port = netdev_priv(netdev);
364 union gmac_status status = { .bits32 = 0 };
365 struct device *dev = port->dev;
366 struct phy_device *phy;
367
368 phy = of_phy_get_and_connect(netdev,
369 dev->of_node,
370 gmac_speed_set);
371 if (!phy)
372 return -ENODEV;
373 netdev->phydev = phy;
374
375 phy_set_max_speed(phy, SPEED_1000);
376 phy_support_asym_pause(phy);
377
378
379 switch (phy->interface) {
380 case PHY_INTERFACE_MODE_MII:
381 netdev_dbg(netdev,
382 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n");
383 status.bits.mii_rmii = GMAC_PHY_MII;
384 break;
385 case PHY_INTERFACE_MODE_GMII:
386 netdev_dbg(netdev,
387 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n");
388 status.bits.mii_rmii = GMAC_PHY_GMII;
389 break;
390 case PHY_INTERFACE_MODE_RGMII:
391 netdev_dbg(netdev,
392 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n");
393 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
394 break;
395 default:
396 netdev_err(netdev, "Unsupported MII interface\n");
397 phy_disconnect(phy);
398 netdev->phydev = NULL;
399 return -EINVAL;
400 }
401 writel(status.bits32, port->gmac_base + GMAC_STATUS);
402
403 if (netif_msg_link(port))
404 phy_attached_info(phy);
405
406 return 0;
407}
408
409
410
411
412
413struct gmac_max_framelen {
414 unsigned int max_l3_len;
415 u8 val;
416};
417
418static const struct gmac_max_framelen gmac_maxlens[] = {
419 {
420 .max_l3_len = 1518,
421 .val = CONFIG0_MAXLEN_1518,
422 },
423 {
424 .max_l3_len = 1522,
425 .val = CONFIG0_MAXLEN_1522,
426 },
427 {
428 .max_l3_len = 1536,
429 .val = CONFIG0_MAXLEN_1536,
430 },
431 {
432 .max_l3_len = 1542,
433 .val = CONFIG0_MAXLEN_1542,
434 },
435 {
436 .max_l3_len = 9212,
437 .val = CONFIG0_MAXLEN_9k,
438 },
439 {
440 .max_l3_len = 10236,
441 .val = CONFIG0_MAXLEN_10k,
442 },
443};
444
445static int gmac_pick_rx_max_len(unsigned int max_l3_len)
446{
447 const struct gmac_max_framelen *maxlen;
448 int maxtot;
449 int i;
450
451 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN;
452
453 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) {
454 maxlen = &gmac_maxlens[i];
455 if (maxtot <= maxlen->max_l3_len)
456 return maxlen->val;
457 }
458
459 return -1;
460}
461
462static int gmac_init(struct net_device *netdev)
463{
464 struct gemini_ethernet_port *port = netdev_priv(netdev);
465 union gmac_config0 config0 = { .bits = {
466 .dis_tx = 1,
467 .dis_rx = 1,
468 .ipv4_rx_chksum = 1,
469 .ipv6_rx_chksum = 1,
470 .rx_err_detect = 1,
471 .rgmm_edge = 1,
472 .port0_chk_hwq = 1,
473 .port1_chk_hwq = 1,
474 .port0_chk_toeq = 1,
475 .port1_chk_toeq = 1,
476 .port0_chk_classq = 1,
477 .port1_chk_classq = 1,
478 } };
479 union gmac_ahb_weight ahb_weight = { .bits = {
480 .rx_weight = 1,
481 .tx_weight = 1,
482 .hash_weight = 1,
483 .pre_req = 0x1f,
484 .tq_dv_threshold = 0,
485 } };
486 union gmac_tx_wcr0 hw_weigh = { .bits = {
487 .hw_tq3 = 1,
488 .hw_tq2 = 1,
489 .hw_tq1 = 1,
490 .hw_tq0 = 1,
491 } };
492 union gmac_tx_wcr1 sw_weigh = { .bits = {
493 .sw_tq5 = 1,
494 .sw_tq4 = 1,
495 .sw_tq3 = 1,
496 .sw_tq2 = 1,
497 .sw_tq1 = 1,
498 .sw_tq0 = 1,
499 } };
500 union gmac_config1 config1 = { .bits = {
501 .set_threshold = 16,
502 .rel_threshold = 24,
503 } };
504 union gmac_config2 config2 = { .bits = {
505 .set_threshold = 16,
506 .rel_threshold = 32,
507 } };
508 union gmac_config3 config3 = { .bits = {
509 .set_threshold = 0,
510 .rel_threshold = 0,
511 } };
512 union gmac_config0 tmp;
513 u32 val;
514
515 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
516 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
517 config0.bits.reserved = tmp.bits.reserved;
518 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
519 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
520 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
521 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
522
523 val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
524 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
525
526 writel(hw_weigh.bits32,
527 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
528 writel(sw_weigh.bits32,
529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
530
531 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
532 port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
533 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
534
535
536
537
538 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
539
540 return 0;
541}
542
543static void gmac_uninit(struct net_device *netdev)
544{
545 if (netdev->phydev)
546 phy_disconnect(netdev->phydev);
547}
548
549static int gmac_setup_txqs(struct net_device *netdev)
550{
551 struct gemini_ethernet_port *port = netdev_priv(netdev);
552 unsigned int n_txq = netdev->num_tx_queues;
553 struct gemini_ethernet *geth = port->geth;
554 size_t entries = 1 << port->txq_order;
555 struct gmac_txq *txq = port->txq;
556 struct gmac_txdesc *desc_ring;
557 size_t len = n_txq * entries;
558 struct sk_buff **skb_tab;
559 void __iomem *rwptr_reg;
560 unsigned int r;
561 int i;
562
563 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
564
565 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
566 if (!skb_tab)
567 return -ENOMEM;
568
569 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
570 &port->txq_dma_base, GFP_KERNEL);
571
572 if (!desc_ring) {
573 kfree(skb_tab);
574 return -ENOMEM;
575 }
576
577 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
578 dev_warn(geth->dev, "TX queue base is not aligned\n");
579 kfree(skb_tab);
580 return -ENOMEM;
581 }
582
583 writel(port->txq_dma_base | port->txq_order,
584 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
585
586 for (i = 0; i < n_txq; i++) {
587 txq->ring = desc_ring;
588 txq->skb = skb_tab;
589 txq->noirq_packets = 0;
590
591 r = readw(rwptr_reg);
592 rwptr_reg += 2;
593 writew(r, rwptr_reg);
594 rwptr_reg += 2;
595 txq->cptr = r;
596
597 txq++;
598 desc_ring += entries;
599 skb_tab += entries;
600 }
601
602 return 0;
603}
604
605static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
606 unsigned int r)
607{
608 struct gemini_ethernet_port *port = netdev_priv(netdev);
609 unsigned int m = (1 << port->txq_order) - 1;
610 struct gemini_ethernet *geth = port->geth;
611 unsigned int c = txq->cptr;
612 union gmac_txdesc_0 word0;
613 union gmac_txdesc_1 word1;
614 unsigned int hwchksum = 0;
615 unsigned long bytes = 0;
616 struct gmac_txdesc *txd;
617 unsigned short nfrags;
618 unsigned int errs = 0;
619 unsigned int pkts = 0;
620 unsigned int word3;
621 dma_addr_t mapping;
622
623 if (c == r)
624 return;
625
626 while (c != r) {
627 txd = txq->ring + c;
628 word0 = txd->word0;
629 word1 = txd->word1;
630 mapping = txd->word2.buf_adr;
631 word3 = txd->word3.bits32;
632
633 dma_unmap_single(geth->dev, mapping,
634 word0.bits.buffer_size, DMA_TO_DEVICE);
635
636 if (word3 & EOF_BIT)
637 dev_kfree_skb(txq->skb[c]);
638
639 c++;
640 c &= m;
641
642 if (!(word3 & SOF_BIT))
643 continue;
644
645 if (!word0.bits.status_tx_ok) {
646 errs++;
647 continue;
648 }
649
650 pkts++;
651 bytes += txd->word1.bits.byte_count;
652
653 if (word1.bits32 & TSS_CHECKUM_ENABLE)
654 hwchksum++;
655
656 nfrags = word0.bits.desc_count - 1;
657 if (nfrags) {
658 if (nfrags >= TX_MAX_FRAGS)
659 nfrags = TX_MAX_FRAGS - 1;
660
661 u64_stats_update_begin(&port->tx_stats_syncp);
662 port->tx_frag_stats[nfrags]++;
663 u64_stats_update_end(&port->tx_stats_syncp);
664 }
665 }
666
667 u64_stats_update_begin(&port->ir_stats_syncp);
668 port->stats.tx_errors += errs;
669 port->stats.tx_packets += pkts;
670 port->stats.tx_bytes += bytes;
671 port->tx_hw_csummed += hwchksum;
672 u64_stats_update_end(&port->ir_stats_syncp);
673
674 txq->cptr = c;
675}
676
677static void gmac_cleanup_txqs(struct net_device *netdev)
678{
679 struct gemini_ethernet_port *port = netdev_priv(netdev);
680 unsigned int n_txq = netdev->num_tx_queues;
681 struct gemini_ethernet *geth = port->geth;
682 void __iomem *rwptr_reg;
683 unsigned int r, i;
684
685 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
686
687 for (i = 0; i < n_txq; i++) {
688 r = readw(rwptr_reg);
689 rwptr_reg += 2;
690 writew(r, rwptr_reg);
691 rwptr_reg += 2;
692
693 gmac_clean_txq(netdev, port->txq + i, r);
694 }
695 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
696
697 kfree(port->txq->skb);
698 dma_free_coherent(geth->dev,
699 n_txq * sizeof(*port->txq->ring) << port->txq_order,
700 port->txq->ring, port->txq_dma_base);
701}
702
703static int gmac_setup_rxq(struct net_device *netdev)
704{
705 struct gemini_ethernet_port *port = netdev_priv(netdev);
706 struct gemini_ethernet *geth = port->geth;
707 struct nontoe_qhdr __iomem *qhdr;
708
709 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
710 port->rxq_rwptr = &qhdr->word1;
711
712
713 port->rxq_ring = dma_alloc_coherent(geth->dev,
714 sizeof(*port->rxq_ring) << port->rxq_order,
715 &port->rxq_dma_base, GFP_KERNEL);
716 if (!port->rxq_ring)
717 return -ENOMEM;
718 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
719 dev_warn(geth->dev, "RX queue base is not aligned\n");
720 return -ENOMEM;
721 }
722
723 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
724 writel(0, port->rxq_rwptr);
725 return 0;
726}
727
728static struct gmac_queue_page *
729gmac_get_queue_page(struct gemini_ethernet *geth,
730 struct gemini_ethernet_port *port,
731 dma_addr_t addr)
732{
733 struct gmac_queue_page *gpage;
734 dma_addr_t mapping;
735 int i;
736
737
738 mapping = addr & PAGE_MASK;
739
740 if (!geth->freeq_pages) {
741 dev_err(geth->dev, "try to get page with no page list\n");
742 return NULL;
743 }
744
745
746 for (i = 0; i < geth->num_freeq_pages; i++) {
747 gpage = &geth->freeq_pages[i];
748 if (gpage->mapping == mapping)
749 return gpage;
750 }
751
752 return NULL;
753}
754
755static void gmac_cleanup_rxq(struct net_device *netdev)
756{
757 struct gemini_ethernet_port *port = netdev_priv(netdev);
758 struct gemini_ethernet *geth = port->geth;
759 struct gmac_rxdesc *rxd = port->rxq_ring;
760 static struct gmac_queue_page *gpage;
761 struct nontoe_qhdr __iomem *qhdr;
762 void __iomem *dma_reg;
763 void __iomem *ptr_reg;
764 dma_addr_t mapping;
765 union dma_rwptr rw;
766 unsigned int r, w;
767
768 qhdr = geth->base +
769 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
770 dma_reg = &qhdr->word0;
771 ptr_reg = &qhdr->word1;
772
773 rw.bits32 = readl(ptr_reg);
774 r = rw.bits.rptr;
775 w = rw.bits.wptr;
776 writew(r, ptr_reg + 2);
777
778 writel(0, dma_reg);
779
780
781
782
783 while (r != w) {
784 mapping = rxd[r].word2.buf_adr;
785 r++;
786 r &= ((1 << port->rxq_order) - 1);
787
788 if (!mapping)
789 continue;
790
791
792 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
793 if (!gpage) {
794 dev_err(geth->dev, "could not find page\n");
795 continue;
796 }
797
798 put_page(gpage->page);
799 }
800
801 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
802 port->rxq_ring, port->rxq_dma_base);
803}
804
805static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
806 int pn)
807{
808 struct gmac_rxdesc *freeq_entry;
809 struct gmac_queue_page *gpage;
810 unsigned int fpp_order;
811 unsigned int frag_len;
812 dma_addr_t mapping;
813 struct page *page;
814 int i;
815
816
817 page = alloc_page(GFP_ATOMIC);
818 if (!page)
819 return NULL;
820
821 mapping = dma_map_single(geth->dev, page_address(page),
822 PAGE_SIZE, DMA_FROM_DEVICE);
823 if (dma_mapping_error(geth->dev, mapping)) {
824 put_page(page);
825 return NULL;
826 }
827
828
829
830
831
832
833
834 frag_len = 1 << geth->freeq_frag_order;
835 fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
836 freeq_entry = geth->freeq_ring + (pn << fpp_order);
837 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
838 pn, frag_len, (1 << fpp_order), freeq_entry);
839 for (i = (1 << fpp_order); i > 0; i--) {
840 freeq_entry->word2.buf_adr = mapping;
841 freeq_entry++;
842 mapping += frag_len;
843 }
844
845
846 gpage = &geth->freeq_pages[pn];
847 if (gpage->page) {
848 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
849 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
850
851
852
853 put_page(gpage->page);
854 }
855
856
857 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
858 pn, (unsigned int)mapping, page);
859 gpage->mapping = mapping;
860 gpage->page = page;
861
862 return page;
863}
864
865
866
867
868
869
870
871
872static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
873{
874 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
875 unsigned int count = 0;
876 unsigned int pn, epn;
877 unsigned long flags;
878 union dma_rwptr rw;
879 unsigned int m_pn;
880
881
882 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
883
884 spin_lock_irqsave(&geth->freeq_lock, flags);
885
886 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
887 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
888 epn = (rw.bits.rptr >> fpp_order) - 1;
889 epn &= m_pn;
890
891
892 while (pn != epn) {
893 struct gmac_queue_page *gpage;
894 struct page *page;
895
896 gpage = &geth->freeq_pages[pn];
897 page = gpage->page;
898
899 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
900 pn, page_ref_count(page), 1 << fpp_order);
901
902 if (page_ref_count(page) > 1) {
903 unsigned int fl = (pn - epn) & m_pn;
904
905 if (fl > 64 >> fpp_order)
906 break;
907
908 page = geth_freeq_alloc_map_page(geth, pn);
909 if (!page)
910 break;
911 }
912
913
914 page_ref_add(page, 1 << fpp_order);
915 count += 1 << fpp_order;
916 pn++;
917 pn &= m_pn;
918 }
919
920 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
921
922 spin_unlock_irqrestore(&geth->freeq_lock, flags);
923
924 return count;
925}
926
927static int geth_setup_freeq(struct gemini_ethernet *geth)
928{
929 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
930 unsigned int frag_len = 1 << geth->freeq_frag_order;
931 unsigned int len = 1 << geth->freeq_order;
932 unsigned int pages = len >> fpp_order;
933 union queue_threshold qt;
934 union dma_skb_size skbsz;
935 unsigned int filled;
936 unsigned int pn;
937
938 geth->freeq_ring = dma_alloc_coherent(geth->dev,
939 sizeof(*geth->freeq_ring) << geth->freeq_order,
940 &geth->freeq_dma_base, GFP_KERNEL);
941 if (!geth->freeq_ring)
942 return -ENOMEM;
943 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
944 dev_warn(geth->dev, "queue ring base is not aligned\n");
945 goto err_freeq;
946 }
947
948
949 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages),
950 GFP_KERNEL);
951 if (!geth->freeq_pages)
952 goto err_freeq;
953 geth->num_freeq_pages = pages;
954
955 dev_info(geth->dev, "allocate %d pages for queue\n", pages);
956 for (pn = 0; pn < pages; pn++)
957 if (!geth_freeq_alloc_map_page(geth, pn))
958 goto err_freeq_alloc;
959
960 filled = geth_fill_freeq(geth, false);
961 if (!filled)
962 goto err_freeq_alloc;
963
964 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
965 qt.bits.swfq_empty = 32;
966 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
967
968 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
969 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
970 writel(geth->freeq_dma_base | geth->freeq_order,
971 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
972
973 return 0;
974
975err_freeq_alloc:
976 while (pn > 0) {
977 struct gmac_queue_page *gpage;
978 dma_addr_t mapping;
979
980 --pn;
981 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
982 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
983 gpage = &geth->freeq_pages[pn];
984 put_page(gpage->page);
985 }
986
987 kfree(geth->freeq_pages);
988err_freeq:
989 dma_free_coherent(geth->dev,
990 sizeof(*geth->freeq_ring) << geth->freeq_order,
991 geth->freeq_ring, geth->freeq_dma_base);
992 geth->freeq_ring = NULL;
993 return -ENOMEM;
994}
995
996
997
998
999
1000static void geth_cleanup_freeq(struct gemini_ethernet *geth)
1001{
1002 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
1003 unsigned int frag_len = 1 << geth->freeq_frag_order;
1004 unsigned int len = 1 << geth->freeq_order;
1005 unsigned int pages = len >> fpp_order;
1006 unsigned int pn;
1007
1008 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
1009 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
1010 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1011
1012 for (pn = 0; pn < pages; pn++) {
1013 struct gmac_queue_page *gpage;
1014 dma_addr_t mapping;
1015
1016 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
1017 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
1018
1019 gpage = &geth->freeq_pages[pn];
1020 while (page_ref_count(gpage->page) > 0)
1021 put_page(gpage->page);
1022 }
1023
1024 kfree(geth->freeq_pages);
1025
1026 dma_free_coherent(geth->dev,
1027 sizeof(*geth->freeq_ring) << geth->freeq_order,
1028 geth->freeq_ring, geth->freeq_dma_base);
1029}
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040static int geth_resize_freeq(struct gemini_ethernet_port *port)
1041{
1042 struct gemini_ethernet *geth = port->geth;
1043 struct net_device *netdev = port->netdev;
1044 struct gemini_ethernet_port *other_port;
1045 struct net_device *other_netdev;
1046 unsigned int new_size = 0;
1047 unsigned int new_order;
1048 unsigned long flags;
1049 u32 en;
1050 int ret;
1051
1052 if (netdev->dev_id == 0)
1053 other_netdev = geth->port1->netdev;
1054 else
1055 other_netdev = geth->port0->netdev;
1056
1057 if (other_netdev && netif_running(other_netdev))
1058 return -EBUSY;
1059
1060 new_size = 1 << (port->rxq_order + 1);
1061 netdev_dbg(netdev, "port %d size: %d order %d\n",
1062 netdev->dev_id,
1063 new_size,
1064 port->rxq_order);
1065 if (other_netdev) {
1066 other_port = netdev_priv(other_netdev);
1067 new_size += 1 << (other_port->rxq_order + 1);
1068 netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1069 other_netdev->dev_id,
1070 (1 << (other_port->rxq_order + 1)),
1071 other_port->rxq_order);
1072 }
1073
1074 new_order = min(15, ilog2(new_size - 1) + 1);
1075 dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1076 new_size, new_order);
1077 if (geth->freeq_order == new_order)
1078 return 0;
1079
1080 spin_lock_irqsave(&geth->irq_lock, flags);
1081
1082
1083 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1084 en &= ~SWFQ_EMPTY_INT_BIT;
1085 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1086 spin_unlock_irqrestore(&geth->irq_lock, flags);
1087
1088
1089 if (geth->freeq_ring)
1090 geth_cleanup_freeq(geth);
1091
1092
1093 geth->freeq_order = new_order;
1094 ret = geth_setup_freeq(geth);
1095
1096
1097
1098
1099
1100 spin_lock_irqsave(&geth->irq_lock, flags);
1101 en |= SWFQ_EMPTY_INT_BIT;
1102 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1103 spin_unlock_irqrestore(&geth->irq_lock, flags);
1104
1105 return ret;
1106}
1107
1108static void gmac_tx_irq_enable(struct net_device *netdev,
1109 unsigned int txq, int en)
1110{
1111 struct gemini_ethernet_port *port = netdev_priv(netdev);
1112 struct gemini_ethernet *geth = port->geth;
1113 u32 val, mask;
1114
1115 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1116
1117 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1118
1119 if (en)
1120 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1121
1122 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1123 val = en ? val | mask : val & ~mask;
1124 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1125}
1126
1127static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1128{
1129 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1130
1131 gmac_tx_irq_enable(netdev, txq_num, 0);
1132 netif_tx_wake_queue(ntxq);
1133}
1134
1135static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1136 struct gmac_txq *txq, unsigned short *desc)
1137{
1138 struct gemini_ethernet_port *port = netdev_priv(netdev);
1139 struct skb_shared_info *skb_si = skb_shinfo(skb);
1140 unsigned short m = (1 << port->txq_order) - 1;
1141 short frag, last_frag = skb_si->nr_frags - 1;
1142 struct gemini_ethernet *geth = port->geth;
1143 unsigned int word1, word3, buflen;
1144 unsigned short w = *desc;
1145 struct gmac_txdesc *txd;
1146 skb_frag_t *skb_frag;
1147 dma_addr_t mapping;
1148 unsigned short mtu;
1149 void *buffer;
1150
1151 mtu = ETH_HLEN;
1152 mtu += netdev->mtu;
1153 if (skb->protocol == htons(ETH_P_8021Q))
1154 mtu += VLAN_HLEN;
1155
1156 word1 = skb->len;
1157 word3 = SOF_BIT;
1158
1159 if (word1 > mtu) {
1160 word1 |= TSS_MTU_ENABLE_BIT;
1161 word3 |= mtu;
1162 }
1163
1164 if (skb->ip_summed != CHECKSUM_NONE) {
1165 int tcp = 0;
1166
1167 if (skb->protocol == htons(ETH_P_IP)) {
1168 word1 |= TSS_IP_CHKSUM_BIT;
1169 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1170 } else {
1171 word1 |= TSS_IPV6_ENABLE_BIT;
1172 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1173 }
1174
1175 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1176 }
1177
1178 frag = -1;
1179 while (frag <= last_frag) {
1180 if (frag == -1) {
1181 buffer = skb->data;
1182 buflen = skb_headlen(skb);
1183 } else {
1184 skb_frag = skb_si->frags + frag;
1185 buffer = page_address(skb_frag_page(skb_frag)) +
1186 skb_frag->page_offset;
1187 buflen = skb_frag->size;
1188 }
1189
1190 if (frag == last_frag) {
1191 word3 |= EOF_BIT;
1192 txq->skb[w] = skb;
1193 }
1194
1195 mapping = dma_map_single(geth->dev, buffer, buflen,
1196 DMA_TO_DEVICE);
1197 if (dma_mapping_error(geth->dev, mapping))
1198 goto map_error;
1199
1200 txd = txq->ring + w;
1201 txd->word0.bits32 = buflen;
1202 txd->word1.bits32 = word1;
1203 txd->word2.buf_adr = mapping;
1204 txd->word3.bits32 = word3;
1205
1206 word3 &= MTU_SIZE_BIT_MASK;
1207 w++;
1208 w &= m;
1209 frag++;
1210 }
1211
1212 *desc = w;
1213 return 0;
1214
1215map_error:
1216 while (w != *desc) {
1217 w--;
1218 w &= m;
1219
1220 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1221 txq->ring[w].word0.bits.buffer_size,
1222 DMA_TO_DEVICE);
1223 }
1224 return -ENOMEM;
1225}
1226
1227static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1228{
1229 struct gemini_ethernet_port *port = netdev_priv(netdev);
1230 unsigned short m = (1 << port->txq_order) - 1;
1231 struct netdev_queue *ntxq;
1232 unsigned short r, w, d;
1233 void __iomem *ptr_reg;
1234 struct gmac_txq *txq;
1235 int txq_num, nfrags;
1236 union dma_rwptr rw;
1237
1238 if (skb->len >= 0x10000)
1239 goto out_drop_free;
1240
1241 txq_num = skb_get_queue_mapping(skb);
1242 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1243 txq = &port->txq[txq_num];
1244 ntxq = netdev_get_tx_queue(netdev, txq_num);
1245 nfrags = skb_shinfo(skb)->nr_frags;
1246
1247 rw.bits32 = readl(ptr_reg);
1248 r = rw.bits.rptr;
1249 w = rw.bits.wptr;
1250
1251 d = txq->cptr - w - 1;
1252 d &= m;
1253
1254 if (d < nfrags + 2) {
1255 gmac_clean_txq(netdev, txq, r);
1256 d = txq->cptr - w - 1;
1257 d &= m;
1258
1259 if (d < nfrags + 2) {
1260 netif_tx_stop_queue(ntxq);
1261
1262 d = txq->cptr + nfrags + 16;
1263 d &= m;
1264 txq->ring[d].word3.bits.eofie = 1;
1265 gmac_tx_irq_enable(netdev, txq_num, 1);
1266
1267 u64_stats_update_begin(&port->tx_stats_syncp);
1268 netdev->stats.tx_fifo_errors++;
1269 u64_stats_update_end(&port->tx_stats_syncp);
1270 return NETDEV_TX_BUSY;
1271 }
1272 }
1273
1274 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1275 if (skb_linearize(skb))
1276 goto out_drop;
1277
1278 u64_stats_update_begin(&port->tx_stats_syncp);
1279 port->tx_frags_linearized++;
1280 u64_stats_update_end(&port->tx_stats_syncp);
1281
1282 if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1283 goto out_drop_free;
1284 }
1285
1286 writew(w, ptr_reg + 2);
1287
1288 gmac_clean_txq(netdev, txq, r);
1289 return NETDEV_TX_OK;
1290
1291out_drop_free:
1292 dev_kfree_skb(skb);
1293out_drop:
1294 u64_stats_update_begin(&port->tx_stats_syncp);
1295 port->stats.tx_dropped++;
1296 u64_stats_update_end(&port->tx_stats_syncp);
1297 return NETDEV_TX_OK;
1298}
1299
1300static void gmac_tx_timeout(struct net_device *netdev)
1301{
1302 netdev_err(netdev, "Tx timeout\n");
1303 gmac_dump_dma_state(netdev);
1304}
1305
1306static void gmac_enable_irq(struct net_device *netdev, int enable)
1307{
1308 struct gemini_ethernet_port *port = netdev_priv(netdev);
1309 struct gemini_ethernet *geth = port->geth;
1310 unsigned long flags;
1311 u32 val, mask;
1312
1313 netdev_dbg(netdev, "%s device %d %s\n", __func__,
1314 netdev->dev_id, enable ? "enable" : "disable");
1315 spin_lock_irqsave(&geth->irq_lock, flags);
1316
1317 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1318 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1319 val = enable ? (val | mask) : (val & ~mask);
1320 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1321
1322 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1323 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1324 val = enable ? (val | mask) : (val & ~mask);
1325 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1326
1327 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1328 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1329 val = enable ? (val | mask) : (val & ~mask);
1330 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1331
1332 spin_unlock_irqrestore(&geth->irq_lock, flags);
1333}
1334
1335static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1336{
1337 struct gemini_ethernet_port *port = netdev_priv(netdev);
1338 struct gemini_ethernet *geth = port->geth;
1339 unsigned long flags;
1340 u32 val, mask;
1341
1342 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1343 enable ? "enable" : "disable");
1344 spin_lock_irqsave(&geth->irq_lock, flags);
1345 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1346
1347 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1348 val = enable ? (val | mask) : (val & ~mask);
1349 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1350
1351 spin_unlock_irqrestore(&geth->irq_lock, flags);
1352}
1353
1354static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1355 union gmac_rxdesc_0 word0,
1356 unsigned int frame_len)
1357{
1358 unsigned int rx_csum = word0.bits.chksum_status;
1359 unsigned int rx_status = word0.bits.status;
1360 struct sk_buff *skb = NULL;
1361
1362 port->rx_stats[rx_status]++;
1363 port->rx_csum_stats[rx_csum]++;
1364
1365 if (word0.bits.derr || word0.bits.perr ||
1366 rx_status || frame_len < ETH_ZLEN ||
1367 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1368 port->stats.rx_errors++;
1369
1370 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1371 port->stats.rx_length_errors++;
1372 if (RX_ERROR_OVER(rx_status))
1373 port->stats.rx_over_errors++;
1374 if (RX_ERROR_CRC(rx_status))
1375 port->stats.rx_crc_errors++;
1376 if (RX_ERROR_FRAME(rx_status))
1377 port->stats.rx_frame_errors++;
1378 return NULL;
1379 }
1380
1381 skb = napi_get_frags(&port->napi);
1382 if (!skb)
1383 goto update_exit;
1384
1385 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1386 skb->ip_summed = CHECKSUM_UNNECESSARY;
1387
1388update_exit:
1389 port->stats.rx_bytes += frame_len;
1390 port->stats.rx_packets++;
1391 return skb;
1392}
1393
1394static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1395{
1396 struct gemini_ethernet_port *port = netdev_priv(netdev);
1397 unsigned short m = (1 << port->rxq_order) - 1;
1398 struct gemini_ethernet *geth = port->geth;
1399 void __iomem *ptr_reg = port->rxq_rwptr;
1400 unsigned int frame_len, frag_len;
1401 struct gmac_rxdesc *rx = NULL;
1402 struct gmac_queue_page *gpage;
1403 static struct sk_buff *skb;
1404 union gmac_rxdesc_0 word0;
1405 union gmac_rxdesc_1 word1;
1406 union gmac_rxdesc_3 word3;
1407 struct page *page = NULL;
1408 unsigned int page_offs;
1409 unsigned short r, w;
1410 union dma_rwptr rw;
1411 dma_addr_t mapping;
1412 int frag_nr = 0;
1413
1414 rw.bits32 = readl(ptr_reg);
1415
1416 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1417 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1418 r = rw.bits.rptr;
1419 w = rw.bits.wptr;
1420
1421 while (budget && w != r) {
1422 rx = port->rxq_ring + r;
1423 word0 = rx->word0;
1424 word1 = rx->word1;
1425 mapping = rx->word2.buf_adr;
1426 word3 = rx->word3;
1427
1428 r++;
1429 r &= m;
1430
1431 frag_len = word0.bits.buffer_size;
1432 frame_len = word1.bits.byte_count;
1433 page_offs = mapping & ~PAGE_MASK;
1434
1435 if (!mapping) {
1436 netdev_err(netdev,
1437 "rxq[%u]: HW BUG: zero DMA desc\n", r);
1438 goto err_drop;
1439 }
1440
1441
1442 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1443 if (!gpage) {
1444 dev_err(geth->dev, "could not find mapping\n");
1445 continue;
1446 }
1447 page = gpage->page;
1448
1449 if (word3.bits32 & SOF_BIT) {
1450 if (skb) {
1451 napi_free_frags(&port->napi);
1452 port->stats.rx_dropped++;
1453 }
1454
1455 skb = gmac_skb_if_good_frame(port, word0, frame_len);
1456 if (!skb)
1457 goto err_drop;
1458
1459 page_offs += NET_IP_ALIGN;
1460 frag_len -= NET_IP_ALIGN;
1461 frag_nr = 0;
1462
1463 } else if (!skb) {
1464 put_page(page);
1465 continue;
1466 }
1467
1468 if (word3.bits32 & EOF_BIT)
1469 frag_len = frame_len - skb->len;
1470
1471
1472 if (frag_nr == MAX_SKB_FRAGS)
1473 goto err_drop;
1474
1475 if (frag_len == 0)
1476 netdev_err(netdev, "Received fragment with len = 0\n");
1477
1478 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1479 skb->len += frag_len;
1480 skb->data_len += frag_len;
1481 skb->truesize += frag_len;
1482 frag_nr++;
1483
1484 if (word3.bits32 & EOF_BIT) {
1485 napi_gro_frags(&port->napi);
1486 skb = NULL;
1487 --budget;
1488 }
1489 continue;
1490
1491err_drop:
1492 if (skb) {
1493 napi_free_frags(&port->napi);
1494 skb = NULL;
1495 }
1496
1497 if (mapping)
1498 put_page(page);
1499
1500 port->stats.rx_dropped++;
1501 }
1502
1503 writew(r, ptr_reg);
1504 return budget;
1505}
1506
1507static int gmac_napi_poll(struct napi_struct *napi, int budget)
1508{
1509 struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1510 struct gemini_ethernet *geth = port->geth;
1511 unsigned int freeq_threshold;
1512 unsigned int received;
1513
1514 freeq_threshold = 1 << (geth->freeq_order - 1);
1515 u64_stats_update_begin(&port->rx_stats_syncp);
1516
1517 received = gmac_rx(napi->dev, budget);
1518 if (received < budget) {
1519 napi_gro_flush(napi, false);
1520 napi_complete_done(napi, received);
1521 gmac_enable_rx_irq(napi->dev, 1);
1522 ++port->rx_napi_exits;
1523 }
1524
1525 port->freeq_refill += (budget - received);
1526 if (port->freeq_refill > freeq_threshold) {
1527 port->freeq_refill -= freeq_threshold;
1528 geth_fill_freeq(geth, true);
1529 }
1530
1531 u64_stats_update_end(&port->rx_stats_syncp);
1532 return received;
1533}
1534
1535static void gmac_dump_dma_state(struct net_device *netdev)
1536{
1537 struct gemini_ethernet_port *port = netdev_priv(netdev);
1538 struct gemini_ethernet *geth = port->geth;
1539 void __iomem *ptr_reg;
1540 u32 reg[5];
1541
1542
1543 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1544 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1545 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1546 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1547 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1548 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1549 reg[0], reg[1], reg[2], reg[3], reg[4]);
1550
1551
1552 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1553 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1554 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1555 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1556 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1557 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1558 reg[0], reg[1], reg[2], reg[3], reg[4]);
1559
1560
1561 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1562 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1563 reg[2] = GET_RPTR(port->rxq_rwptr);
1564 reg[3] = GET_WPTR(port->rxq_rwptr);
1565 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1566 reg[0], reg[1], reg[2], reg[3]);
1567
1568 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1569 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1570 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1571 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1572 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1573 reg[0], reg[1], reg[2], reg[3]);
1574
1575
1576 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1577
1578 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1579 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1580 reg[2] = GET_RPTR(ptr_reg);
1581 reg[3] = GET_WPTR(ptr_reg);
1582 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1583 reg[0], reg[1], reg[2], reg[3]);
1584
1585 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1586 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1587 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1588 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1589 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1590 reg[0], reg[1], reg[2], reg[3]);
1591
1592
1593 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1594
1595 reg[0] = GET_RPTR(ptr_reg);
1596 reg[1] = GET_WPTR(ptr_reg);
1597
1598 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1599
1600 reg[2] = GET_RPTR(ptr_reg);
1601 reg[3] = GET_WPTR(ptr_reg);
1602 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1603 reg[0], reg[1], reg[2], reg[3]);
1604}
1605
1606static void gmac_update_hw_stats(struct net_device *netdev)
1607{
1608 struct gemini_ethernet_port *port = netdev_priv(netdev);
1609 unsigned int rx_discards, rx_mcast, rx_bcast;
1610 struct gemini_ethernet *geth = port->geth;
1611 unsigned long flags;
1612
1613 spin_lock_irqsave(&geth->irq_lock, flags);
1614 u64_stats_update_begin(&port->ir_stats_syncp);
1615
1616 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1617 port->hw_stats[0] += rx_discards;
1618 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1619 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1620 port->hw_stats[2] += rx_mcast;
1621 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1622 port->hw_stats[3] += rx_bcast;
1623 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1624 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1625
1626 port->stats.rx_missed_errors += rx_discards;
1627 port->stats.multicast += rx_mcast;
1628 port->stats.multicast += rx_bcast;
1629
1630 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1631 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1632
1633 u64_stats_update_end(&port->ir_stats_syncp);
1634 spin_unlock_irqrestore(&geth->irq_lock, flags);
1635}
1636
1637
1638
1639
1640
1641
1642static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1643{
1644 struct gemini_ethernet_port *port = netdev_priv(netdev);
1645 struct gemini_ethernet *geth = port->geth;
1646 void __iomem *irqif_reg, *irqen_reg;
1647 unsigned int offs, val;
1648
1649
1650 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1651 GLOBAL_INTERRUPT_STATUS_0_REG);
1652
1653 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1654 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1655
1656 val = readl(irqif_reg) & readl(irqen_reg);
1657 return val;
1658}
1659
1660static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1661{
1662 struct gemini_ethernet_port *port =
1663 container_of(timer, struct gemini_ethernet_port,
1664 rx_coalesce_timer);
1665
1666 napi_schedule(&port->napi);
1667 return HRTIMER_NORESTART;
1668}
1669
1670static irqreturn_t gmac_irq(int irq, void *data)
1671{
1672 struct gemini_ethernet_port *port;
1673 struct net_device *netdev = data;
1674 struct gemini_ethernet *geth;
1675 u32 val, orr = 0;
1676
1677 port = netdev_priv(netdev);
1678 geth = port->geth;
1679
1680 val = gmac_get_intr_flags(netdev, 0);
1681 orr |= val;
1682
1683 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1684
1685 netdev_err(netdev, "hw failure/sw bug\n");
1686 gmac_dump_dma_state(netdev);
1687
1688
1689 gmac_enable_irq(netdev, 0);
1690 return IRQ_HANDLED;
1691 }
1692
1693 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1694 gmac_tx_irq(netdev, 0);
1695
1696 val = gmac_get_intr_flags(netdev, 1);
1697 orr |= val;
1698
1699 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1700 gmac_enable_rx_irq(netdev, 0);
1701
1702 if (!port->rx_coalesce_nsecs) {
1703 napi_schedule(&port->napi);
1704 } else {
1705 ktime_t ktime;
1706
1707 ktime = ktime_set(0, port->rx_coalesce_nsecs);
1708 hrtimer_start(&port->rx_coalesce_timer, ktime,
1709 HRTIMER_MODE_REL);
1710 }
1711 }
1712
1713 val = gmac_get_intr_flags(netdev, 4);
1714 orr |= val;
1715
1716 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1717 gmac_update_hw_stats(netdev);
1718
1719 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1720 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1721 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1722
1723 spin_lock(&geth->irq_lock);
1724 u64_stats_update_begin(&port->ir_stats_syncp);
1725 ++port->stats.rx_fifo_errors;
1726 u64_stats_update_end(&port->ir_stats_syncp);
1727 spin_unlock(&geth->irq_lock);
1728 }
1729
1730 return orr ? IRQ_HANDLED : IRQ_NONE;
1731}
1732
1733static void gmac_start_dma(struct gemini_ethernet_port *port)
1734{
1735 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1736 union gmac_dma_ctrl dma_ctrl;
1737
1738 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1739 dma_ctrl.bits.rd_enable = 1;
1740 dma_ctrl.bits.td_enable = 1;
1741 dma_ctrl.bits.loopback = 0;
1742 dma_ctrl.bits.drop_small_ack = 0;
1743 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1744 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1745 dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1746 dma_ctrl.bits.rd_bus = HSIZE_8;
1747 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1748 dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1749 dma_ctrl.bits.td_bus = HSIZE_8;
1750
1751 writel(dma_ctrl.bits32, dma_ctrl_reg);
1752}
1753
1754static void gmac_stop_dma(struct gemini_ethernet_port *port)
1755{
1756 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1757 union gmac_dma_ctrl dma_ctrl;
1758
1759 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1760 dma_ctrl.bits.rd_enable = 0;
1761 dma_ctrl.bits.td_enable = 0;
1762 writel(dma_ctrl.bits32, dma_ctrl_reg);
1763}
1764
1765static int gmac_open(struct net_device *netdev)
1766{
1767 struct gemini_ethernet_port *port = netdev_priv(netdev);
1768 int err;
1769
1770 if (!netdev->phydev) {
1771 err = gmac_setup_phy(netdev);
1772 if (err) {
1773 netif_err(port, ifup, netdev,
1774 "PHY init failed: %d\n", err);
1775 return err;
1776 }
1777 }
1778
1779 err = request_irq(netdev->irq, gmac_irq,
1780 IRQF_SHARED, netdev->name, netdev);
1781 if (err) {
1782 netdev_err(netdev, "no IRQ\n");
1783 return err;
1784 }
1785
1786 netif_carrier_off(netdev);
1787 phy_start(netdev->phydev);
1788
1789 err = geth_resize_freeq(port);
1790
1791
1792
1793 if (err && (err != -EBUSY)) {
1794 netdev_err(netdev, "could not resize freeq\n");
1795 goto err_stop_phy;
1796 }
1797
1798 err = gmac_setup_rxq(netdev);
1799 if (err) {
1800 netdev_err(netdev, "could not setup RXQ\n");
1801 goto err_stop_phy;
1802 }
1803
1804 err = gmac_setup_txqs(netdev);
1805 if (err) {
1806 netdev_err(netdev, "could not setup TXQs\n");
1807 gmac_cleanup_rxq(netdev);
1808 goto err_stop_phy;
1809 }
1810
1811 napi_enable(&port->napi);
1812
1813 gmac_start_dma(port);
1814 gmac_enable_irq(netdev, 1);
1815 gmac_enable_tx_rx(netdev);
1816 netif_tx_start_all_queues(netdev);
1817
1818 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1819 HRTIMER_MODE_REL);
1820 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1821
1822 netdev_dbg(netdev, "opened\n");
1823
1824 return 0;
1825
1826err_stop_phy:
1827 phy_stop(netdev->phydev);
1828 free_irq(netdev->irq, netdev);
1829 return err;
1830}
1831
1832static int gmac_stop(struct net_device *netdev)
1833{
1834 struct gemini_ethernet_port *port = netdev_priv(netdev);
1835
1836 hrtimer_cancel(&port->rx_coalesce_timer);
1837 netif_tx_stop_all_queues(netdev);
1838 gmac_disable_tx_rx(netdev);
1839 gmac_stop_dma(port);
1840 napi_disable(&port->napi);
1841
1842 gmac_enable_irq(netdev, 0);
1843 gmac_cleanup_rxq(netdev);
1844 gmac_cleanup_txqs(netdev);
1845
1846 phy_stop(netdev->phydev);
1847 free_irq(netdev->irq, netdev);
1848
1849 gmac_update_hw_stats(netdev);
1850 return 0;
1851}
1852
1853static void gmac_set_rx_mode(struct net_device *netdev)
1854{
1855 struct gemini_ethernet_port *port = netdev_priv(netdev);
1856 union gmac_rx_fltr filter = { .bits = {
1857 .broadcast = 1,
1858 .multicast = 1,
1859 .unicast = 1,
1860 } };
1861 struct netdev_hw_addr *ha;
1862 unsigned int bit_nr;
1863 u32 mc_filter[2];
1864
1865 mc_filter[1] = 0;
1866 mc_filter[0] = 0;
1867
1868 if (netdev->flags & IFF_PROMISC) {
1869 filter.bits.error = 1;
1870 filter.bits.promiscuous = 1;
1871 mc_filter[1] = ~0;
1872 mc_filter[0] = ~0;
1873 } else if (netdev->flags & IFF_ALLMULTI) {
1874 mc_filter[1] = ~0;
1875 mc_filter[0] = ~0;
1876 } else {
1877 netdev_for_each_mc_addr(ha, netdev) {
1878 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1879 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1880 }
1881 }
1882
1883 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1884 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1885 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1886}
1887
1888static void gmac_write_mac_address(struct net_device *netdev)
1889{
1890 struct gemini_ethernet_port *port = netdev_priv(netdev);
1891 __le32 addr[3];
1892
1893 memset(addr, 0, sizeof(addr));
1894 memcpy(addr, netdev->dev_addr, ETH_ALEN);
1895
1896 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1897 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1898 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1899}
1900
1901static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1902{
1903 struct sockaddr *sa = addr;
1904
1905 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
1906 gmac_write_mac_address(netdev);
1907
1908 return 0;
1909}
1910
1911static void gmac_clear_hw_stats(struct net_device *netdev)
1912{
1913 struct gemini_ethernet_port *port = netdev_priv(netdev);
1914
1915 readl(port->gmac_base + GMAC_IN_DISCARDS);
1916 readl(port->gmac_base + GMAC_IN_ERRORS);
1917 readl(port->gmac_base + GMAC_IN_MCAST);
1918 readl(port->gmac_base + GMAC_IN_BCAST);
1919 readl(port->gmac_base + GMAC_IN_MAC1);
1920 readl(port->gmac_base + GMAC_IN_MAC2);
1921}
1922
1923static void gmac_get_stats64(struct net_device *netdev,
1924 struct rtnl_link_stats64 *stats)
1925{
1926 struct gemini_ethernet_port *port = netdev_priv(netdev);
1927 unsigned int start;
1928
1929 gmac_update_hw_stats(netdev);
1930
1931
1932 do {
1933 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
1934
1935 stats->rx_packets = port->stats.rx_packets;
1936 stats->rx_bytes = port->stats.rx_bytes;
1937 stats->rx_errors = port->stats.rx_errors;
1938 stats->rx_dropped = port->stats.rx_dropped;
1939
1940 stats->rx_length_errors = port->stats.rx_length_errors;
1941 stats->rx_over_errors = port->stats.rx_over_errors;
1942 stats->rx_crc_errors = port->stats.rx_crc_errors;
1943 stats->rx_frame_errors = port->stats.rx_frame_errors;
1944
1945 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
1946
1947
1948 do {
1949 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
1950
1951 stats->tx_errors = port->stats.tx_errors;
1952 stats->tx_packets = port->stats.tx_packets;
1953 stats->tx_bytes = port->stats.tx_bytes;
1954
1955 stats->multicast = port->stats.multicast;
1956 stats->rx_missed_errors = port->stats.rx_missed_errors;
1957 stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1958
1959 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
1960
1961
1962 do {
1963 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
1964
1965 stats->tx_dropped = port->stats.tx_dropped;
1966
1967 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
1968
1969 stats->rx_dropped += stats->rx_missed_errors;
1970}
1971
1972static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1973{
1974 int max_len = gmac_pick_rx_max_len(new_mtu);
1975
1976 if (max_len < 0)
1977 return -EINVAL;
1978
1979 gmac_disable_tx_rx(netdev);
1980
1981 netdev->mtu = new_mtu;
1982 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
1983 CONFIG0_MAXLEN_MASK);
1984
1985 netdev_update_features(netdev);
1986
1987 gmac_enable_tx_rx(netdev);
1988
1989 return 0;
1990}
1991
1992static netdev_features_t gmac_fix_features(struct net_device *netdev,
1993 netdev_features_t features)
1994{
1995 if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1996 features &= ~GMAC_OFFLOAD_FEATURES;
1997
1998 return features;
1999}
2000
2001static int gmac_set_features(struct net_device *netdev,
2002 netdev_features_t features)
2003{
2004 struct gemini_ethernet_port *port = netdev_priv(netdev);
2005 int enable = features & NETIF_F_RXCSUM;
2006 unsigned long flags;
2007 u32 reg;
2008
2009 spin_lock_irqsave(&port->config_lock, flags);
2010
2011 reg = readl(port->gmac_base + GMAC_CONFIG0);
2012 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
2013 writel(reg, port->gmac_base + GMAC_CONFIG0);
2014
2015 spin_unlock_irqrestore(&port->config_lock, flags);
2016 return 0;
2017}
2018
2019static int gmac_get_sset_count(struct net_device *netdev, int sset)
2020{
2021 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
2022}
2023
2024static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2025{
2026 if (stringset != ETH_SS_STATS)
2027 return;
2028
2029 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
2030}
2031
2032static void gmac_get_ethtool_stats(struct net_device *netdev,
2033 struct ethtool_stats *estats, u64 *values)
2034{
2035 struct gemini_ethernet_port *port = netdev_priv(netdev);
2036 unsigned int start;
2037 u64 *p;
2038 int i;
2039
2040 gmac_update_hw_stats(netdev);
2041
2042
2043 do {
2044 p = values;
2045 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
2046
2047 for (i = 0; i < RX_STATS_NUM; i++)
2048 *p++ = port->hw_stats[i];
2049
2050 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
2051 values = p;
2052
2053
2054 do {
2055 p = values;
2056 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
2057
2058 for (i = 0; i < RX_STATUS_NUM; i++)
2059 *p++ = port->rx_stats[i];
2060 for (i = 0; i < RX_CHKSUM_NUM; i++)
2061 *p++ = port->rx_csum_stats[i];
2062 *p++ = port->rx_napi_exits;
2063
2064 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
2065 values = p;
2066
2067
2068 do {
2069 p = values;
2070 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
2071
2072 for (i = 0; i < TX_MAX_FRAGS; i++) {
2073 *values++ = port->tx_frag_stats[i];
2074 port->tx_frag_stats[i] = 0;
2075 }
2076 *values++ = port->tx_frags_linearized;
2077 *values++ = port->tx_hw_csummed;
2078
2079 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
2080}
2081
2082static int gmac_get_ksettings(struct net_device *netdev,
2083 struct ethtool_link_ksettings *cmd)
2084{
2085 if (!netdev->phydev)
2086 return -ENXIO;
2087 phy_ethtool_ksettings_get(netdev->phydev, cmd);
2088
2089 return 0;
2090}
2091
2092static int gmac_set_ksettings(struct net_device *netdev,
2093 const struct ethtool_link_ksettings *cmd)
2094{
2095 if (!netdev->phydev)
2096 return -ENXIO;
2097 return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2098}
2099
2100static int gmac_nway_reset(struct net_device *netdev)
2101{
2102 if (!netdev->phydev)
2103 return -ENXIO;
2104 return phy_start_aneg(netdev->phydev);
2105}
2106
2107static void gmac_get_pauseparam(struct net_device *netdev,
2108 struct ethtool_pauseparam *pparam)
2109{
2110 struct gemini_ethernet_port *port = netdev_priv(netdev);
2111 union gmac_config0 config0;
2112
2113 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2114
2115 pparam->rx_pause = config0.bits.rx_fc_en;
2116 pparam->tx_pause = config0.bits.tx_fc_en;
2117 pparam->autoneg = true;
2118}
2119
2120static void gmac_get_ringparam(struct net_device *netdev,
2121 struct ethtool_ringparam *rp)
2122{
2123 struct gemini_ethernet_port *port = netdev_priv(netdev);
2124 union gmac_config0 config0;
2125
2126 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2127
2128 rp->rx_max_pending = 1 << 15;
2129 rp->rx_mini_max_pending = 0;
2130 rp->rx_jumbo_max_pending = 0;
2131 rp->tx_max_pending = 1 << 15;
2132
2133 rp->rx_pending = 1 << port->rxq_order;
2134 rp->rx_mini_pending = 0;
2135 rp->rx_jumbo_pending = 0;
2136 rp->tx_pending = 1 << port->txq_order;
2137}
2138
2139static int gmac_set_ringparam(struct net_device *netdev,
2140 struct ethtool_ringparam *rp)
2141{
2142 struct gemini_ethernet_port *port = netdev_priv(netdev);
2143 int err = 0;
2144
2145 if (netif_running(netdev))
2146 return -EBUSY;
2147
2148 if (rp->rx_pending) {
2149 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2150 err = geth_resize_freeq(port);
2151 }
2152 if (rp->tx_pending) {
2153 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2154 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2155 }
2156
2157 return err;
2158}
2159
2160static int gmac_get_coalesce(struct net_device *netdev,
2161 struct ethtool_coalesce *ecmd)
2162{
2163 struct gemini_ethernet_port *port = netdev_priv(netdev);
2164
2165 ecmd->rx_max_coalesced_frames = 1;
2166 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2167 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2168
2169 return 0;
2170}
2171
2172static int gmac_set_coalesce(struct net_device *netdev,
2173 struct ethtool_coalesce *ecmd)
2174{
2175 struct gemini_ethernet_port *port = netdev_priv(netdev);
2176
2177 if (ecmd->tx_max_coalesced_frames < 1)
2178 return -EINVAL;
2179 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2180 return -EINVAL;
2181
2182 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2183 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2184
2185 return 0;
2186}
2187
2188static u32 gmac_get_msglevel(struct net_device *netdev)
2189{
2190 struct gemini_ethernet_port *port = netdev_priv(netdev);
2191
2192 return port->msg_enable;
2193}
2194
2195static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2196{
2197 struct gemini_ethernet_port *port = netdev_priv(netdev);
2198
2199 port->msg_enable = level;
2200}
2201
2202static void gmac_get_drvinfo(struct net_device *netdev,
2203 struct ethtool_drvinfo *info)
2204{
2205 strcpy(info->driver, DRV_NAME);
2206 strcpy(info->version, DRV_VERSION);
2207 strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2208}
2209
2210static const struct net_device_ops gmac_351x_ops = {
2211 .ndo_init = gmac_init,
2212 .ndo_uninit = gmac_uninit,
2213 .ndo_open = gmac_open,
2214 .ndo_stop = gmac_stop,
2215 .ndo_start_xmit = gmac_start_xmit,
2216 .ndo_tx_timeout = gmac_tx_timeout,
2217 .ndo_set_rx_mode = gmac_set_rx_mode,
2218 .ndo_set_mac_address = gmac_set_mac_address,
2219 .ndo_get_stats64 = gmac_get_stats64,
2220 .ndo_change_mtu = gmac_change_mtu,
2221 .ndo_fix_features = gmac_fix_features,
2222 .ndo_set_features = gmac_set_features,
2223};
2224
2225static const struct ethtool_ops gmac_351x_ethtool_ops = {
2226 .get_sset_count = gmac_get_sset_count,
2227 .get_strings = gmac_get_strings,
2228 .get_ethtool_stats = gmac_get_ethtool_stats,
2229 .get_link = ethtool_op_get_link,
2230 .get_link_ksettings = gmac_get_ksettings,
2231 .set_link_ksettings = gmac_set_ksettings,
2232 .nway_reset = gmac_nway_reset,
2233 .get_pauseparam = gmac_get_pauseparam,
2234 .get_ringparam = gmac_get_ringparam,
2235 .set_ringparam = gmac_set_ringparam,
2236 .get_coalesce = gmac_get_coalesce,
2237 .set_coalesce = gmac_set_coalesce,
2238 .get_msglevel = gmac_get_msglevel,
2239 .set_msglevel = gmac_set_msglevel,
2240 .get_drvinfo = gmac_get_drvinfo,
2241};
2242
2243static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2244{
2245 unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2246 struct gemini_ethernet_port *port = data;
2247 struct gemini_ethernet *geth;
2248 unsigned long flags;
2249
2250 geth = port->geth;
2251
2252 geth_fill_freeq(geth, true);
2253
2254 spin_lock_irqsave(&geth->irq_lock, flags);
2255
2256 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2257
2258 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2259 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2260 spin_unlock_irqrestore(&geth->irq_lock, flags);
2261
2262 return IRQ_HANDLED;
2263}
2264
2265static irqreturn_t gemini_port_irq(int irq, void *data)
2266{
2267 struct gemini_ethernet_port *port = data;
2268 struct gemini_ethernet *geth;
2269 irqreturn_t ret = IRQ_NONE;
2270 u32 val, en;
2271
2272 geth = port->geth;
2273 spin_lock(&geth->irq_lock);
2274
2275 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2276 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2277
2278 if (val & en & SWFQ_EMPTY_INT_BIT) {
2279
2280
2281
2282
2283 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2284 | GMAC1_RX_OVERRUN_INT_BIT);
2285 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2286 ret = IRQ_WAKE_THREAD;
2287 }
2288
2289 spin_unlock(&geth->irq_lock);
2290
2291 return ret;
2292}
2293
2294static void gemini_port_remove(struct gemini_ethernet_port *port)
2295{
2296 if (port->netdev)
2297 unregister_netdev(port->netdev);
2298 clk_disable_unprepare(port->pclk);
2299 geth_cleanup_freeq(port->geth);
2300}
2301
2302static void gemini_ethernet_init(struct gemini_ethernet *geth)
2303{
2304
2305 if (geth->initialized)
2306 return;
2307 if (geth->port0 && geth->port1)
2308 geth->initialized = true;
2309 else
2310 return;
2311
2312 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2313 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2314 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2315 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2316 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2329 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2330 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2331 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2332 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2333
2334
2335 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2336 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2337 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2338 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2339 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2340
2341
2342 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2343 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2344 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2345 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2346
2347 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2348
2349
2350
2351 geth->freeq_order = 1;
2352}
2353
2354static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2355{
2356 port->mac_addr[0] =
2357 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2358 port->mac_addr[1] =
2359 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2360 port->mac_addr[2] =
2361 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2362}
2363
2364static int gemini_ethernet_port_probe(struct platform_device *pdev)
2365{
2366 char *port_names[2] = { "ethernet0", "ethernet1" };
2367 struct gemini_ethernet_port *port;
2368 struct device *dev = &pdev->dev;
2369 struct gemini_ethernet *geth;
2370 struct net_device *netdev;
2371 struct resource *gmacres;
2372 struct resource *dmares;
2373 struct device *parent;
2374 unsigned int id;
2375 int irq;
2376 int ret;
2377
2378 parent = dev->parent;
2379 geth = dev_get_drvdata(parent);
2380
2381 if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2382 id = 0;
2383 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2384 id = 1;
2385 else
2386 return -ENODEV;
2387
2388 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2389
2390 netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
2391 if (!netdev) {
2392 dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2393 return -ENOMEM;
2394 }
2395
2396 port = netdev_priv(netdev);
2397 SET_NETDEV_DEV(netdev, dev);
2398 port->netdev = netdev;
2399 port->id = id;
2400 port->geth = geth;
2401 port->dev = dev;
2402 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2403
2404
2405 dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2406 if (!dmares) {
2407 dev_err(dev, "no DMA resource\n");
2408 return -ENODEV;
2409 }
2410 port->dma_base = devm_ioremap_resource(dev, dmares);
2411 if (IS_ERR(port->dma_base))
2412 return PTR_ERR(port->dma_base);
2413
2414
2415 gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2416 if (!gmacres) {
2417 dev_err(dev, "no GMAC resource\n");
2418 return -ENODEV;
2419 }
2420 port->gmac_base = devm_ioremap_resource(dev, gmacres);
2421 if (IS_ERR(port->gmac_base))
2422 return PTR_ERR(port->gmac_base);
2423
2424
2425 irq = platform_get_irq(pdev, 0);
2426 if (irq <= 0) {
2427 dev_err(dev, "no IRQ\n");
2428 return irq ? irq : -ENODEV;
2429 }
2430 port->irq = irq;
2431
2432
2433 port->pclk = devm_clk_get(dev, "PCLK");
2434 if (IS_ERR(port->pclk)) {
2435 dev_err(dev, "no PCLK\n");
2436 return PTR_ERR(port->pclk);
2437 }
2438 ret = clk_prepare_enable(port->pclk);
2439 if (ret)
2440 return ret;
2441
2442
2443 gemini_port_save_mac_addr(port);
2444
2445
2446 port->reset = devm_reset_control_get_exclusive(dev, NULL);
2447 if (IS_ERR(port->reset)) {
2448 dev_err(dev, "no reset\n");
2449 return PTR_ERR(port->reset);
2450 }
2451 reset_control_reset(port->reset);
2452 usleep_range(100, 500);
2453
2454
2455 if (!id)
2456 geth->port0 = port;
2457 else
2458 geth->port1 = port;
2459
2460
2461 gemini_ethernet_init(geth);
2462
2463 platform_set_drvdata(pdev, port);
2464
2465
2466 netdev->dev_id = port->id;
2467 netdev->irq = irq;
2468 netdev->netdev_ops = &gmac_351x_ops;
2469 netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2470
2471 spin_lock_init(&port->config_lock);
2472 gmac_clear_hw_stats(netdev);
2473
2474 netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2475 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2476
2477
2478
2479 netdev->min_mtu = ETH_MIN_MTU;
2480 netdev->max_mtu = 10236 - VLAN_ETH_HLEN;
2481
2482 port->freeq_refill = 0;
2483 netif_napi_add(netdev, &port->napi, gmac_napi_poll,
2484 DEFAULT_NAPI_WEIGHT);
2485
2486 if (is_valid_ether_addr((void *)port->mac_addr)) {
2487 memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
2488 } else {
2489 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2490 port->mac_addr[0], port->mac_addr[1],
2491 port->mac_addr[2]);
2492 dev_info(dev, "using a random ethernet address\n");
2493 eth_random_addr(netdev->dev_addr);
2494 }
2495 gmac_write_mac_address(netdev);
2496
2497 ret = devm_request_threaded_irq(port->dev,
2498 port->irq,
2499 gemini_port_irq,
2500 gemini_port_irq_thread,
2501 IRQF_SHARED,
2502 port_names[port->id],
2503 port);
2504 if (ret)
2505 return ret;
2506
2507 ret = register_netdev(netdev);
2508 if (!ret) {
2509 netdev_info(netdev,
2510 "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
2511 port->irq, &dmares->start,
2512 &gmacres->start);
2513 ret = gmac_setup_phy(netdev);
2514 if (ret)
2515 netdev_info(netdev,
2516 "PHY init failed, deferring to ifup time\n");
2517 return 0;
2518 }
2519
2520 port->netdev = NULL;
2521 free_netdev(netdev);
2522 return ret;
2523}
2524
2525static int gemini_ethernet_port_remove(struct platform_device *pdev)
2526{
2527 struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2528
2529 gemini_port_remove(port);
2530 return 0;
2531}
2532
2533static const struct of_device_id gemini_ethernet_port_of_match[] = {
2534 {
2535 .compatible = "cortina,gemini-ethernet-port",
2536 },
2537 {},
2538};
2539MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2540
2541static struct platform_driver gemini_ethernet_port_driver = {
2542 .driver = {
2543 .name = "gemini-ethernet-port",
2544 .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
2545 },
2546 .probe = gemini_ethernet_port_probe,
2547 .remove = gemini_ethernet_port_remove,
2548};
2549
2550static int gemini_ethernet_probe(struct platform_device *pdev)
2551{
2552 struct device *dev = &pdev->dev;
2553 struct gemini_ethernet *geth;
2554 unsigned int retry = 5;
2555 struct resource *res;
2556 u32 val;
2557
2558
2559 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2560 if (!geth)
2561 return -ENOMEM;
2562 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2563 if (!res)
2564 return -ENODEV;
2565 geth->base = devm_ioremap_resource(dev, res);
2566 if (IS_ERR(geth->base))
2567 return PTR_ERR(geth->base);
2568 geth->dev = dev;
2569
2570
2571 do {
2572 udelay(2);
2573 val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2574 barrier();
2575 } while (!val && --retry);
2576 if (!retry) {
2577 dev_err(dev, "failed to reset ethernet\n");
2578 return -EIO;
2579 }
2580 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2581 (val >> 4) & 0xFFFU, val & 0xFU);
2582
2583 spin_lock_init(&geth->irq_lock);
2584 spin_lock_init(&geth->freeq_lock);
2585
2586
2587 platform_set_drvdata(pdev, geth);
2588
2589
2590 return devm_of_platform_populate(dev);
2591}
2592
2593static int gemini_ethernet_remove(struct platform_device *pdev)
2594{
2595 struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2596
2597 geth_cleanup_freeq(geth);
2598 geth->initialized = false;
2599
2600 return 0;
2601}
2602
2603static const struct of_device_id gemini_ethernet_of_match[] = {
2604 {
2605 .compatible = "cortina,gemini-ethernet",
2606 },
2607 {},
2608};
2609MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2610
2611static struct platform_driver gemini_ethernet_driver = {
2612 .driver = {
2613 .name = DRV_NAME,
2614 .of_match_table = of_match_ptr(gemini_ethernet_of_match),
2615 },
2616 .probe = gemini_ethernet_probe,
2617 .remove = gemini_ethernet_remove,
2618};
2619
2620static int __init gemini_ethernet_module_init(void)
2621{
2622 int ret;
2623
2624 ret = platform_driver_register(&gemini_ethernet_port_driver);
2625 if (ret)
2626 return ret;
2627
2628 ret = platform_driver_register(&gemini_ethernet_driver);
2629 if (ret) {
2630 platform_driver_unregister(&gemini_ethernet_port_driver);
2631 return ret;
2632 }
2633
2634 return 0;
2635}
2636module_init(gemini_ethernet_module_init);
2637
2638static void __exit gemini_ethernet_module_exit(void)
2639{
2640 platform_driver_unregister(&gemini_ethernet_driver);
2641 platform_driver_unregister(&gemini_ethernet_port_driver);
2642}
2643module_exit(gemini_ethernet_module_exit);
2644
2645MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2646MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2647MODULE_LICENSE("GPL");
2648MODULE_ALIAS("platform:" DRV_NAME);
2649