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19#ifndef __GIANFAR_H
20#define __GIANFAR_H
21
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/spinlock.h>
33#include <linux/mm.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <linux/uaccess.h>
40#include <linux/module.h>
41#include <linux/crc32.h>
42#include <linux/workqueue.h>
43#include <linux/ethtool.h>
44
45struct ethtool_flow_spec_container {
46 struct ethtool_rx_flow_spec fs;
47 struct list_head list;
48};
49
50struct ethtool_rx_list {
51 struct list_head list;
52 unsigned int count;
53};
54
55
56#define GFAR_DEV_WEIGHT 64
57
58
59#define GMAC_FCB_LEN 8
60
61
62#define GMAC_TXPAL_LEN 16
63
64
65#define DEFAULT_PADDING 2
66
67
68#define RXBUF_ALIGNMENT 64
69
70#define PHY_INIT_TIMEOUT 100000
71
72#define DRV_NAME "gfar-enet"
73extern const char gfar_driver_version[];
74
75
76#define MAX_TX_QS 0x8
77#define MAX_RX_QS 0x8
78
79
80#define MAXGROUPS 0x2
81
82
83#define DEFAULT_TX_RING_SIZE 256
84#define DEFAULT_RX_RING_SIZE 256
85
86#define GFAR_RX_BUFF_ALLOC 16
87
88#define GFAR_RX_MAX_RING_SIZE 256
89#define GFAR_TX_MAX_RING_SIZE 256
90
91#define GFAR_MAX_FIFO_THRESHOLD 511
92#define GFAR_MAX_FIFO_STARVE 511
93#define GFAR_MAX_FIFO_STARVE_OFF 511
94
95#define FBTHR_SHIFT 24
96#define DEFAULT_RX_LFC_THR 16
97#define DEFAULT_LFC_PTVVAL 4
98
99
100#define GFAR_RXB_SIZE roundup(1536 + 8, 64)
101#define GFAR_SKBFRAG_SIZE (RXBUF_ALIGNMENT + GFAR_RXB_SIZE \
102 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
103#define GFAR_RXB_TRUESIZE 2048
104
105#define TX_RING_MOD_MASK(size) (size-1)
106#define RX_RING_MOD_MASK(size) (size-1)
107#define GFAR_JUMBO_FRAME_SIZE 9600
108
109#define DEFAULT_FIFO_TX_THR 0x100
110#define DEFAULT_FIFO_TX_STARVE 0x40
111#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
112#define DEFAULT_BD_STASH 1
113#define DEFAULT_STASH_LENGTH 96
114#define DEFAULT_STASH_INDEX 0
115
116
117#define GFAR_EM_NUM 15
118
119
120
121
122
123
124
125
126
127
128
129#define GFAR_GBIT_TIME 512
130#define GFAR_100_TIME 2560
131#define GFAR_10_TIME 25600
132
133#define DEFAULT_TX_COALESCE 1
134#define DEFAULT_TXCOUNT 16
135#define DEFAULT_TXTIME 21
136
137#define DEFAULT_RXTIME 21
138
139#define DEFAULT_RX_COALESCE 0
140#define DEFAULT_RXCOUNT 0
141
142#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
143 | SUPPORTED_10baseT_Full \
144 | SUPPORTED_100baseT_Half \
145 | SUPPORTED_100baseT_Full \
146 | SUPPORTED_Autoneg \
147 | SUPPORTED_MII)
148
149#define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full
150
151
152#define MII_TBICON 0x11
153
154
155#define TBICON_CLK_SELECT 0x0020
156
157
158#define MACCFG1_SOFT_RESET 0x80000000
159#define MACCFG1_RESET_RX_MC 0x00080000
160#define MACCFG1_RESET_TX_MC 0x00040000
161#define MACCFG1_RESET_RX_FUN 0x00020000
162#define MACCFG1_RESET_TX_FUN 0x00010000
163#define MACCFG1_LOOPBACK 0x00000100
164#define MACCFG1_RX_FLOW 0x00000020
165#define MACCFG1_TX_FLOW 0x00000010
166#define MACCFG1_SYNCD_RX_EN 0x00000008
167#define MACCFG1_RX_EN 0x00000004
168#define MACCFG1_SYNCD_TX_EN 0x00000002
169#define MACCFG1_TX_EN 0x00000001
170
171#define MACCFG2_INIT_SETTINGS 0x00007205
172#define MACCFG2_FULL_DUPLEX 0x00000001
173#define MACCFG2_IF 0x00000300
174#define MACCFG2_MII 0x00000100
175#define MACCFG2_GMII 0x00000200
176#define MACCFG2_HUGEFRAME 0x00000020
177#define MACCFG2_LENGTHCHECK 0x00000010
178#define MACCFG2_MPEN 0x00000008
179
180#define ECNTRL_FIFM 0x00008000
181#define ECNTRL_INIT_SETTINGS 0x00001000
182#define ECNTRL_TBI_MODE 0x00000020
183#define ECNTRL_REDUCED_MODE 0x00000010
184#define ECNTRL_R100 0x00000008
185#define ECNTRL_REDUCED_MII_MODE 0x00000004
186#define ECNTRL_SGMII_MODE 0x00000002
187
188#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
189
190#define MINFLR_INIT_SETTINGS 0x00000040
191
192
193#define TQUEUE_EN0 0x00008000
194#define TQUEUE_EN1 0x00004000
195#define TQUEUE_EN2 0x00002000
196#define TQUEUE_EN3 0x00001000
197#define TQUEUE_EN4 0x00000800
198#define TQUEUE_EN5 0x00000400
199#define TQUEUE_EN6 0x00000200
200#define TQUEUE_EN7 0x00000100
201#define TQUEUE_EN_ALL 0x0000FF00
202
203#define TR03WT_WT0_MASK 0xFF000000
204#define TR03WT_WT1_MASK 0x00FF0000
205#define TR03WT_WT2_MASK 0x0000FF00
206#define TR03WT_WT3_MASK 0x000000FF
207
208#define TR47WT_WT4_MASK 0xFF000000
209#define TR47WT_WT5_MASK 0x00FF0000
210#define TR47WT_WT6_MASK 0x0000FF00
211#define TR47WT_WT7_MASK 0x000000FF
212
213
214#define RQUEUE_EX0 0x00800000
215#define RQUEUE_EX1 0x00400000
216#define RQUEUE_EX2 0x00200000
217#define RQUEUE_EX3 0x00100000
218#define RQUEUE_EX4 0x00080000
219#define RQUEUE_EX5 0x00040000
220#define RQUEUE_EX6 0x00020000
221#define RQUEUE_EX7 0x00010000
222#define RQUEUE_EX_ALL 0x00FF0000
223
224#define RQUEUE_EN0 0x00000080
225#define RQUEUE_EN1 0x00000040
226#define RQUEUE_EN2 0x00000020
227#define RQUEUE_EN3 0x00000010
228#define RQUEUE_EN4 0x00000008
229#define RQUEUE_EN5 0x00000004
230#define RQUEUE_EN6 0x00000002
231#define RQUEUE_EN7 0x00000001
232#define RQUEUE_EN_ALL 0x000000FF
233
234
235#define DMACTRL_INIT_SETTINGS 0x000000c3
236#define DMACTRL_GRS 0x00000010
237#define DMACTRL_GTS 0x00000008
238
239#define TSTAT_CLEAR_THALT_ALL 0xFF000000
240#define TSTAT_CLEAR_THALT 0x80000000
241#define TSTAT_CLEAR_THALT0 0x80000000
242#define TSTAT_CLEAR_THALT1 0x40000000
243#define TSTAT_CLEAR_THALT2 0x20000000
244#define TSTAT_CLEAR_THALT3 0x10000000
245#define TSTAT_CLEAR_THALT4 0x08000000
246#define TSTAT_CLEAR_THALT5 0x04000000
247#define TSTAT_CLEAR_THALT6 0x02000000
248#define TSTAT_CLEAR_THALT7 0x01000000
249
250
251#define IC_ICEN 0x80000000
252#define IC_ICFT_MASK 0x1fe00000
253#define IC_ICFT_SHIFT 21
254#define mk_ic_icft(x) \
255 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
256#define IC_ICTT_MASK 0x0000ffff
257#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
258
259#define mk_ic_value(count, time) (IC_ICEN | \
260 mk_ic_icft(count) | \
261 mk_ic_ictt(time))
262#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
263 IC_ICFT_SHIFT)
264#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
265
266#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
267#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
268
269#define skip_bd(bdp, stride, base, ring_size) ({ \
270 typeof(bdp) new_bd = (bdp) + (stride); \
271 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
272
273#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
274
275#define RCTRL_TS_ENABLE 0x01000000
276#define RCTRL_PAL_MASK 0x001f0000
277#define RCTRL_LFC 0x00004000
278#define RCTRL_VLEX 0x00002000
279#define RCTRL_FILREN 0x00001000
280#define RCTRL_GHTX 0x00000400
281#define RCTRL_IPCSEN 0x00000200
282#define RCTRL_TUCSEN 0x00000100
283#define RCTRL_PRSDEP_MASK 0x000000c0
284#define RCTRL_PRSDEP_INIT 0x000000c0
285#define RCTRL_PRSFM 0x00000020
286#define RCTRL_PROM 0x00000008
287#define RCTRL_EMEN 0x00000002
288#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
289 RCTRL_TUCSEN | RCTRL_FILREN)
290#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
291 RCTRL_PRSDEP_INIT)
292#define RCTRL_EXTHASH (RCTRL_GHTX)
293#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
294#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
295
296
297#define RSTAT_CLEAR_RHALT 0x00800000
298#define RSTAT_CLEAR_RXF0 0x00000080
299#define RSTAT_RXF_MASK 0x000000ff
300
301#define TCTRL_IPCSEN 0x00004000
302#define TCTRL_TUCSEN 0x00002000
303#define TCTRL_VLINS 0x00001000
304#define TCTRL_THDF 0x00000800
305#define TCTRL_RFCPAUSE 0x00000010
306#define TCTRL_TFCPAUSE 0x00000008
307#define TCTRL_TXSCHED_MASK 0x00000006
308#define TCTRL_TXSCHED_INIT 0x00000000
309
310#define TCTRL_TXSCHED_PRIO 0x00000002
311
312#define TCTRL_TXSCHED_WRRS 0x00000004
313
314
315
316
317#define DEFAULT_WRRS_WEIGHT 0x18181818
318
319#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
320
321#define IEVENT_INIT_CLEAR 0xffffffff
322#define IEVENT_BABR 0x80000000
323#define IEVENT_RXC 0x40000000
324#define IEVENT_BSY 0x20000000
325#define IEVENT_EBERR 0x10000000
326#define IEVENT_MSRO 0x04000000
327#define IEVENT_GTSC 0x02000000
328#define IEVENT_BABT 0x01000000
329#define IEVENT_TXC 0x00800000
330#define IEVENT_TXE 0x00400000
331#define IEVENT_TXB 0x00200000
332#define IEVENT_TXF 0x00100000
333#define IEVENT_LC 0x00040000
334#define IEVENT_CRL 0x00020000
335#define IEVENT_XFUN 0x00010000
336#define IEVENT_RXB0 0x00008000
337#define IEVENT_MAG 0x00000800
338#define IEVENT_GRSC 0x00000100
339#define IEVENT_RXF0 0x00000080
340#define IEVENT_FGPI 0x00000010
341#define IEVENT_FIR 0x00000008
342#define IEVENT_FIQ 0x00000004
343#define IEVENT_DPE 0x00000002
344#define IEVENT_PERR 0x00000001
345#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
346#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
347#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
348#define IEVENT_ERR_MASK \
349(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
350 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
351 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
352 | IEVENT_MAG | IEVENT_BABR)
353
354#define IMASK_INIT_CLEAR 0x00000000
355#define IMASK_BABR 0x80000000
356#define IMASK_RXC 0x40000000
357#define IMASK_BSY 0x20000000
358#define IMASK_EBERR 0x10000000
359#define IMASK_MSRO 0x04000000
360#define IMASK_GTSC 0x02000000
361#define IMASK_BABT 0x01000000
362#define IMASK_TXC 0x00800000
363#define IMASK_TXEEN 0x00400000
364#define IMASK_TXBEN 0x00200000
365#define IMASK_TXFEN 0x00100000
366#define IMASK_LC 0x00040000
367#define IMASK_CRL 0x00020000
368#define IMASK_XFUN 0x00010000
369#define IMASK_RXB0 0x00008000
370#define IMASK_MAG 0x00000800
371#define IMASK_GRSC 0x00000100
372#define IMASK_RXFEN0 0x00000080
373#define IMASK_FGPI 0x00000010
374#define IMASK_FIR 0x00000008
375#define IMASK_FIQ 0x00000004
376#define IMASK_DPE 0x00000002
377#define IMASK_PERR 0x00000001
378#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
379 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
380 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
381 | IMASK_PERR)
382#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
383#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
384
385#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
386#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
387
388
389#define FIFO_TX_THR_MASK 0x01ff
390#define FIFO_TX_STARVE_MASK 0x01ff
391#define FIFO_TX_STARVE_OFF_MASK 0x01ff
392
393
394
395
396#define ATTR_BDSTASH 0x00000800
397
398#define ATTR_BUFSTASH 0x00004000
399
400#define ATTR_SNOOPING 0x000000c0
401#define ATTR_INIT_SETTINGS ATTR_SNOOPING
402
403#define ATTRELI_INIT_SETTINGS 0x0
404#define ATTRELI_EL_MASK 0x3fff0000
405#define ATTRELI_EL(x) (x << 16)
406#define ATTRELI_EI_MASK 0x00003fff
407#define ATTRELI_EI(x) (x)
408
409#define BD_LFLAG(flags) ((flags) << 16)
410#define BD_LENGTH_MASK 0x0000ffff
411
412#define FPR_FILER_MASK 0xFFFFFFFF
413#define MAX_FILER_IDX 0xFF
414
415
416
417#define DEFAULT_8RXQ_RIR0 0x05397700
418
419#define DEFAULT_2RXQ_RIR0 0x04104100
420
421
422#define RQFCR_GPI 0x80000000
423#define RQFCR_HASHTBL_Q 0x00000000
424#define RQFCR_HASHTBL_0 0x00020000
425#define RQFCR_HASHTBL_1 0x00040000
426#define RQFCR_HASHTBL_2 0x00060000
427#define RQFCR_HASHTBL_3 0x00080000
428#define RQFCR_HASH 0x00010000
429#define RQFCR_QUEUE 0x0000FC00
430#define RQFCR_CLE 0x00000200
431#define RQFCR_RJE 0x00000100
432#define RQFCR_AND 0x00000080
433#define RQFCR_CMP_EXACT 0x00000000
434#define RQFCR_CMP_MATCH 0x00000020
435#define RQFCR_CMP_NOEXACT 0x00000040
436#define RQFCR_CMP_NOMATCH 0x00000060
437
438
439#define RQFCR_PID_MASK 0x00000000
440#define RQFCR_PID_PARSE 0x00000001
441#define RQFCR_PID_ARB 0x00000002
442#define RQFCR_PID_DAH 0x00000003
443#define RQFCR_PID_DAL 0x00000004
444#define RQFCR_PID_SAH 0x00000005
445#define RQFCR_PID_SAL 0x00000006
446#define RQFCR_PID_ETY 0x00000007
447#define RQFCR_PID_VID 0x00000008
448#define RQFCR_PID_PRI 0x00000009
449#define RQFCR_PID_TOS 0x0000000A
450#define RQFCR_PID_L4P 0x0000000B
451#define RQFCR_PID_DIA 0x0000000C
452#define RQFCR_PID_SIA 0x0000000D
453#define RQFCR_PID_DPT 0x0000000E
454#define RQFCR_PID_SPT 0x0000000F
455
456
457#define RQFPR_HDR_GE_512 0x00200000
458#define RQFPR_LERR 0x00100000
459#define RQFPR_RAR 0x00080000
460#define RQFPR_RARQ 0x00040000
461#define RQFPR_AR 0x00020000
462#define RQFPR_ARQ 0x00010000
463#define RQFPR_EBC 0x00008000
464#define RQFPR_VLN 0x00004000
465#define RQFPR_CFI 0x00002000
466#define RQFPR_JUM 0x00001000
467#define RQFPR_IPF 0x00000800
468#define RQFPR_FIF 0x00000400
469#define RQFPR_IPV4 0x00000200
470#define RQFPR_IPV6 0x00000100
471#define RQFPR_ICC 0x00000080
472#define RQFPR_ICV 0x00000040
473#define RQFPR_TCP 0x00000020
474#define RQFPR_UDP 0x00000010
475#define RQFPR_TUC 0x00000008
476#define RQFPR_TUV 0x00000004
477#define RQFPR_PER 0x00000002
478#define RQFPR_EER 0x00000001
479
480
481#define TXBD_READY 0x8000
482#define TXBD_PADCRC 0x4000
483#define TXBD_WRAP 0x2000
484#define TXBD_INTERRUPT 0x1000
485#define TXBD_LAST 0x0800
486#define TXBD_CRC 0x0400
487#define TXBD_DEF 0x0200
488#define TXBD_HUGEFRAME 0x0080
489#define TXBD_LATECOLLISION 0x0080
490#define TXBD_RETRYLIMIT 0x0040
491#define TXBD_RETRYCOUNTMASK 0x003c
492#define TXBD_UNDERRUN 0x0002
493#define TXBD_TOE 0x0002
494
495
496#define TXFCB_VLN 0x80
497#define TXFCB_IP 0x40
498#define TXFCB_IP6 0x20
499#define TXFCB_TUP 0x10
500#define TXFCB_UDP 0x08
501#define TXFCB_CIP 0x04
502#define TXFCB_CTU 0x02
503#define TXFCB_NPH 0x01
504#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
505
506
507#define RXBD_EMPTY 0x8000
508#define RXBD_RO1 0x4000
509#define RXBD_WRAP 0x2000
510#define RXBD_INTERRUPT 0x1000
511#define RXBD_LAST 0x0800
512#define RXBD_FIRST 0x0400
513#define RXBD_MISS 0x0100
514#define RXBD_BROADCAST 0x0080
515#define RXBD_MULTICAST 0x0040
516#define RXBD_LARGE 0x0020
517#define RXBD_NONOCTET 0x0010
518#define RXBD_SHORT 0x0008
519#define RXBD_CRCERR 0x0004
520#define RXBD_OVERRUN 0x0002
521#define RXBD_TRUNCATED 0x0001
522#define RXBD_STATS 0x01ff
523#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
524 | RXBD_CRCERR | RXBD_OVERRUN \
525 | RXBD_TRUNCATED)
526
527
528#define RXFCB_VLN 0x8000
529#define RXFCB_IP 0x4000
530#define RXFCB_IP6 0x2000
531#define RXFCB_TUP 0x1000
532#define RXFCB_CIP 0x0800
533#define RXFCB_CTU 0x0400
534#define RXFCB_EIP 0x0200
535#define RXFCB_ETU 0x0100
536#define RXFCB_CSUM_MASK 0x0f00
537#define RXFCB_PERR_MASK 0x000c
538#define RXFCB_PERR_BADL3 0x0008
539
540#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6)
541
542#define GFAR_WOL_MAGIC 0x00000001
543#define GFAR_WOL_FILER_UCAST 0x00000002
544
545struct txbd8
546{
547 union {
548 struct {
549 __be16 status;
550 __be16 length;
551 };
552 __be32 lstatus;
553 };
554 __be32 bufPtr;
555};
556
557struct txfcb {
558 u8 flags;
559 u8 ptp;
560 u8 l4os;
561 u8 l3os;
562 __be16 phcs;
563 __be16 vlctl;
564};
565
566struct rxbd8
567{
568 union {
569 struct {
570 __be16 status;
571 __be16 length;
572 };
573 __be32 lstatus;
574 };
575 __be32 bufPtr;
576};
577
578struct rxfcb {
579 __be16 flags;
580 u8 rq;
581 u8 pro;
582 u16 reserved;
583 __be16 vlctl;
584};
585
586struct gianfar_skb_cb {
587 unsigned int bytes_sent;
588};
589
590#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
591
592struct rmon_mib
593{
594 u32 tr64;
595 u32 tr127;
596 u32 tr255;
597 u32 tr511;
598 u32 tr1k;
599 u32 trmax;
600 u32 trmgv;
601 u32 rbyt;
602 u32 rpkt;
603 u32 rfcs;
604 u32 rmca;
605 u32 rbca;
606 u32 rxcf;
607 u32 rxpf;
608 u32 rxuo;
609 u32 raln;
610 u32 rflr;
611 u32 rcde;
612 u32 rcse;
613 u32 rund;
614 u32 rovr;
615 u32 rfrg;
616 u32 rjbr;
617 u32 rdrp;
618 u32 tbyt;
619 u32 tpkt;
620 u32 tmca;
621 u32 tbca;
622 u32 txpf;
623 u32 tdfr;
624 u32 tedf;
625 u32 tscl;
626 u32 tmcl;
627 u32 tlcl;
628 u32 txcl;
629 u32 tncl;
630 u8 res1[4];
631 u32 tdrp;
632 u32 tjbr;
633 u32 tfcs;
634 u32 txcf;
635 u32 tovr;
636 u32 tund;
637 u32 tfrg;
638 u32 car1;
639 u32 car2;
640 u32 cam1;
641 u32 cam2;
642};
643
644struct gfar_extra_stats {
645 atomic64_t rx_alloc_err;
646 atomic64_t rx_large;
647 atomic64_t rx_short;
648 atomic64_t rx_nonoctet;
649 atomic64_t rx_crcerr;
650 atomic64_t rx_overrun;
651 atomic64_t rx_bsy;
652 atomic64_t rx_babr;
653 atomic64_t rx_trunc;
654 atomic64_t eberr;
655 atomic64_t tx_babt;
656 atomic64_t tx_underrun;
657 atomic64_t tx_timeout;
658};
659
660#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
661#define GFAR_EXTRA_STATS_LEN \
662 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
663
664
665#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
666
667struct gfar {
668 u32 tsec_id;
669 u32 tsec_id2;
670 u8 res1[8];
671 u32 ievent;
672 u32 imask;
673 u32 edis;
674 u32 emapg;
675 u32 ecntrl;
676 u32 minflr;
677 u32 ptv;
678 u32 dmactrl;
679 u32 tbipa;
680 u8 res2[28];
681 u32 fifo_rx_pause;
682
683 u32 fifo_rx_pause_shutoff;
684
685 u32 fifo_rx_alarm;
686
687 u32 fifo_rx_alarm_shutoff;
688
689 u8 res3[44];
690 u32 fifo_tx_thr;
691 u8 res4[8];
692 u32 fifo_tx_starve;
693 u32 fifo_tx_starve_shutoff;
694 u8 res5[96];
695 u32 tctrl;
696 u32 tstat;
697 u32 dfvlan;
698 u32 tbdlen;
699 u32 txic;
700 u32 tqueue;
701 u8 res7[40];
702 u32 tr03wt;
703 u32 tr47wt;
704 u8 res8[52];
705 u32 tbdbph;
706 u8 res9a[4];
707 u32 tbptr0;
708 u8 res9b[4];
709 u32 tbptr1;
710 u8 res9c[4];
711 u32 tbptr2;
712 u8 res9d[4];
713 u32 tbptr3;
714 u8 res9e[4];
715 u32 tbptr4;
716 u8 res9f[4];
717 u32 tbptr5;
718 u8 res9g[4];
719 u32 tbptr6;
720 u8 res9h[4];
721 u32 tbptr7;
722 u8 res9[64];
723 u32 tbaseh;
724 u32 tbase0;
725 u8 res10a[4];
726 u32 tbase1;
727 u8 res10b[4];
728 u32 tbase2;
729 u8 res10c[4];
730 u32 tbase3;
731 u8 res10d[4];
732 u32 tbase4;
733 u8 res10e[4];
734 u32 tbase5;
735 u8 res10f[4];
736 u32 tbase6;
737 u8 res10g[4];
738 u32 tbase7;
739 u8 res10[192];
740 u32 rctrl;
741 u32 rstat;
742 u8 res12[8];
743 u32 rxic;
744 u32 rqueue;
745 u32 rir0;
746 u32 rir1;
747 u32 rir2;
748 u32 rir3;
749 u8 res13[8];
750 u32 rbifx;
751 u32 rqfar;
752 u32 rqfcr;
753 u32 rqfpr;
754 u32 mrblr;
755 u8 res14[56];
756 u32 rbdbph;
757 u8 res15a[4];
758 u32 rbptr0;
759 u8 res15b[4];
760 u32 rbptr1;
761 u8 res15c[4];
762 u32 rbptr2;
763 u8 res15d[4];
764 u32 rbptr3;
765 u8 res15e[4];
766 u32 rbptr4;
767 u8 res15f[4];
768 u32 rbptr5;
769 u8 res15g[4];
770 u32 rbptr6;
771 u8 res15h[4];
772 u32 rbptr7;
773 u8 res16[64];
774 u32 rbaseh;
775 u32 rbase0;
776 u8 res17a[4];
777 u32 rbase1;
778 u8 res17b[4];
779 u32 rbase2;
780 u8 res17c[4];
781 u32 rbase3;
782 u8 res17d[4];
783 u32 rbase4;
784 u8 res17e[4];
785 u32 rbase5;
786 u8 res17f[4];
787 u32 rbase6;
788 u8 res17g[4];
789 u32 rbase7;
790 u8 res17[192];
791 u32 maccfg1;
792 u32 maccfg2;
793 u32 ipgifg;
794 u32 hafdup;
795 u32 maxfrm;
796 u8 res18[12];
797 u8 gfar_mii_regs[24];
798 u32 ifctrl;
799 u32 ifstat;
800 u32 macstnaddr1;
801 u32 macstnaddr2;
802 u32 mac01addr1;
803 u32 mac01addr2;
804 u32 mac02addr1;
805 u32 mac02addr2;
806 u32 mac03addr1;
807 u32 mac03addr2;
808 u32 mac04addr1;
809 u32 mac04addr2;
810 u32 mac05addr1;
811 u32 mac05addr2;
812 u32 mac06addr1;
813 u32 mac06addr2;
814 u32 mac07addr1;
815 u32 mac07addr2;
816 u32 mac08addr1;
817 u32 mac08addr2;
818 u32 mac09addr1;
819 u32 mac09addr2;
820 u32 mac10addr1;
821 u32 mac10addr2;
822 u32 mac11addr1;
823 u32 mac11addr2;
824 u32 mac12addr1;
825 u32 mac12addr2;
826 u32 mac13addr1;
827 u32 mac13addr2;
828 u32 mac14addr1;
829 u32 mac14addr2;
830 u32 mac15addr1;
831 u32 mac15addr2;
832 u8 res20[192];
833 struct rmon_mib rmon;
834 u32 rrej;
835 u8 res21[188];
836 u32 igaddr0;
837 u32 igaddr1;
838 u32 igaddr2;
839 u32 igaddr3;
840 u32 igaddr4;
841 u32 igaddr5;
842 u32 igaddr6;
843 u32 igaddr7;
844 u8 res22[96];
845 u32 gaddr0;
846 u32 gaddr1;
847 u32 gaddr2;
848 u32 gaddr3;
849 u32 gaddr4;
850 u32 gaddr5;
851 u32 gaddr6;
852 u32 gaddr7;
853 u8 res23a[352];
854 u32 fifocfg;
855 u8 res23b[252];
856 u8 res23c[248];
857 u32 attr;
858 u32 attreli;
859 u32 rqprm0;
860 u32 rqprm1;
861 u32 rqprm2;
862 u32 rqprm3;
863 u32 rqprm4;
864 u32 rqprm5;
865 u32 rqprm6;
866 u32 rqprm7;
867 u8 res24[36];
868 u32 rfbptr0;
869 u8 res24a[4];
870 u32 rfbptr1;
871 u8 res24b[4];
872 u32 rfbptr2;
873 u8 res24c[4];
874 u32 rfbptr3;
875 u8 res24d[4];
876 u32 rfbptr4;
877 u8 res24e[4];
878 u32 rfbptr5;
879 u8 res24f[4];
880 u32 rfbptr6;
881 u8 res24g[4];
882 u32 rfbptr7;
883 u8 res24h[4];
884 u8 res24x[556];
885 u32 isrg0;
886 u32 isrg1;
887 u32 isrg2;
888 u32 isrg3;
889 u8 res25[16];
890 u32 rxic0;
891 u32 rxic1;
892 u32 rxic2;
893 u32 rxic3;
894 u32 rxic4;
895 u32 rxic5;
896 u32 rxic6;
897 u32 rxic7;
898 u8 res26[32];
899 u32 txic0;
900 u32 txic1;
901 u32 txic2;
902 u32 txic3;
903 u32 txic4;
904 u32 txic5;
905 u32 txic6;
906 u32 txic7;
907 u8 res27[208];
908};
909
910
911#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
912#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
913#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
914#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
915#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
916#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
917#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
918#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
919#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
920#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
921#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
922#define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000
923#define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000
924
925#if (MAXGROUPS == 2)
926#define DEFAULT_MAPPING 0xAA
927#else
928#define DEFAULT_MAPPING 0xFF
929#endif
930
931#define ISRG_RR0 0x80000000
932#define ISRG_TR0 0x00800000
933
934
935
936
937
938
939enum {
940 SQ_SG_MODE = 0,
941 MQ_MG_MODE
942};
943
944
945
946
947
948
949
950
951
952
953
954
955enum gfar_poll_mode {
956 GFAR_SQ_POLLING = 0,
957 GFAR_MQ_POLLING
958};
959
960
961
962
963struct tx_q_stats {
964 unsigned long tx_packets;
965 unsigned long tx_bytes;
966};
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988struct gfar_priv_tx_q {
989
990 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
991 struct txbd8 *tx_bd_base;
992 struct txbd8 *cur_tx;
993 unsigned int num_txbdfree;
994 unsigned short skb_curtx;
995 unsigned short tx_ring_size;
996 struct tx_q_stats stats;
997 struct gfar_priv_grp *grp;
998
999 struct net_device *dev;
1000 struct sk_buff **tx_skbuff;
1001 struct txbd8 *dirty_tx;
1002 unsigned short skb_dirtytx;
1003 unsigned short qindex;
1004
1005 unsigned int txcoalescing;
1006 unsigned long txic;
1007 dma_addr_t tx_bd_dma_base;
1008};
1009
1010
1011
1012
1013struct rx_q_stats {
1014 unsigned long rx_packets;
1015 unsigned long rx_bytes;
1016 unsigned long rx_dropped;
1017};
1018
1019struct gfar_rx_buff {
1020 dma_addr_t dma;
1021 struct page *page;
1022 unsigned int page_offset;
1023};
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038struct gfar_priv_rx_q {
1039 struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
1040 struct rxbd8 *rx_bd_base;
1041 struct net_device *ndev;
1042 struct device *dev;
1043 u16 rx_ring_size;
1044 u16 qindex;
1045 struct gfar_priv_grp *grp;
1046 u16 next_to_clean;
1047 u16 next_to_use;
1048 u16 next_to_alloc;
1049 struct sk_buff *skb;
1050 struct rx_q_stats stats;
1051 u32 __iomem *rfbptr;
1052 unsigned char rxcoalescing;
1053 unsigned long rxic;
1054 dma_addr_t rx_bd_dma_base;
1055};
1056
1057enum gfar_irqinfo_id {
1058 GFAR_TX = 0,
1059 GFAR_RX = 1,
1060 GFAR_ER = 2,
1061 GFAR_NUM_IRQS = 3
1062};
1063
1064struct gfar_irqinfo {
1065 unsigned int irq;
1066 char name[GFAR_INT_NAME_MAX];
1067};
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077struct gfar_priv_grp {
1078 spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1079 struct napi_struct napi_rx;
1080 struct napi_struct napi_tx;
1081 struct gfar __iomem *regs;
1082 struct gfar_priv_tx_q *tx_queue;
1083 struct gfar_priv_rx_q *rx_queue;
1084 unsigned int tstat;
1085 unsigned int rstat;
1086
1087 struct gfar_private *priv;
1088 unsigned long num_tx_queues;
1089 unsigned long tx_bit_map;
1090 unsigned long num_rx_queues;
1091 unsigned long rx_bit_map;
1092
1093 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1094};
1095
1096#define gfar_irq(grp, ID) \
1097 ((grp)->irqinfo[GFAR_##ID])
1098
1099enum gfar_errata {
1100 GFAR_ERRATA_74 = 0x01,
1101 GFAR_ERRATA_76 = 0x02,
1102 GFAR_ERRATA_A002 = 0x04,
1103 GFAR_ERRATA_12 = 0x08,
1104};
1105
1106enum gfar_dev_state {
1107 GFAR_DOWN = 1,
1108 GFAR_RESETTING
1109};
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120struct gfar_private {
1121 struct device *dev;
1122 struct net_device *ndev;
1123 enum gfar_errata errata;
1124
1125 u16 uses_rxfcb;
1126 u16 padding;
1127 u32 device_flags;
1128
1129
1130 int hwts_rx_en;
1131 int hwts_tx_en;
1132
1133 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1134 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1135 struct gfar_priv_grp gfargrp[MAXGROUPS];
1136
1137 unsigned long state;
1138
1139 unsigned short mode;
1140 unsigned short poll_mode;
1141 unsigned int num_tx_queues;
1142 unsigned int num_rx_queues;
1143 unsigned int num_grps;
1144 int tx_actual_en;
1145
1146
1147 struct gfar_extra_stats extra_stats;
1148
1149
1150 phy_interface_t interface;
1151 struct device_node *phy_node;
1152 struct device_node *tbi_node;
1153 struct mii_bus *mii_bus;
1154 int oldspeed;
1155 int oldduplex;
1156 int oldlink;
1157
1158 uint32_t msg_enable;
1159
1160 struct work_struct reset_task;
1161
1162 struct platform_device *ofdev;
1163 unsigned char
1164 extended_hash:1,
1165 bd_stash_en:1,
1166 rx_filer_enable:1,
1167
1168 prio_sched_en:1,
1169
1170 pause_aneg_en:1,
1171 tx_pause_en:1,
1172 rx_pause_en:1;
1173
1174
1175 unsigned int total_tx_ring_size;
1176 unsigned int total_rx_ring_size;
1177
1178 u32 rqueue;
1179 u32 tqueue;
1180
1181
1182 unsigned int rx_stash_size;
1183 unsigned int rx_stash_index;
1184
1185 u32 cur_filer_idx;
1186
1187
1188 struct ethtool_rx_list rx_list;
1189 struct mutex rx_queue_access;
1190
1191
1192 u32 __iomem *hash_regs[16];
1193 int hash_width;
1194
1195
1196 u16 wol_opts;
1197 u16 wol_supported;
1198
1199
1200 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1201 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1202};
1203
1204
1205static inline int gfar_has_errata(struct gfar_private *priv,
1206 enum gfar_errata err)
1207{
1208 return priv->errata & err;
1209}
1210
1211static inline u32 gfar_read(unsigned __iomem *addr)
1212{
1213 u32 val;
1214 val = ioread32be(addr);
1215 return val;
1216}
1217
1218static inline void gfar_write(unsigned __iomem *addr, u32 val)
1219{
1220 iowrite32be(val, addr);
1221}
1222
1223static inline void gfar_write_filer(struct gfar_private *priv,
1224 unsigned int far, unsigned int fcr, unsigned int fpr)
1225{
1226 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1227
1228 gfar_write(®s->rqfar, far);
1229 gfar_write(®s->rqfcr, fcr);
1230 gfar_write(®s->rqfpr, fpr);
1231}
1232
1233static inline void gfar_read_filer(struct gfar_private *priv,
1234 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1235{
1236 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1237
1238 gfar_write(®s->rqfar, far);
1239 *fcr = gfar_read(®s->rqfcr);
1240 *fpr = gfar_read(®s->rqfpr);
1241}
1242
1243static inline void gfar_write_isrg(struct gfar_private *priv)
1244{
1245 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1246 u32 __iomem *baddr = ®s->isrg0;
1247 u32 isrg = 0;
1248 int grp_idx, i;
1249
1250 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1251 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1252
1253 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1254 isrg |= (ISRG_RR0 >> i);
1255 }
1256
1257 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1258 isrg |= (ISRG_TR0 >> i);
1259 }
1260
1261 gfar_write(baddr, isrg);
1262
1263 baddr++;
1264 isrg = 0;
1265 }
1266}
1267
1268static inline int gfar_is_dma_stopped(struct gfar_private *priv)
1269{
1270 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271
1272 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
1273 (IEVENT_GRSC | IEVENT_GTSC));
1274}
1275
1276static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
1277{
1278 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1279
1280 return gfar_read(®s->ievent) & IEVENT_GRSC;
1281}
1282
1283static inline void gfar_wmb(void)
1284{
1285#if defined(CONFIG_PPC)
1286
1287
1288
1289
1290
1291
1292
1293 eieio();
1294#else
1295 wmb();
1296#endif
1297}
1298
1299static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
1300{
1301 u32 lstatus = be32_to_cpu(bdp->lstatus);
1302
1303 lstatus &= BD_LFLAG(TXBD_WRAP);
1304 bdp->lstatus = cpu_to_be32(lstatus);
1305}
1306
1307static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
1308{
1309 if (rxq->next_to_clean > rxq->next_to_use)
1310 return rxq->next_to_clean - rxq->next_to_use - 1;
1311
1312 return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
1313}
1314
1315static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
1316{
1317 struct rxbd8 *bdp;
1318 u32 bdp_dma;
1319 int i;
1320
1321 i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
1322 bdp = &rxq->rx_bd_base[i];
1323 bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
1324 bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
1325
1326 return bdp_dma;
1327}
1328
1329irqreturn_t gfar_receive(int irq, void *dev_id);
1330int startup_gfar(struct net_device *dev);
1331void stop_gfar(struct net_device *dev);
1332void reset_gfar(struct net_device *dev);
1333void gfar_mac_reset(struct gfar_private *priv);
1334void gfar_halt(struct gfar_private *priv);
1335void gfar_start(struct gfar_private *priv);
1336void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
1337 u32 regnum, u32 read);
1338void gfar_configure_coalescing_all(struct gfar_private *priv);
1339int gfar_set_features(struct net_device *dev, netdev_features_t features);
1340
1341extern const struct ethtool_ops gfar_ethtool_ops;
1342
1343#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1344
1345#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1346#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1347#define RQFCR_PID_VID_MASK 0xFFFFF000
1348#define RQFCR_PID_PORT_MASK 0xFFFF0000
1349#define RQFCR_PID_MAC_MASK 0xFF000000
1350
1351struct gfar_mask_entry {
1352 unsigned int mask;
1353 unsigned int start;
1354 unsigned int end;
1355 unsigned int block;
1356};
1357
1358
1359struct gfar_filer_entry {
1360 u32 ctrl;
1361 u32 prop;
1362};
1363
1364
1365
1366struct filer_table {
1367 u32 index;
1368 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1369};
1370
1371#endif
1372