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14#ifndef __UCC_GETH_H__
15#define __UCC_GETH_H__
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/if_ether.h>
20
21#include <soc/fsl/qe/immap_qe.h>
22#include <soc/fsl/qe/qe.h>
23
24#include <soc/fsl/qe/ucc.h>
25#include <soc/fsl/qe/ucc_fast.h>
26
27#define DRV_DESC "QE UCC Gigabit Ethernet Controller"
28#define DRV_NAME "ucc_geth"
29#define DRV_VERSION "1.1"
30
31#define NUM_TX_QUEUES 8
32#define NUM_RX_QUEUES 8
33#define NUM_BDS_IN_PREFETCHED_BDS 4
34#define TX_IP_OFFSET_ENTRY_MAX 8
35#define NUM_OF_PADDRS 4
36#define ENET_INIT_PARAM_MAX_ENTRIES_RX 9
37#define ENET_INIT_PARAM_MAX_ENTRIES_TX 8
38
39struct ucc_geth {
40 struct ucc_fast uccf;
41 u8 res0[0x100 - sizeof(struct ucc_fast)];
42
43 u32 maccfg1;
44 u32 maccfg2;
45 u32 ipgifg;
46 u32 hafdup;
47 u8 res1[0x10];
48 u8 miimng[0x18];
49 u32 ifctl;
50 u32 ifstat;
51 u32 macstnaddr1;
52 u32 macstnaddr2;
53 u8 res2[0x8];
54 u32 uempr;
55 u32 utbipar;
56 u16 uescr;
57 u8 res3[0x180 - 0x15A];
58 u32 tx64;
59
60
61
62
63 u32 tx127;
64
65
66
67 u32 tx255;
68
69
70 u32 rx64;
71
72
73 u32 rx127;
74
75
76 u32 rx255;
77
78
79 u32 txok;
80
81
82 u16 txcf;
83
84 u8 res4[0x2];
85 u32 tmca;
86
87
88 u32 tbca;
89
90
91 u32 rxfok;
92 u32 rxbok;
93 u32 rbyt;
94
95
96
97 u32 rmca;
98
99
100 u32 rbca;
101
102
103 u32 scar;
104 u32 scam;
105 u8 res5[0x200 - 0x1c4];
106} __packed;
107
108
109#define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100
110
111#define TEMODER_SCHEDULER_ENABLE 0x2000
112#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
113
114#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
115
116
117#define TEMODER_RMON_STATISTICS 0x0100
118
119#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
120
121
122
123#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
124
125#define REMODER_RX_EXTENDED_FEATURES 0x80000000
126
127
128#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
129
130#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
131
132#define REMODER_RX_QOS_MODE_SHIFT (31-15)
133
134#define REMODER_RMON_STATISTICS 0x00001000
135
136#define REMODER_RX_EXTENDED_FILTERING 0x00000800
137
138
139
140
141#define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
142
143#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
144
145
146
147#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
148
149
150
151#define REMODER_IP_CHECKSUM_CHECK 0x00000002
152
153#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
154
155
156
157
158
159#define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
160 UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
161 UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
162 UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
163
164#define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
165 UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
166 UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
167 UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
168
169#define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
170 UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
171 UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
172 UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
173
174#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
175 UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
176 UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
177
178#define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY)
179#define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE)
180
181
182#define ENET_TBI_MII_CR 0x00
183#define ENET_TBI_MII_SR 0x01
184#define ENET_TBI_MII_ANA 0x04
185#define ENET_TBI_MII_ANLPBPA 0x05
186#define ENET_TBI_MII_ANEX 0x06
187#define ENET_TBI_MII_ANNPT 0x07
188#define ENET_TBI_MII_ANLPANP 0x08
189#define ENET_TBI_MII_EXST 0x0F
190#define ENET_TBI_MII_JD 0x10
191#define ENET_TBI_MII_TBICON 0x11
192
193
194#define TBISR_LSTATUS 0x0004
195#define TBICON_CLK_SELECT 0x0020
196#define TBIANA_ASYMMETRIC_PAUSE 0x0100
197#define TBIANA_SYMMETRIC_PAUSE 0x0080
198#define TBIANA_HALF_DUPLEX 0x0040
199#define TBIANA_FULL_DUPLEX 0x0020
200#define TBICR_PHY_RESET 0x8000
201#define TBICR_ANEG_ENABLE 0x1000
202#define TBICR_RESTART_ANEG 0x0200
203#define TBICR_FULL_DUPLEX 0x0100
204#define TBICR_SPEED1_SET 0x0040
205
206#define TBIANA_SETTINGS ( \
207 TBIANA_ASYMMETRIC_PAUSE \
208 | TBIANA_SYMMETRIC_PAUSE \
209 | TBIANA_FULL_DUPLEX \
210 )
211#define TBICR_SETTINGS ( \
212 TBICR_PHY_RESET \
213 | TBICR_ANEG_ENABLE \
214 | TBICR_FULL_DUPLEX \
215 | TBICR_SPEED1_SET \
216 )
217
218
219#define MACCFG1_FLOW_RX 0x00000020
220
221#define MACCFG1_FLOW_TX 0x00000010
222
223#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008
224
225
226
227#define MACCFG1_ENABLE_RX 0x00000004
228#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002
229
230
231
232#define MACCFG1_ENABLE_TX 0x00000001
233
234
235#define MACCFG2_PREL_SHIFT (31 - 19)
236
237
238#define MACCFG2_PREL_MASK 0x0000f000
239
240#define MACCFG2_SRP 0x00000080
241
242#define MACCFG2_STP 0x00000040
243
244
245#define MACCFG2_RESERVED_1 0x00000020
246
247
248#define MACCFG2_LC 0x00000010
249
250#define MACCFG2_MPE 0x00000008
251
252#define MACCFG2_FDX 0x00000001
253#define MACCFG2_FDX_MASK 0x00000001
254
255#define MACCFG2_PAD_CRC 0x00000004
256#define MACCFG2_CRC_EN 0x00000002
257#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
258
259
260
261#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
262
263#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
264#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
265
266
267#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
268
269
270#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
271
272
273
274
275
276#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7)
277
278
279
280
281#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)
282
283
284
285
286#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23)
287
288
289#define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31)
290
291
292
293#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127
294
295
296#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127
297
298
299#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255
300
301#define IPGIFG_BACK_TO_BACK_IFG_MAX 127
302
303#define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000
304#define IPGIFG_NBTB_IPG_MASK 0x007F0000
305#define IPGIFG_MIN_IFG_MASK 0x0000FF00
306#define IPGIFG_BTB_IPG_MASK 0x0000007F
307
308
309#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11)
310
311
312
313
314
315#define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf
316
317
318#define HALFDUP_ALT_BEB 0x00080000
319
320
321
322#define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000
323
324
325#define HALFDUP_NO_BACKOFF 0x00020000
326#define HALFDUP_EXCESSIVE_DEFER 0x00010000
327
328#define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19)
329
330
331#define HALFDUP_MAX_RETRANSMISSION_MAX 0xf
332
333
334#define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31)
335
336
337#define HALFDUP_COLLISION_WINDOW_MAX 0x3f
338
339#define HALFDUP_ALT_BEB_TR_MASK 0x00F00000
340#define HALFDUP_RETRANS_MASK 0x0000F000
341#define HALFDUP_COL_WINDOW_MASK 0x0000003F
342
343
344#define UCCS_BPR 0x02
345
346#define UCCS_PAU 0x02
347
348#define UCCS_MPD 0x01
349
350
351
352#define IFSTAT_EXCESS_DEFER 0x00000200
353
354
355
356
357#define MACSTNADDR1_OCTET_6_SHIFT (31 - 7)
358
359
360
361#define MACSTNADDR1_OCTET_5_SHIFT (31 - 15)
362
363
364
365#define MACSTNADDR1_OCTET_4_SHIFT (31 - 23)
366
367
368
369#define MACSTNADDR1_OCTET_3_SHIFT (31 - 31)
370
371
372
373
374
375#define MACSTNADDR2_OCTET_2_SHIFT (31 - 7)
376
377
378
379#define MACSTNADDR2_OCTET_1_SHIFT (31 - 15)
380
381
382
383
384
385#define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15)
386
387
388#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31)
389
390
391
392
393
394#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
395
396#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
397
398
399
400#define UESCR_AUTOZ 0x8000
401
402
403
404#define UESCR_CLRCNT 0x4000
405
406#define UESCR_MAXCOV_SHIFT (15 - 7)
407
408
409
410#define UESCR_SCOV_SHIFT (15 - 15)
411
412
413
414
415
416#define UDSR_MAGIC 0x067E
417
418struct ucc_geth_thread_data_tx {
419 u8 res0[104];
420} __packed;
421
422struct ucc_geth_thread_data_rx {
423 u8 res0[40];
424} __packed;
425
426
427struct ucc_geth_send_queue_qd {
428 u32 bd_ring_base;
429 u8 res0[0x8];
430 u32 last_bd_completed_address;
431 u8 res1[0x30];
432} __packed;
433
434struct ucc_geth_send_queue_mem_region {
435 struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
436} __packed;
437
438struct ucc_geth_thread_tx_pram {
439 u8 res0[64];
440} __packed;
441
442struct ucc_geth_thread_rx_pram {
443 u8 res0[128];
444} __packed;
445
446#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64
447#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64
448#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96
449
450struct ucc_geth_scheduler {
451 u16 cpucount0;
452 u16 cpucount1;
453 u16 cecount0;
454 u16 cecount1;
455 u16 cpucount2;
456 u16 cpucount3;
457 u16 cecount2;
458 u16 cecount3;
459 u16 cpucount4;
460 u16 cpucount5;
461 u16 cecount4;
462 u16 cecount5;
463 u16 cpucount6;
464 u16 cpucount7;
465 u16 cecount6;
466 u16 cecount7;
467 u32 weightstatus[NUM_TX_QUEUES];
468 u32 rtsrshadow;
469 u32 time;
470 u32 ttl;
471 u32 mblinterval;
472 u16 nortsrbytetime;
473 u8 fracsiz;
474
475 u8 res0[1];
476 u8 strictpriorityq;
477 u8 txasap;
478 u8 extrabw;
479 u8 oldwfqmask;
480 u8 weightfactor[NUM_TX_QUEUES];
481
482 u32 minw;
483 u8 res1[0x70 - 0x64];
484} __packed;
485
486struct ucc_geth_tx_firmware_statistics_pram {
487 u32 sicoltx;
488 u32 mulcoltx;
489 u32 latecoltxfr;
490 u32 frabortduecol;
491 u32 frlostinmactxer;
492
493
494 u32 carriersenseertx;
495 u32 frtxok;
496 u32 txfrexcessivedefer;
497
498 u32 txpkts256;
499
500 u32 txpkts512;
501
502 u32 txpkts1024;
503
504 u32 txpktsjumbo;
505
506} __packed;
507
508struct ucc_geth_rx_firmware_statistics_pram {
509 u32 frrxfcser;
510 u32 fraligner;
511 u32 inrangelenrxer;
512 u32 outrangelenrxer;
513 u32 frtoolong;
514 u32 runt;
515 u32 verylongevent;
516 u32 symbolerror;
517 u32 dropbsy;
518 u8 res0[0x8];
519 u32 mismatchdrop;
520
521 u32 underpkts;
522 u32 pkts256;
523
524 u32 pkts512;
525
526 u32 pkts1024;
527
528 u32 pktsjumbo;
529
530 u32 frlossinmacer;
531
532 u32 pausefr;
533 u8 res1[0x4];
534 u32 removevlan;
535
536 u32 replacevlan;
537
538 u32 insertvlan;
539
540} __packed;
541
542struct ucc_geth_rx_interrupt_coalescing_entry {
543 u32 interruptcoalescingmaxvalue;
544
545 u32 interruptcoalescingcounter;
546
547
548} __packed;
549
550struct ucc_geth_rx_interrupt_coalescing_table {
551 struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
552
553} __packed;
554
555struct ucc_geth_rx_prefetched_bds {
556 struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];
557} __packed;
558
559struct ucc_geth_rx_bd_queues_entry {
560 u32 bdbaseptr;
561 u32 bdptr;
562 u32 externalbdbaseptr;
563 u32 externalbdptr;
564} __packed;
565
566struct ucc_geth_tx_global_pram {
567 u16 temoder;
568 u8 res0[0x38 - 0x02];
569 u32 sqptr;
570 u32 schedulerbasepointer;
571
572 u32 txrmonbaseptr;
573 u32 tstate;
574
575 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
576 u32 vtagtable[0x8];
577 u32 tqptr;
578
579 u8 res2[0x80 - 0x74];
580} __packed;
581
582
583struct ucc_geth_exf_global_pram {
584 u32 l2pcdptr;
585 u8 res0[0x10 - 0x04];
586} __packed;
587
588struct ucc_geth_rx_global_pram {
589 u32 remoder;
590 u32 rqptr;
591 u32 res0[0x1];
592 u8 res1[0x20 - 0xC];
593 u16 typeorlen;
594
595 u8 res2[0x1];
596 u8 rxgstpack;
597 u32 rxrmonbaseptr;
598 u8 res3[0x30 - 0x28];
599 u32 intcoalescingptr;
600 u8 res4[0x36 - 0x34];
601 u8 rstate;
602
603 u8 res5[0x46 - 0x37];
604 u16 mrblr;
605 u32 rbdqptr;
606
607 u16 mflr;
608 u16 minflr;
609 u16 maxd1;
610 u16 maxd2;
611 u32 ecamptr;
612 u32 l2qt;
613 u32 l3qt[0x8];
614 u16 vlantype;
615 u16 vlantci;
616 u8 addressfiltering[64];
617 u32 exfGlobalParam;
618
619 u8 res6[0x100 - 0xC4];
620} __packed;
621
622#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
623
624
625struct ucc_geth_init_pram {
626 u8 resinit1;
627 u8 resinit2;
628 u8 resinit3;
629 u8 resinit4;
630 u16 resinit5;
631 u8 res1[0x1];
632 u8 largestexternallookupkeysize;
633 u32 rgftgfrxglobal;
634 u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];
635 u8 res2[0x38 - 0x30];
636 u32 txglobal;
637 u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];
638 u8 res3[0x1];
639} __packed;
640
641#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
642#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
643
644#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
645#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
646#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
647#define ENET_INIT_PARAM_SNUM_SHIFT 24
648
649#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06
650#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30
651#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff
652#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00
653#define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400
654
655
656struct ucc_geth_82xx_enet_address {
657 u8 res1[0x2];
658 u16 h;
659 u16 m;
660 u16 l;
661} __packed;
662
663
664struct ucc_geth_82xx_address_filtering_pram {
665 u32 iaddr_h;
666 u32 iaddr_l;
667 u32 gaddr_h;
668 u32 gaddr_l;
669 struct ucc_geth_82xx_enet_address __iomem taddr;
670 struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
671 u8 res0[0x40 - 0x38];
672} __packed;
673
674
675
676struct ucc_geth_tx_firmware_statistics {
677 u32 sicoltx;
678 u32 mulcoltx;
679 u32 latecoltxfr;
680 u32 frabortduecol;
681 u32 frlostinmactxer;
682
683
684 u32 carriersenseertx;
685 u32 frtxok;
686 u32 txfrexcessivedefer;
687
688 u32 txpkts256;
689
690 u32 txpkts512;
691
692 u32 txpkts1024;
693
694 u32 txpktsjumbo;
695
696} __packed;
697
698
699
700struct ucc_geth_rx_firmware_statistics {
701 u32 frrxfcser;
702 u32 fraligner;
703 u32 inrangelenrxer;
704 u32 outrangelenrxer;
705 u32 frtoolong;
706 u32 runt;
707 u32 verylongevent;
708 u32 symbolerror;
709 u32 dropbsy;
710 u8 res0[0x8];
711 u32 mismatchdrop;
712
713 u32 underpkts;
714 u32 pkts256;
715
716 u32 pkts512;
717
718 u32 pkts1024;
719
720 u32 pktsjumbo;
721
722 u32 frlossinmacer;
723
724 u32 pausefr;
725 u8 res1[0x4];
726 u32 removevlan;
727
728 u32 replacevlan;
729
730 u32 insertvlan;
731
732} __packed;
733
734
735
736struct ucc_geth_hardware_statistics {
737 u32 tx64;
738
739
740
741
742 u32 tx127;
743
744
745
746 u32 tx255;
747
748
749 u32 rx64;
750
751
752 u32 rx127;
753
754
755 u32 rx255;
756
757
758 u32 txok;
759
760
761 u16 txcf;
762
763 u32 tmca;
764
765
766 u32 tbca;
767
768
769 u32 rxfok;
770 u32 rxbok;
771 u32 rbyt;
772
773
774
775 u32 rmca;
776
777
778 u32 rbca;
779
780
781} __packed;
782
783
784#define TX_ERRORS_DEF 0x0200
785#define TX_ERRORS_EXDEF 0x0100
786#define TX_ERRORS_LC 0x0080
787#define TX_ERRORS_RL 0x0040
788#define TX_ERRORS_RC_MASK 0x003C
789#define TX_ERRORS_RC_SHIFT 2
790#define TX_ERRORS_UN 0x0002
791#define TX_ERRORS_CSL 0x0001
792
793
794#define RX_ERRORS_CMR 0x0200
795#define RX_ERRORS_M 0x0100
796#define RX_ERRORS_BC 0x0080
797#define RX_ERRORS_MC 0x0040
798
799
800#define T_VID 0x003c0000
801#define T_DEF (((u32) TX_ERRORS_DEF ) << 16)
802#define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16)
803#define T_LC (((u32) TX_ERRORS_LC ) << 16)
804#define T_RL (((u32) TX_ERRORS_RL ) << 16)
805#define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16)
806#define T_UN (((u32) TX_ERRORS_UN ) << 16)
807#define T_CSL (((u32) TX_ERRORS_CSL ) << 16)
808#define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
809 | T_UN | T_CSL)
810
811
812#define R_LG 0x00200000
813#define R_NO 0x00100000
814#define R_SH 0x00080000
815#define R_CR 0x00040000
816#define R_OV 0x00020000
817#define R_IPCH 0x00010000
818#define R_CMR (((u32) RX_ERRORS_CMR ) << 16)
819#define R_M (((u32) RX_ERRORS_M ) << 16)
820#define R_BC (((u32) RX_ERRORS_BC ) << 16)
821#define R_MC (((u32) RX_ERRORS_MC ) << 16)
822#define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)
823
824#define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
825 R_OV | R_IPCH)
826
827
828#define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256
829#define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128
830#define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128
831#define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64
832#define UCC_GETH_THREAD_DATA_ALIGNMENT 256
833
834
835
836
837#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
838#define UCC_GETH_SCHEDULER_ALIGNMENT 8
839#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4
840#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4
841#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
842#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8
843#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128
844#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8
845
846
847
848#define UCC_GETH_RX_BD_RING_ALIGNMENT 32
849#define UCC_GETH_TX_BD_RING_ALIGNMENT 32
850#define UCC_GETH_MRBLR_ALIGNMENT 128
851#define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4
852#define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
853#define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64
854
855#define UCC_GETH_TAD_EF 0x80
856#define UCC_GETH_TAD_V 0x40
857#define UCC_GETH_TAD_REJ 0x20
858#define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2
859#define UCC_GETH_TAD_VTAG_OP_SHIFT 6
860#define UCC_GETH_TAD_V_NON_VTAG_OP 0x20
861#define UCC_GETH_TAD_RQOS_SHIFT 0
862#define UCC_GETH_TAD_V_PRIORITY_SHIFT 5
863#define UCC_GETH_TAD_CFI 0x10
864
865#define UCC_GETH_VLAN_PRIORITY_MAX 8
866#define UCC_GETH_IP_PRIORITY_MAX 64
867#define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8
868#define UCC_GETH_RX_BD_RING_SIZE_MIN 8
869#define UCC_GETH_TX_BD_RING_SIZE_MIN 2
870#define UCC_GETH_BD_RING_SIZE_MAX 0xffff
871
872#define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD
873
874
875#define TX_BD_RING_LEN 0x10
876#define RX_BD_RING_LEN 0x20
877
878#define TX_RING_MOD_MASK(size) (size-1)
879#define RX_RING_MOD_MASK(size) (size-1)
880
881#define ENET_GROUP_ADDR 0x01
882
883
884
885#define TX_TIMEOUT (1*HZ)
886#define SKB_ALLOC_TIMEOUT 100000
887#define PHY_INIT_TIMEOUT 100000
888#define PHY_CHANGE_TIME 2
889
890
891#define UCC_GETH_URFS_INIT 512
892
893#define UCC_GETH_URFET_INIT 256
894#define UCC_GETH_URFSET_INIT 384
895#define UCC_GETH_UTFS_INIT 512
896
897#define UCC_GETH_UTFET_INIT 256
898#define UCC_GETH_UTFTT_INIT 256
899
900
901#define UCC_GETH_URFS_GIGA_INIT 4096
902
903#define UCC_GETH_URFET_GIGA_INIT 2048
904#define UCC_GETH_URFSET_GIGA_INIT 3072
905#define UCC_GETH_UTFS_GIGA_INIT 4096
906
907#define UCC_GETH_UTFET_GIGA_INIT 2048
908#define UCC_GETH_UTFTT_GIGA_INIT 4096
909
910
911#define UCC_GETH_REMODER_INIT 0
912
913#define UCC_GETH_TEMODER_INIT 0xC000
914
915
916#define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1
917
918#define UCC_GETH_MACCFG1_INIT 0
919#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)
920
921
922enum enet_addr_type {
923 ENET_ADDR_TYPE_INDIVIDUAL,
924 ENET_ADDR_TYPE_GROUP,
925 ENET_ADDR_TYPE_BROADCAST
926};
927
928
929enum ucc_geth_enet_address_recognition_location {
930 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,
931
932 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST,
933
934
935
936 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,
937
938
939
940 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,
941
942
943
944 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,
945
946
947
948 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,
949 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH
950
951};
952
953
954enum ucc_geth_vlan_operation_tagged {
955 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,
956 UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
957 = 0x1,
958 UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
959 = 0x2,
960 UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
961 = 0x3
962};
963
964
965enum ucc_geth_vlan_operation_non_tagged {
966 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,
967 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1
968
969
970};
971
972
973enum ucc_geth_qos_mode {
974 UCC_GETH_QOS_MODE_DEFAULT = 0x0,
975 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,
976
977
978
979 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2
980
981
982
983};
984
985
986
987enum ucc_geth_statistics_gathering_mode {
988 UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,
989
990
991 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,
992
993
994
995
996 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,
997
998
999
1000
1001
1002 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008
1003
1004
1005
1006
1007
1008};
1009
1010
1011enum ucc_geth_maccfg2_pad_and_crc_mode {
1012 UCC_GETH_PAD_AND_CRC_MODE_NONE
1013 = MACCFG2_PAD_AND_CRC_MODE_NONE,
1014
1015
1016 UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1017 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,
1018
1019 UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1020 MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1021};
1022
1023
1024enum ucc_geth_flow_control_mode {
1025 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,
1026
1027
1028 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1029 = 0x00004000
1030
1031};
1032
1033
1034enum ucc_geth_num_of_threads {
1035 UCC_GETH_NUM_OF_THREADS_1 = 0x1,
1036 UCC_GETH_NUM_OF_THREADS_2 = 0x2,
1037 UCC_GETH_NUM_OF_THREADS_4 = 0x0,
1038 UCC_GETH_NUM_OF_THREADS_6 = 0x3,
1039 UCC_GETH_NUM_OF_THREADS_8 = 0x4
1040};
1041
1042
1043enum ucc_geth_num_of_station_addresses {
1044 UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
1045 UCC_GETH_NUM_OF_STATION_ADDRESSES_5
1046};
1047
1048
1049struct enet_addr_container {
1050 u8 address[ETH_ALEN];
1051 enum ucc_geth_enet_address_recognition_location location;
1052
1053
1054
1055 struct list_head node;
1056};
1057
1058#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1059
1060
1061struct ucc_geth_tad_params {
1062 int rx_non_dynamic_extended_features_mode;
1063 int reject_frame;
1064 enum ucc_geth_vlan_operation_tagged vtag_op;
1065 enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1066 enum ucc_geth_qos_mode rqos;
1067 u8 vpri;
1068 u16 vid;
1069};
1070
1071
1072struct ucc_geth_info {
1073 struct ucc_fast_info uf_info;
1074 u8 numQueuesTx;
1075 u8 numQueuesRx;
1076 int ipCheckSumCheck;
1077 int ipCheckSumGenerate;
1078 int rxExtendedFiltering;
1079 u32 extendedFilteringChainPointer;
1080 u16 typeorlen;
1081 int dynamicMaxFrameLength;
1082 int dynamicMinFrameLength;
1083 u8 nonBackToBackIfgPart1;
1084 u8 nonBackToBackIfgPart2;
1085 u8 miminumInterFrameGapEnforcement;
1086 u8 backToBackInterFrameGap;
1087 int ipAddressAlignment;
1088 int lengthCheckRx;
1089 u32 mblinterval;
1090 u16 nortsrbytetime;
1091 u8 fracsiz;
1092 u8 strictpriorityq;
1093 u8 txasap;
1094 u8 extrabw;
1095 int miiPreambleSupress;
1096 u8 altBebTruncation;
1097 int altBeb;
1098 int backPressureNoBackoff;
1099 int noBackoff;
1100 int excessDefer;
1101 u8 maxRetransmission;
1102 u8 collisionWindow;
1103 int pro;
1104 int cap;
1105 int rsh;
1106 int rlpb;
1107 int cam;
1108 int bro;
1109 int ecm;
1110 int receiveFlowControl;
1111 int transmitFlowControl;
1112 u8 maxGroupAddrInHash;
1113 u8 maxIndAddrInHash;
1114 u8 prel;
1115 u16 maxFrameLength;
1116 u16 minFrameLength;
1117 u16 maxD1Length;
1118 u16 maxD2Length;
1119 u16 vlantype;
1120 u16 vlantci;
1121 u32 ecamptr;
1122 u32 eventRegMask;
1123 u16 pausePeriod;
1124 u16 extensionField;
1125 struct device_node *phy_node;
1126 struct device_node *tbi_node;
1127 u8 weightfactor[NUM_TX_QUEUES];
1128 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1129 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1130 u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1131 u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1132 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1133 u16 bdRingLenTx[NUM_TX_QUEUES];
1134 u16 bdRingLenRx[NUM_RX_QUEUES];
1135 enum ucc_geth_num_of_station_addresses numStationAddresses;
1136 enum qe_fltr_largest_external_tbl_lookup_key_size
1137 largestexternallookupkeysize;
1138 enum ucc_geth_statistics_gathering_mode statisticsMode;
1139 enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1140 enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1141 enum ucc_geth_qos_mode rxQoSMode;
1142 enum ucc_geth_flow_control_mode aufc;
1143 enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1144 enum ucc_geth_num_of_threads numThreadsTx;
1145 enum ucc_geth_num_of_threads numThreadsRx;
1146 unsigned int riscTx;
1147 unsigned int riscRx;
1148};
1149
1150
1151struct ucc_geth_private {
1152 struct ucc_geth_info *ug_info;
1153 struct ucc_fast_private *uccf;
1154 struct device *dev;
1155 struct net_device *ndev;
1156 struct napi_struct napi;
1157 struct work_struct timeout_work;
1158 struct ucc_geth __iomem *ug_regs;
1159 struct ucc_geth_init_pram *p_init_enet_param_shadow;
1160 struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1161 u32 exf_glbl_param_offset;
1162 struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1163 u32 rx_glbl_pram_offset;
1164 struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1165 u32 tx_glbl_pram_offset;
1166 struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1167 u32 send_q_mem_reg_offset;
1168 struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1169 u32 thread_dat_tx_offset;
1170 struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1171 u32 thread_dat_rx_offset;
1172 struct ucc_geth_scheduler __iomem *p_scheduler;
1173 u32 scheduler_offset;
1174 struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1175 u32 tx_fw_statistics_pram_offset;
1176 struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1177 u32 rx_fw_statistics_pram_offset;
1178 struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1179 u32 rx_irq_coalescing_tbl_offset;
1180 struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1181 u32 rx_bd_qs_tbl_offset;
1182 u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1183 u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1184 u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1185 u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1186 u8 __iomem *confBd[NUM_TX_QUEUES];
1187 u8 __iomem *txBd[NUM_TX_QUEUES];
1188 u8 __iomem *rxBd[NUM_RX_QUEUES];
1189 int badFrame[NUM_RX_QUEUES];
1190 u16 cpucount[NUM_TX_QUEUES];
1191 u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1192 int indAddrRegUsed[NUM_OF_PADDRS];
1193 u8 paddr[NUM_OF_PADDRS][ETH_ALEN];
1194 u8 numGroupAddrInHash;
1195 u8 numIndAddrInHash;
1196 u8 numIndAddrInReg;
1197 int rx_extended_features;
1198 int rx_non_dynamic_extended_features;
1199 struct list_head conf_skbs;
1200 struct list_head group_hash_q;
1201 struct list_head ind_hash_q;
1202 u32 saved_uccm;
1203 spinlock_t lock;
1204
1205 struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1206 struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1207
1208 u16 skb_curtx[NUM_TX_QUEUES];
1209 u16 skb_currx[NUM_RX_QUEUES];
1210
1211 u16 skb_dirtytx[NUM_TX_QUEUES];
1212
1213 struct ugeth_mii_info *mii_info;
1214 struct phy_device *phydev;
1215 phy_interface_t phy_interface;
1216 int max_speed;
1217 uint32_t msg_enable;
1218 int oldspeed;
1219 int oldduplex;
1220 int oldlink;
1221 int wol_en;
1222
1223 struct device_node *node;
1224};
1225
1226void uec_set_ethtool_ops(struct net_device *netdev);
1227int init_flow_control_params(u32 automatic_flow_control_mode,
1228 int rx_flow_control_enable, int tx_flow_control_enable,
1229 u16 pause_period, u16 extension_field,
1230 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1231 u32 __iomem *maccfg1_register);
1232
1233
1234#endif
1235