1
2
3
4#ifndef __HNS3_ENET_H
5#define __HNS3_ENET_H
6
7#include <linux/if_vlan.h>
8
9#include "hnae3.h"
10
11#define HNS3_MOD_VERSION "1.0"
12
13extern const char hns3_driver_version[];
14
15enum hns3_nic_state {
16 HNS3_NIC_STATE_TESTING,
17 HNS3_NIC_STATE_RESETTING,
18 HNS3_NIC_STATE_INITED,
19 HNS3_NIC_STATE_DOWN,
20 HNS3_NIC_STATE_DISABLED,
21 HNS3_NIC_STATE_REMOVING,
22 HNS3_NIC_STATE_SERVICE_INITED,
23 HNS3_NIC_STATE_SERVICE_SCHED,
24 HNS3_NIC_STATE2_RESET_REQUESTED,
25 HNS3_NIC_STATE_MAX
26};
27
28#define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
29#define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
30#define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
31#define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
32#define HNS3_RING_RX_RING_TAIL_REG 0x00018
33#define HNS3_RING_RX_RING_HEAD_REG 0x0001C
34#define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
35#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
36
37#define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
38#define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
39#define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
40#define HNS3_RING_TX_RING_TC_REG 0x00050
41#define HNS3_RING_TX_RING_TAIL_REG 0x00058
42#define HNS3_RING_TX_RING_HEAD_REG 0x0005C
43#define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
44#define HNS3_RING_TX_RING_OFFSET_REG 0x00064
45#define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
46#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
47#define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
48#define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
49#define HNS3_RING_PREFETCH_EN_REG 0x0007C
50#define HNS3_RING_CFG_VF_NUM_REG 0x00080
51#define HNS3_RING_ASID_REG 0x0008C
52#define HNS3_RING_EN_REG 0x00090
53#define HNS3_RING_T0_BE_RST 0x00094
54#define HNS3_RING_COULD_BE_RST 0x00098
55#define HNS3_RING_WRR_WEIGHT_REG 0x0009c
56
57#define HNS3_RING_INTMSK_RXWL_REG 0x000A0
58#define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
59#define HNS3_RX_RING_INT_STS_REG 0x000A8
60#define HNS3_RING_INTMSK_TXWL_REG 0x000AC
61#define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
62#define HNS3_TX_RING_INT_STS_REG 0x000B4
63#define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
64#define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
65#define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
66#define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
67
68#define HNS3_RING_MB_CTRL_REG 0x00100
69#define HNS3_RING_MB_DATA_BASE_REG 0x00200
70
71#define HNS3_TX_REG_OFFSET 0x40
72
73#define HNS3_RX_HEAD_SIZE 256
74
75#define HNS3_TX_TIMEOUT (5 * HZ)
76#define HNS3_RING_NAME_LEN 16
77#define HNS3_BUFFER_SIZE_2048 2048
78#define HNS3_RING_MAX_PENDING 32768
79#define HNS3_RING_MIN_PENDING 24
80#define HNS3_RING_BD_MULTIPLE 8
81
82#define HNS3_MAC_MAX_FRAME 9728
83#define HNS3_MAX_MTU \
84 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
85
86#define HNS3_BD_SIZE_512_TYPE 0
87#define HNS3_BD_SIZE_1024_TYPE 1
88#define HNS3_BD_SIZE_2048_TYPE 2
89#define HNS3_BD_SIZE_4096_TYPE 3
90
91#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
92#define HNS3_RX_FLAG_L3ID_IPV4 0x0
93#define HNS3_RX_FLAG_L3ID_IPV6 0x1
94#define HNS3_RX_FLAG_L4ID_UDP 0x0
95#define HNS3_RX_FLAG_L4ID_TCP 0x1
96
97#define HNS3_RXD_DMAC_S 0
98#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
99#define HNS3_RXD_VLAN_S 2
100#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
101#define HNS3_RXD_L3ID_S 4
102#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
103#define HNS3_RXD_L4ID_S 8
104#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
105#define HNS3_RXD_FRAG_B 12
106#define HNS3_RXD_STRP_TAGP_S 13
107#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
108
109#define HNS3_RXD_L2E_B 16
110#define HNS3_RXD_L3E_B 17
111#define HNS3_RXD_L4E_B 18
112#define HNS3_RXD_TRUNCAT_B 19
113#define HNS3_RXD_HOI_B 20
114#define HNS3_RXD_DOI_B 21
115#define HNS3_RXD_OL3E_B 22
116#define HNS3_RXD_OL4E_B 23
117#define HNS3_RXD_GRO_COUNT_S 24
118#define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
119#define HNS3_RXD_GRO_FIXID_B 30
120#define HNS3_RXD_GRO_ECN_B 31
121
122#define HNS3_RXD_ODMAC_S 0
123#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
124#define HNS3_RXD_OVLAN_S 2
125#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
126#define HNS3_RXD_OL3ID_S 4
127#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
128#define HNS3_RXD_OL4ID_S 8
129#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
130#define HNS3_RXD_FBHI_S 12
131#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
132#define HNS3_RXD_FBLI_S 14
133#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
134
135#define HNS3_RXD_BDTYPE_S 0
136#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
137#define HNS3_RXD_VLD_B 4
138#define HNS3_RXD_UDP0_B 5
139#define HNS3_RXD_EXTEND_B 7
140#define HNS3_RXD_FE_B 8
141#define HNS3_RXD_LUM_B 9
142#define HNS3_RXD_CRCP_B 10
143#define HNS3_RXD_L3L4P_B 11
144#define HNS3_RXD_TSIND_S 12
145#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
146#define HNS3_RXD_LKBK_B 15
147#define HNS3_RXD_GRO_SIZE_S 16
148#define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
149
150#define HNS3_TXD_L3T_S 0
151#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
152#define HNS3_TXD_L4T_S 2
153#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
154#define HNS3_TXD_L3CS_B 4
155#define HNS3_TXD_L4CS_B 5
156#define HNS3_TXD_VLAN_B 6
157#define HNS3_TXD_TSO_B 7
158
159#define HNS3_TXD_L2LEN_S 8
160#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
161#define HNS3_TXD_L3LEN_S 16
162#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
163#define HNS3_TXD_L4LEN_S 24
164#define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
165
166#define HNS3_TXD_OL3T_S 0
167#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
168#define HNS3_TXD_OVLAN_B 2
169#define HNS3_TXD_MACSEC_B 3
170#define HNS3_TXD_TUNTYPE_S 4
171#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
172
173#define HNS3_TXD_BDTYPE_S 0
174#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
175#define HNS3_TXD_FE_B 4
176#define HNS3_TXD_SC_S 5
177#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
178#define HNS3_TXD_EXTEND_B 7
179#define HNS3_TXD_VLD_B 8
180#define HNS3_TXD_RI_B 9
181#define HNS3_TXD_RA_B 10
182#define HNS3_TXD_TSYN_B 11
183#define HNS3_TXD_DECTTL_S 12
184#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
185
186#define HNS3_TXD_MSS_S 0
187#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
188
189#define HNS3_TX_LAST_SIZE_M 0xffff
190
191#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
192#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
193
194#define HNS3_VECTOR_NOT_INITED 0
195#define HNS3_VECTOR_INITED 1
196
197#define HNS3_MAX_BD_SIZE 65535
198#define HNS3_MAX_BD_PER_FRAG 8
199#define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
200
201#define HNS3_VECTOR_GL0_OFFSET 0x100
202#define HNS3_VECTOR_GL1_OFFSET 0x200
203#define HNS3_VECTOR_GL2_OFFSET 0x300
204#define HNS3_VECTOR_RL_OFFSET 0x900
205#define HNS3_VECTOR_RL_EN_B 6
206
207#define HNS3_RING_EN_B 0
208
209enum hns3_pkt_l2t_type {
210 HNS3_L2_TYPE_UNICAST,
211 HNS3_L2_TYPE_MULTICAST,
212 HNS3_L2_TYPE_BROADCAST,
213 HNS3_L2_TYPE_INVALID,
214};
215
216enum hns3_pkt_l3t_type {
217 HNS3_L3T_NONE,
218 HNS3_L3T_IPV6,
219 HNS3_L3T_IPV4,
220 HNS3_L3T_RESERVED
221};
222
223enum hns3_pkt_l4t_type {
224 HNS3_L4T_UNKNOWN,
225 HNS3_L4T_TCP,
226 HNS3_L4T_UDP,
227 HNS3_L4T_SCTP
228};
229
230enum hns3_pkt_ol3t_type {
231 HNS3_OL3T_NONE,
232 HNS3_OL3T_IPV6,
233 HNS3_OL3T_IPV4_NO_CSUM,
234 HNS3_OL3T_IPV4_CSUM
235};
236
237enum hns3_pkt_tun_type {
238 HNS3_TUN_NONE,
239 HNS3_TUN_MAC_IN_UDP,
240 HNS3_TUN_NVGRE,
241 HNS3_TUN_OTHER
242};
243
244
245struct __packed hns3_desc {
246 __le64 addr;
247 union {
248 struct {
249 __le16 vlan_tag;
250 __le16 send_size;
251 union {
252 __le32 type_cs_vlan_tso_len;
253 struct {
254 __u8 type_cs_vlan_tso;
255 __u8 l2_len;
256 __u8 l3_len;
257 __u8 l4_len;
258 };
259 };
260 __le16 outer_vlan_tag;
261 __le16 tv;
262
263 union {
264 __le32 ol_type_vlan_len_msec;
265 struct {
266 __u8 ol_type_vlan_msec;
267 __u8 ol2_len;
268 __u8 ol3_len;
269 __u8 ol4_len;
270 };
271 };
272
273 __le32 paylen;
274 __le16 bdtp_fe_sc_vld_ra_ri;
275 __le16 mss;
276 } tx;
277
278 struct {
279 __le32 l234_info;
280 __le16 pkt_len;
281 __le16 size;
282
283 __le32 rss_hash;
284 __le16 fd_id;
285 __le16 vlan_tag;
286
287 union {
288 __le32 ol_info;
289 struct {
290 __le16 o_dm_vlan_id_fb;
291 __le16 ot_vlan_tag;
292 };
293 };
294
295 __le32 bd_base_info;
296 } rx;
297 };
298};
299
300struct hns3_desc_cb {
301 dma_addr_t dma;
302 void *buf;
303
304
305 void *priv;
306 u32 page_offset;
307 u32 length;
308
309 u16 reuse_flag;
310
311
312 u16 type;
313};
314
315enum hns3_pkt_l3type {
316 HNS3_L3_TYPE_IPV4,
317 HNS3_L3_TYPE_IPV6,
318 HNS3_L3_TYPE_ARP,
319 HNS3_L3_TYPE_RARP,
320 HNS3_L3_TYPE_IPV4_OPT,
321 HNS3_L3_TYPE_IPV6_EXT,
322 HNS3_L3_TYPE_LLDP,
323 HNS3_L3_TYPE_BPDU,
324 HNS3_L3_TYPE_MAC_PAUSE,
325 HNS3_L3_TYPE_PFC_PAUSE,
326
327
328
329 HNS3_L3_TYPE_CNM = 0xc,
330
331
332
333 HNS3_L3_TYPE_PARSE_FAIL = 0xf
334};
335
336enum hns3_pkt_l4type {
337 HNS3_L4_TYPE_UDP,
338 HNS3_L4_TYPE_TCP,
339 HNS3_L4_TYPE_GRE,
340 HNS3_L4_TYPE_SCTP,
341 HNS3_L4_TYPE_IGMP,
342 HNS3_L4_TYPE_ICMP,
343
344
345
346 HNS3_L4_TYPE_PARSE_FAIL = 0xf
347};
348
349enum hns3_pkt_ol3type {
350 HNS3_OL3_TYPE_IPV4 = 0,
351 HNS3_OL3_TYPE_IPV6,
352
353 HNS3_OL3_TYPE_IPV4_OPT = 4,
354 HNS3_OL3_TYPE_IPV6_EXT,
355
356
357
358 HNS3_OL3_TYPE_PARSE_FAIL = 0xf
359};
360
361enum hns3_pkt_ol4type {
362 HNS3_OL4_TYPE_NO_TUN,
363 HNS3_OL4_TYPE_MAC_IN_UDP,
364 HNS3_OL4_TYPE_NVGRE,
365 HNS3_OL4_TYPE_UNKNOWN
366};
367
368struct ring_stats {
369 u64 io_err_cnt;
370 u64 sw_err_cnt;
371 u64 seg_pkt_cnt;
372 union {
373 struct {
374 u64 tx_pkts;
375 u64 tx_bytes;
376 u64 tx_err_cnt;
377 u64 restart_queue;
378 u64 tx_busy;
379 u64 tx_copy;
380 };
381 struct {
382 u64 rx_pkts;
383 u64 rx_bytes;
384 u64 rx_err_cnt;
385 u64 reuse_pg_cnt;
386 u64 err_pkt_len;
387 u64 err_bd_num;
388 u64 l2_err;
389 u64 l3l4_csum_err;
390 u64 rx_multicast;
391 u64 non_reuse_pg;
392 };
393 };
394};
395
396struct hns3_enet_ring {
397 u8 __iomem *io_base;
398 struct hns3_desc *desc;
399 struct hns3_desc_cb *desc_cb;
400 struct hns3_enet_ring *next;
401 struct hns3_enet_tqp_vector *tqp_vector;
402 struct hnae3_queue *tqp;
403 struct device *dev;
404
405
406 struct ring_stats stats;
407 struct u64_stats_sync syncp;
408
409 dma_addr_t desc_dma_addr;
410 u32 buf_size;
411 u16 desc_num;
412 int next_to_use;
413
414
415
416
417 int next_to_clean;
418
419 u32 pull_len;
420 u32 frag_num;
421 unsigned char *va;
422
423 u32 flag;
424
425 int pending_buf;
426 struct sk_buff *skb;
427 struct sk_buff *tail_skb;
428};
429
430struct hns_queue;
431
432struct hns3_nic_ring_data {
433 struct hns3_enet_ring *ring;
434 struct napi_struct napi;
435 int queue_index;
436 int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
437 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
438 void (*fini_process)(struct hns3_nic_ring_data *);
439};
440
441enum hns3_flow_level_range {
442 HNS3_FLOW_LOW = 0,
443 HNS3_FLOW_MID = 1,
444 HNS3_FLOW_HIGH = 2,
445 HNS3_FLOW_ULTRA = 3,
446};
447
448#define HNS3_INT_GL_MAX 0x1FE0
449#define HNS3_INT_GL_50K 0x0014
450#define HNS3_INT_GL_20K 0x0032
451#define HNS3_INT_GL_18K 0x0036
452#define HNS3_INT_GL_8K 0x007C
453
454#define HNS3_INT_RL_MAX 0x00EC
455#define HNS3_INT_RL_ENABLE_MASK 0x40
456
457struct hns3_enet_coalesce {
458 u16 int_gl;
459 u8 gl_adapt_enable;
460 enum hns3_flow_level_range flow_level;
461};
462
463struct hns3_enet_ring_group {
464
465 struct hns3_enet_ring *ring;
466 u64 total_bytes;
467 u64 total_packets;
468 u16 count;
469 struct hns3_enet_coalesce coal;
470};
471
472struct hns3_enet_tqp_vector {
473 struct hnae3_handle *handle;
474 u8 __iomem *mask_addr;
475 int vector_irq;
476 int irq_init_flag;
477
478 u16 idx;
479
480 struct napi_struct napi;
481
482 struct hns3_enet_ring_group rx_group;
483 struct hns3_enet_ring_group tx_group;
484
485 cpumask_t affinity_mask;
486 u16 num_tqps;
487 struct irq_affinity_notify affinity_notify;
488
489 char name[HNAE3_INT_NAME_LEN];
490
491 unsigned long last_jiffies;
492} ____cacheline_internodealigned_in_smp;
493
494enum hns3_udp_tnl_type {
495 HNS3_UDP_TNL_VXLAN,
496 HNS3_UDP_TNL_GENEVE,
497 HNS3_UDP_TNL_MAX,
498};
499
500struct hns3_udp_tunnel {
501 u16 dst_port;
502 int used;
503};
504
505struct hns3_nic_priv {
506 struct hnae3_handle *ae_handle;
507 u32 enet_ver;
508 u32 port_id;
509 struct net_device *netdev;
510 struct device *dev;
511
512
513
514
515
516 struct hns3_nic_ring_data *ring_data;
517 struct hns3_enet_tqp_vector *tqp_vector;
518 u16 vector_num;
519
520
521 int link;
522 u64 tx_timeout_count;
523
524 unsigned long state;
525
526 struct timer_list service_timer;
527
528 struct work_struct service_task;
529
530 struct notifier_block notifier_block;
531
532 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
533 struct hns3_enet_coalesce tx_coal;
534 struct hns3_enet_coalesce rx_coal;
535};
536
537union l3_hdr_info {
538 struct iphdr *v4;
539 struct ipv6hdr *v6;
540 unsigned char *hdr;
541};
542
543union l4_hdr_info {
544 struct tcphdr *tcp;
545 struct udphdr *udp;
546 struct gre_base_hdr *gre;
547 unsigned char *hdr;
548};
549
550static inline int ring_space(struct hns3_enet_ring *ring)
551{
552
553
554
555 int begin = smp_load_acquire(&ring->next_to_clean);
556 int end = READ_ONCE(ring->next_to_use);
557
558 return ((end >= begin) ? (ring->desc_num - end + begin) :
559 (begin - end)) - 1;
560}
561
562static inline int is_ring_empty(struct hns3_enet_ring *ring)
563{
564 return ring->next_to_use == ring->next_to_clean;
565}
566
567static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
568{
569 return readl(base + reg);
570}
571
572static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
573{
574 u8 __iomem *reg_addr = READ_ONCE(base);
575
576 writel(value, reg_addr + reg);
577}
578
579static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev)
580{
581 return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET ||
582 ae_dev->reset_type == HNAE3_FLR_RESET ||
583 ae_dev->reset_type == HNAE3_VF_FUNC_RESET ||
584 ae_dev->reset_type == HNAE3_VF_FULL_RESET ||
585 ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET));
586}
587
588#define hns3_read_dev(a, reg) \
589 hns3_read_reg((a)->io_base, (reg))
590
591static inline bool hns3_nic_resetting(struct net_device *netdev)
592{
593 struct hns3_nic_priv *priv = netdev_priv(netdev);
594
595 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
596}
597
598#define hns3_write_dev(a, reg, value) \
599 hns3_write_reg((a)->io_base, (reg), (value))
600
601#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
602 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
603
604#define ring_to_dev(ring) ((ring)->dev)
605
606#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
607 DMA_TO_DEVICE : DMA_FROM_DEVICE)
608
609#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
610
611#define hnae3_buf_size(_ring) ((_ring)->buf_size)
612#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
613#define hnae3_page_size(_ring) (PAGE_SIZE << (u32)hnae3_page_order(_ring))
614
615
616#define hns3_for_each_ring(pos, head) \
617 for (pos = (head).ring; pos; pos = pos->next)
618
619#define hns3_get_handle(ndev) \
620 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
621
622#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
623#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
624
625#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
626#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
627
628void hns3_ethtool_set_ops(struct net_device *netdev);
629int hns3_set_channels(struct net_device *netdev,
630 struct ethtool_channels *ch);
631
632void hns3_clean_tx_ring(struct hns3_enet_ring *ring);
633int hns3_init_all_ring(struct hns3_nic_priv *priv);
634int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
635int hns3_nic_reset_all_ring(struct hnae3_handle *h);
636netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
637bool hns3_is_phys_func(struct pci_dev *pdev);
638int hns3_clean_rx_ring(
639 struct hns3_enet_ring *ring, int budget,
640 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
641
642void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
643 u32 gl_value);
644void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
645 u32 gl_value);
646void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
647 u32 rl_value);
648
649void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
650int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags);
651
652#ifdef CONFIG_HNS3_DCB
653void hns3_dcbnl_setup(struct hnae3_handle *handle);
654#else
655static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
656#endif
657
658void hns3_dbg_init(struct hnae3_handle *handle);
659void hns3_dbg_uninit(struct hnae3_handle *handle);
660void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
661void hns3_dbg_unregister_debugfs(void);
662#endif
663